SU1651299A1 - Video information concurrent processing block - Google Patents

Abstract

The invention relates to computing technology, allows performing digital two-dimensional convolution and sliding histogram alignment over two-dimensional digital fields (in particular, images) and can be used in the construction of specialized real-time computing systems. The aim of the invention is to improve the performance of the device by fully parallelizing the computational process. For this, each k device group contains (2L-H) computing blocks, each of which has a multiplier and an adder. 4 il. Ј5 ®

Description

The invention relates to computing technology, allows performing digital two-dimensional convolution (1-CS) and sliding histogram alignment (CSH) operations on two-dimensional digital fields (in particular, images) and can be used in the construction of specialized computer systems operating in real life. timescale.

The aim of the invention is to improve the performance of the device.

Figures 1 and 2 depict a general functional diagram of the device} Fig. 3 is a functional diagram of an arithmetic unit; 4 is a functional block diagram of the control unit.

The device for parallel processing of video information contains an input switch 1, the first 2 and the second 3

delay lines, 2K + 1 group of 2L + 1 computational blocks 4.1.1; 4.1.2,

4.1.2L + 1, 4.2.1, 4.2.24.2.2L-H,

4.2K + 1.4.2K-H.2 ,. .., 4.2K +;. 2L + 1, control block 5. Each 1st computing unit of the kth group 4k.1 contains the first switch 6.k.l, the input register 7.k.l, the trigger 8.k.l, the second switch 9.k.l, the multiplier lO.k.l, and the arithmetic block ll.k.1. Each arithmetic unit ll.kl contains the adder 12.kl, the first I3, kl and the second 14.kl switches, the key 15 kl, the counter 16 kl, the result register 17.kl, the first 18.kl and the second 19, kl information inputs and output 20.k ".l, The device also has the first 21 and second 22 information inputs, information output 23, input 24 of the job setting" & ,

you, input 25 of the initial setup and input 26 of the sequence of clock pulses.

The control unit contains a group of outputs 27-30, output 31, which is the control output of the device, a group of outputs 32-35, block 36 of microprogram control, block 37 of microprogram memory, register 38 microcommand, first 39, second 40, third 41 and fourth 42 decoders, the first 43 and second 44 groups of elements OR.

The device works as follows.

Sliding alignment of the histogram of the distribution of digital signal values is that each value of the digital signal x (n, m) of the input array of samples X (N, M) is transformed according to the histogram Hn ", (c) constructed over a certain neighborhood of the signal x (n, m) (part of the image), consisting of G elements, in accordance

formula formula

X (PT)

H (s). (ABOUT

y (n, m)

Formula (1), taking into account the rectangular- ™ of the image area consisting of. (2K + 1) (2L + 1) samples, in which the Hnrn histogram is evaluated, can be replaced by the formula

2km 2lh. , 5 RG / 35

U (n, sh) - 7mn72L + TTA-L P (2K + 1M2L + 1) -k + k-1, m-L + l-l) Ј x (n, m) l,

(2)

where n K + l, N-K; m L + l, M-L;

l.-i JO if S ubj - | ls if a $ b.

y (n, m) is the normalized result

transform. A device for parallel processing of video information calculates an unnormalized result of an FGH according to the formula IM 2L-H

y (n, m) Z IE- & Gx (pK + k-1, m-L + her L

+ 1-1) x (n, m) J, (3)

where n K + l, N-K; m L + l, M-L;

{Oh, if 1. if

y (n, m) is an unnormalized result of the transformation.

i The relationship between the normalized and unnormalized conversion results is determined by the formula

v (n m) 1 - ZlSiSl. . g / and

Y n, m; i (2K + I) (2L + I)

When using CSF, the conversion results are normalized in an external device.

The DDS operation of the x (n, m) signals of the input X-array of samples (N, M) with weighting factors ({) (and, 1) of the array w (2K + l, 2L + 1) is defined by the formula 2fc + l 2L-I-I

z (n, m) ZI 21 W (k, l) x (nk + 1, 1

m-1 + 1), (5)

where n 2K + 1, N; m 2L + 1.M;

z (n, m) is the result of the conversion.

The mode of operation of the device is determined by the level of the signal coming from the external device at the input 24 of the device operation task. If the signal level is high, a DDS operation is performed; otherwise, an AEL.

The input 25 of the initial installation of the device from an external device receives a signal on which the micro-command register 38 is set to the zero state. With the arrival of the next sync pulse / zero cycle of the device operation at input 26, the block of firmware control 36 corresponds to the signal level at input 24 setting the operation mode of the device generates a start address at which the first microcommand that manages the execution of the DPC or CB operation is read from the microprogram memory block 37. G. The memory of the firmware 37 is conventionally divided into two parts: one is used when performing the operation of the DPL, the second is the CSA. The micro-command read is fed to the input of the micro-command register 38. With the arrival of the next clock pulse at the input 26 of the sequence of clock pulses (the first cycle of the device), the read micro-command is written to the micro-command register 38, partially decrypted using decoders 39-42 and groups 43 and 44 of the OR elements and goes to other nodes of the device. The choice of the next microcommand is provided by the fifth group of register bits 38 microcodes

Mandates 38. Thus, the micro-command code is read from the memory of the program 37 programmed for a clock cycle before it is executed. When performing the DPC operation, the fifth output 31 of the control unit ensures that weights are received from the external device via the first information input 21 of the device

2996

The total rows of the input sample array are 4L + 2 samples, from which the latter is not processed by the device.

During the initial movement of the input samples x (n, ra) Ј lines 2 and 3 delays, the contents are input. the registers 7.kl does not change, B is available in terms of C0 {1,1), 60 (1,2), ..., 6E (1, laziness of the input sample x (1,1) in -1), 03 (2.1), ..., OH2-2L + I), 63 (2K + last k (2L + l) ijth register of the first line

+ 1.1), CO (2K + 1.2), ..., CO (2K + I.2L-H). The control unit 5 generates signals for the input switch 1, the first switches 6.R.1 and the input registers 7.kl, which record the weights that come in the given order, respectively, into the input registers 7.1.1,7.1.2., .. ,, 7.1.2L + 1, 7.2.1,7.2.2 ....., 7.2.2L + 1, ... 7.2K + 1.1.7.2K + G, 2, .. ,, 7.2K + 1.2L +. The change in the signal level at the fifth output 31 of the control unit at the moment of the arrival of the last weighting factor causes the arrival, beginning with the next clock cycle, from the counting input (n, ha) from the external device. The input samples x (n, m) are transmitted via two information inputs 21 and 22 of the device, and the first information input 21 of the device receives the samples x (n, m) odd rows of the input sample array X (N, M), and the second information input 22 devices receive samples of x (n, tn) even lines. The input samples arrive at the speed of one sample per clock for each information input 21 and 22 of the devices, starting from the first information input 21 of the device, respectively on the first 2 and second 3 delay lines. The length of each transmitted input sample line is 4L + 1 samples. The time delays in the arrival of the next even row of the input array of samples are relatively odd and odd relative to the even one and are 2L + 1 cycles. Thus, after each line of the input array has a length of 4L-H samples, information input 2 or 22 devices one clock cycle does not transmit the input information. Any information on this information input 21 or 22 in this cycle is not processed by the device. Therefore, to simplify the circuits that provide a sample of x (n, m) samples in an external device, the length of the transmission 15

20

25

thirty

2 delays, the control signal at the third output 29 of the control unit sets all the controllers Skl to the initial (single) state, and also sent the first commutators 6, kl to other registers 7..1., 7.1.2, ..., 7.I.2L + 1, 7.2.1, 7.2.2, ..., 7.2, П-Н, .. ..7.2К + 1.), 7.2К + .2, ... 7.2K + 1.2L + form a ring. With the arrival of the next sync pulse, you start populating the VTS operation. Each time the next synchronization signal arrives at the synchronization inputs of input registers 7.U.1, information is shifted (weights) along the ring formed by these registers. Similarly, when the next synchronizing signal arrives at the synchronization inputs of the trigger 8, kl information located in the trigger 8, kl, it is transmitted along the ring formed by these trgges, each trigger 8.k.2L + l (except for k 2K-H ) transmits information with inversion to the information input of the trigger 8A + 1.I. Trigger 8. 2K +, 2L + transmits information with inversion to the information input of the trigger 8.1.1. The direct output of the trigger Skl controls the operation of the second switch 9.kl, and if the forward output of the trigger Skl has a low logic level, then the corresponding second switch 9 "k, l transmits the information from its first input, if it is high, then from the second the entrance. In parallel, in all computing blocks 4.k.l devices multipliers I0.k. 1 form the product of samples x (n, ir) arriving at the first input of the second switches 9, k.l, with corresponding weighting factors amn u) (k, 1) stored in the input registers 7.k.l. The formed products arrive at the first input 1 of S.k.l arithmetic units. 3 each arithmetic unit M.k.l for (2K + 1) to (2Ь + 1)

40

45

50

55

2996

The total rows of the input sample array are 4L + 2 samples, from which the latter is not processed by the device.

During the initial movement of the input samples x (n, ra) Ј lines 2 and 3 delays, the contents are input. of registers 7.k.l does not change, the moment of accessing the input sample x (1,1) to the last k (2L + l) ijth register of the first line

five

0

five

0

The 2 delays, the control signal at the third output 29 of the control unit, sets the entire Sklgger Skl to the initial (single) state, and also sent the first Commutators 6, kl to other registers 7..1., 7.1.2 ,. .., 7.I.2L + 1, 7.2.1, 7.2.2, ..., 7.2, П-Н, .. ..7.2К + 1.), 7.2К + .2, ... 7.2 K + 1,2L + form a ring. With the arrival of the next sync pulse, the direct injection of the VTS operation begins. Each time the next synchronization signal arrives at the synchronization inputs of input registers 7.U.1, information is shifted (weights) along the ring formed by these registers. Similarly, when the next synchronizing signal arrives at the synchronization inputs of the trigger 8, kl information located in the trigger 8, kl, it is transmitted along the ring formed by these trgges, each trigger 8.k.2L + l (except for k 2K-H ) transmits information with inversion to the information input of the trigger 8A + 1.I. Trigger 8. 2K +, 2L + transmits information with inversion to the information input of the trigger 8.1.1. The direct output of the trigger Skl controls the operation of the second switch 9.kl, and if the forward output of the trigger Skl has a low logic level, then the corresponding second switch 9 "k, l transmits the information from its first input, if it is high, then from the second the entrance. In parallel, in all computing blocks 4.k.l devices multipliers I0.k. 1 form the product of samples x (n, ir) arriving at the first input of the second switches 9, k.l, with corresponding weighting factors amn u) (k, 1) stored in the input registers 7.k.l. The formed products arrive at the first input 1 of S.k.l arithmetic units. 3 each arithmetic unit M.k.l for (2K + 1) to (2Ь + 1)

0

five

0

five

71

The work cycles accumulate (sum up) the product, and once in (2K-H) tf (2L + l) cycles, the next result of the VDS operation, generated in the 4.k.l computing unit, is transmitted to the information output 23 of the device.

In the CBP operation, the fifth output of the 31-control unit provides the input from the external device, via the first information input 21, of the device single signals, which are written into the input registers 7.k.l and rewritten into the register of the second multiplier multipliers lO.k.l. The change in the signal level at the fourth output 30 of the control unit, after recording the single signals in the second multiplier register all multipliers lO.kl, causes the multipliers lO.kl to transfer their data to their outputs entrances. A change in the signal level at the fifth output of the control unit 3 at the moment of the arrival of the last single signal causes the input, starting from the next clock, of the input samples x (n, m) from outside the device. The method and order of their arrival is the same as in the operation of the CSR. At the moment the input x (3.1) arrives at the last JJK. (2L +) -L-lJ-ft register of the first delay line 2, the control signal at the third output 29 of the control unit sets all the triggers 8, k.l to the initial unit state. With the arrival of the next sync signal, the direct operation of the CSG begins. Similarly, as in the case of performing the VDS operation, the triggers 8.L.1 form a ring, along which with the arrival of the next sync pulses the information shifts. With a delay per clock relative to the start of the direct execution of the operation of the FHD, all the first switches 6.kl begin to transmit information from their second input to the input of the corresponding input registers 7.k, 1. At the same time, the input switch 1 starts to transmit information from the first (with even K) or from the second (for odd K) input to the second inputs of the first switches 6.1c. (Further, the input switch 1 transmits information to the second inputs

eight

0

five

0

50

five

0

five

five

first switches 6.kl then from the first, then from the second one of their inputs with a period of 2L + 1 cycles). The operation of the input switch 1 and the first switches 6, kl allows you to select and write to the input registers 7.U.1 the central elements of the image sections . In parallel, in all arithmetic units ll.k.l of the device, a subtraction operation is performed (the next element of the section is subtracted from the central element of the section), and the result sign is added to the contents of the 16.k.l counter. Once a time (2K + 1) x x (2L + i) cycles the next result of the operation of the CSA. formed in the computing unit ll.k.l is transmitted to the information output 23 of the device. Every (2K + 1) x (2L + l) cycles in the input register 6.k.l a new central element of the image section is received.

Signal control unit for other device nodes. The low logic level at the first output 27 of the control unit corresponds to the transfer of information from the first input switch 1 to its output, otherwise from the second input. A low logic level at the second output 28 of the control unit corresponds to the transfer of information from the first inputs of the first switches 6.k.l to their inputs, otherwise - from the second inputs. A high logic level at the third output 29 of the control unit sets all the triggers S.k.l to one. A high logic level at the fourth output 30 of the control unit will allow information to be written to the second multiplier of all multipliers lO.k.l, otherwise, write prohibition. A high logic level at the fifth output 31 of the control unit corresponds to the receipt of input samples x (n, m) in the next clock cycle in a parallel video processing device. A low logic level at the control output 31 of the device provides psdachu in the next cycle to the first information input 21 of the device of the weighting coefficients C0 (k, l) in the case of performing DDS and single samples in the case of performing the CSA operation. In order to save the memory of the firmware 37 and taking into account the specifics of the calculations, decoders 39-42, per10 are used.

15

20

91651299 10

WA 43 and the second 44 groups of elements OR. A high logical address on one of the outputs of the first group of outputs 32 of the control unit allows the recording of information in the corresponding input register 7.k.l, otherwise - the prohibition of recording. During the operation of the device, information can be written to all input registers 7.R.1 simultaneously, to each input-, NOW register 7.k.l separately and not written to any input register 7.k.l. Consequently, the number of bits in the first group of bits of the register of 38 microinstructions for coding these situations is flog (2K + I) x (2L + 1) parallel.

For example, combinations of 00.0 and

111 are decrypted accordingly.

as a ban and receiving information about all input registers 7.k.l3 00 .... 00, 00 ..,. 010, etc. - receiving information, respectively, only in the input register 7.1.1, 7.1.2, etc. At a high logic level, at one of the outputs of a group of outputs 33 of a control unit connected to the second control input of the adder 12, kl, and at a high logic level at the first 30 control input (performance of the DDS operation), this adder 12.kl performs transfer to its output operand arriving at its first input. During the operation of the device, each output device 23 of the device 12, adder 12.k, l arithmetic coincides. The number of bits in a block can, separately, perform the fourth group of register bits transmitting to the output of the operand, the arrival of micro-commands 33 (2K + l) (2L + I). on his first entrance. The following combinations are 00 ... 001, 00 ... 010, the number of bits in the second is 40 and causes a high logical group of bits of the register of the 38 microcircuit, respectively, on the first one, the second flog r. C (K + 1 ) (2L + 1) i. For example, combinations 00 .... 01, 00 .... 010, etc. correspond to the implementation, respectively, of adders 12.1.1, 12.1.2 d5, etc. transmissions to their outputs of operands arriving at their peo inputs. At a low logic level, the first control input of the accumulator 12.k.l (performing the CSA operation) and regardless of the information at its second control input (the second group of outputs 33 of the control unit), the adder 12.R.1 performs the subtraction operation. A high logic level at one of the outputs of the third group of outputs 34 of the control unit causes the mode of parallel recording of information into the corresponding counter 16.U.1 and

transmission through the corresponding class. 15. To the sequence of clock pulses. With a low logic level, which detects the third group of outputs - 34 of the control unit, the 16.k.l counter operates in the counting mode, and the 15.K.1 key, depending on the signal level at its first control input, transmits or does not transmit a sequence of clock pulses. The number of bits in the third group of register bits is 38 micro-instructions (2K + l) (2L-H) + ffj. For example, a combination of bits 00O corresponds to high logic levels on all outputs of the third group of outputs 34 of the control unit, and the combination

00 ..., 00, 0.010, etc. there is a high logic level, respectively, on the first, second, etc. . the outputs of the third group of outputs 34 of the control unit. A high logic level on one of the outputs of the fourth 25 group of outputs 35 of the control unit calls up the result in the corresponding result register 17.k.l and outputs the result to the output 20.k.l of the arithmetic unit. The remaining result J7.k.l of the result receives a low logic level, which ensures the third state (high resistance) of their outputs. Thus, the information at the output 20.k.l of the arithmetic unit and

50

rum, etc. exits.

Further assume that.

For a DPC operation, consider the formation of an arbitrary reference defined by the expression h

, m) SL§LU (k, l) x (nk + I (m-l + i) "

k-i e «i з

 51 Ј (3, l) x (n-2, m-l + 1) +

55

t

+ iEL G3 (2, l) x (n-l, m-l + l)

.

+, l) x (n, m-l-H

C i

4- (n, m) + zf (n, m),

z (n, m) +

where 2K + 1 3 Ј n N,

 2L-H 3 & m & 5 4L + 1,

0

five

0

0 5 formational output 23 of the device is the same. The number of bits in the fourth group of bits of the register of micro-commands is 33 (2K + l) (2L + I). The combinations 00 .... 001, 00 ... 010 0 and cause a high logic level, respectively, on the first, second, 5

transmission through the corresponding class. 15. To the sequence of clock pulses. When the logic level is low, which is g of the third group of outputs - 34 of the control unit, the 16.k.l counter operates in the counting mode, and the 15.K.1 key, depending on the signal level, on its first control input transmits or does not transmit a sequence of sync pulses. The number of bits in the third group of register bits is 38 micro-instructions (2K + l) (2L-H) + ffj. For example, a combination of bits 00O corresponds to high logic levels on all outputs of the third group of outputs 34 of the control unit, and the combination

00 ..., 00, 0.010, etc. there is a high logic level, respectively, on the first, second, etc. . the outputs of the third group of outputs 34 of the control unit. A high logic level on one of the outputs of the fourth 5th group of outputs 35 of the control unit calls up the result in the corresponding result register 17.k.l and outputs the result to the output 20.k.l of the arithmetic unit. The remaining result J7.k.l of the result receives a low logic level, which ensures the third state (high resistance) of their outputs. Thus, the information at the output 20.k.l of the arithmetic unit and

30 35 formational output 23 of the device is the same. The number of bits in the fourth group of bits of the register of micro-commands is 33 (2K + l) (2L + I). Combinations 00 .... 001, 00 ... 010 40 and cause a high logic level, respectively, on the first, second, 5

50

rum, etc. exits.

Further assume that.

For a DPC operation, consider the formation of an arbitrary reference defined by the expression h

, m) SL§LU (k, l) x (nk + I (m-l + i) "

k-i e «i з

 51 Ј (3, l) x (n-2, m-l + 1) +

five

t

+ iEL G3 (2, l) x (n-l, m-l + l)

.

+, l) x (n, m-l-H

C i

4- (n, m) + zf (n, m),

z (n, m) +

formational output 23 device matches. The number of bits to the fourth group of bits of reg micro-commands 33 (2K + l) (2 Combinations 00 .... 001, 00 ... 01 and cause a high logical level, respectively, on the first

where 2K + 1 3 Ј n N,

 2L-H 3 & m & 5 4L + 1,

one

with this, the device processes samples x () of the input array that satisfy the conditions

1 ЈriЈN, lЈm Ј 5 4L + 1. The input count x (n, ha) comes in tact with the number-R (n, m) (2K + I) (2L +

-t-Ol O (2L + i) + L-Q + Ј (2L + i) (n-i) + m

 12 + 3 () - hn from the first delay line 2, (for odd n) or from the second delay line 3 (for even n), respectively, to the first and second inputs of the second switches 9.U.I.

The formation of reference 2 (pt) occurs in the computing unit 4.p.t where p is the group number determined from the relations

13;

n + l5p (mod (2K + l)

t - block number, ratios

1 Јt 2L + 1 3;

m + 1 - t (inod (2L + l) 3).

The formation of the count r (n, ta) in the computing unit 4, pt begins in the cycle with the number s R (n-2K., M-2L) R (, m-2) 12 - «- 3 (n-3) + m-2.

Define the function

f 0 if (e) a

 3)

definable of

- odd

I if e is even

one

The state of the trigger S.p.t in the formation of a reference is written using the function (e).

The work of the arithmetic unit ll.p. during the operation, the VDS can be described with the help of three micro-operations A1, A2 and A3, the duration of which is one device operation cycle. A high logic level from the output of the third group of outputs 34 of the control unit is supplied respectively to the control input of the counter 16.p.t and to the second control input of the key 15.p.t. The IG.p.t counter operates in the parallel information recording mode, and the IS.p.t key sends to the counting input of the I6.p.t counter a sequence of clock pulses, incoming and information input of the IS.p.t. key. The low logic level coming from the fours of the output control group 35 of the control unit to the control input of the result register 17.p.t transfers its output to the third high-impedance state, otherwise this peiistr outputs the output 20.p.t arithmetically

ten

15

20

25

35

45

. 65129912

unit and, therefore, the information output device 23 generated result. According to the high logic level of the signal at the input 24, setting the operation mode of the device, the first 13, p.t and second 14.p.t switches of the arithmetic units transmit information to their outputs from their second and first inputs respectively. A high logic level at the input 24 of the device operation mode setting also enters the first control input of the adder 12.p.t. The arithmetic block ll.p.t, depending on the logic level of the signal at the second control input of the adder 12.p.t and on the logic level of the signal at the control input of the result register 17.p.t, performs microoperations Al, A2 and A3.

Microoperation A1 Starting the formation of a new result corresponds to a high logic level at the second control input of the adder 12.p.t and a low logic level at the control input of the result register 17.p.t. The generated result with the arrival of the next sync pulse is received in the counter 16.p.t and is fed to the input of the register 17.p.t of the result, the output of which is in the third high-resistance state. The operand arriving at the first input IS.p.t of the arithmetic unit through the adder 12.p.t and the first input of the second switchboard 34.p.t of the arithmetic unit enters the input of the parallel reception of the counter 16.p.t.

Micro-operation A2 Summation corresponds to a low logic level at the second control input of the adder 12.p.t and a low logic level at the control input of the result 17.p.t register. With the arrival of the next clock pulse, a partial result is received at the counter 16. pt and is fed respectively to the input register 17. pt of the result and through the second input of the first IS.pt switchboard arithmetic unit to the second input of the adder 12, pt, which performs the operation of summing with the operand arriving at his first entrance. The result of summing through the first input of the second switch 14.p.t of the arithmetic unit is fed to the input of the parallel reception of the counter 16.p.t. Register output

thirty

50

55

T7.p, t of the result is in the third high-resistance state.

Microoperation A3 Summation and output of the result corresponds to a low logic level at the second control input of the adder 12.p.t and a high logic level at the control input of the result register 17, p.t. With the arrival of the next sync-JQ ro-pulse, the generated result is accepted into the result register 17.p.t and arrives at the output 20.p.t of the arithmetic unit. The operand arriving at the parallel clock input to the parallel reception of the 16.pt counter is taken into this counter and fed through the second input of the first switch 13.pt of the arithmetic unit to the second input of the adder 12.p.tt which ro performs the operation of summing with arriving at his first entrance. The result of the summing through the first input of the second switch 14.p.t of the arithmetic unit is fed to the 25th input of the parallel receiving counter 16.p.t.

For an SVG operation, we consider the formation of an arbitrary reference y (n, m) defined by the expression30

33

Y (n, tn) Z- (n + k-2, m + l-2)

x (n, m)), x (n, m)) +

Ј (x (n-l, m + lT2) (x (n, m + l-2) 35

3

x (n-m)) 4-21 (x (n + l, m + l-2)

e t. x (n, m)) y3 (n, m) + y4 (n, m) +

+ y (n, m),

where K + l-2 Ј n Ј N-K N-l, while the device processes samples x (njHi} of the input array that satisfy the conditions

40

45

1 n N;

Јiu G 5 4L + 1.

The input count x (n, ha) arrives in the cycle with the number p (n, m) (2K + l) xx (2L + iy - - (2L-H) (nl) Vm 9 + 3 (n-1) - Ip at the first 21 (for odd n) or at the second 22 (for even n) information input of the device. The definition of the ticker with the number R (n, m) is the same as in the case of the DPS operation.

The formation of the reference y (n, m) occurs in the computing unit 4. R. t,

Jq about 5

0

five

0

five

U

five

where p is the number of group control, determined from the ratios

  2K-H 3;

 p (mod (2K + l) 3),

at - block number, determined from ratios

1 6L Ј-. 2L + 1 3s

m-L tp-1 n t (mod (2L + I)).

The formation of the counting y (n, m) in the 4.p.t computational block starts in the cycle with the number s R (n-K, m-L) R (n-l, m-l) 12 + 3 (n-2) + m-l. The definition of the function L (e) is similar to

in case of a VTS operation. i

The operation of the arithmetic block ll.p.t in performing the operation of an SVG will be described with the help of two microoperations В1 and В2, the duration of which is one tact of the device operation. By the low logic level of the signal on the pkho / de 24 setting the operation mode of the device, the first IS.pt and the second 14.pt switches of the arithmetic units transmit information to their outputs from their first and second inputs, respectively, and the adder 12.pt regardless of the logic level on the second control input performs the subtraction operation (from the operand arriving at the second input of the adder 12.pt, the operand arriving at its first input is subtracted). The low logical level coming from the fourth group of outputs 35 of the control unit to the control input of the result register 17.pt transfers its output to the third high-resistivity state; otherwise, this register outputs to output 20.p, t 1 arithmetic unit and, therefore, the information output device 23 generated result. The low logic level coming from the third group of outputs 34 of the control unit, respectively, to the second control input of the key 15.pt and the control input of the counter 16.pt, causes the counting mode of the counter to 16.pt, and the key IS.pt depending on the state its first control input skips (or does not skip) sync pulses to the count input of the I6.pt counter. With a high logic level coming from the third group of outputs 34 of the control unit, the counter 16.p, t operates in the parallel information recording mode, and the key

15

IS.p.t transmits to the counting input of the counter 16.p.t Clock pulses. The arithmetic unit ll.pt, depending on the logic level at the control input of the output register 17.pt and the logic level, respectively, of the counter 16.p, t and the second control input of the IS.pt key, performs the microoperations B1 or B2.

Micro-operation B1 Vstascha and the beginning of the formation of a new result is determined by a high logic level, respectively, on the control input of the result register I7.p.t, the control input of the counter 16.p.t and on the second control input of the key 15, p.t. With the arrival of the sync pulse, the generated result is accepted into the result register 17.p.t and outputted at the output 20.p.t of the arithmetic unit, the counter 16.p.t receives the information that arrives at its parallel receive input. The adder 2.p.t subtracts from the operand (the central element of the image portion) coming from the second input 19.p.t of the arithmetic unit, the operand coming from the first input IS.p.t of the arithmetic unit (the next element of the image portion). The sign of the subtraction operation goes to the first control input of the IS.p.t key and the last digit of the second input of the second I4.p.t switch of the arithmetic unit.

Micro-operation B2 Comparison is determined by a low logic level respectively at the control input of the output register 17.p.t, the control input of the counter I6.p.t and at the second control input of the key IS.p.t. With the arrival of the sync pulse, the partial result is received in the result registrar 17.pt, the output of which is in the third state, the counter 16.p, t, depending on the sign of the previous subtraction operation going to the first control input of the IS.pt key, increases by one ( or does not increase, if the sign of the one’s subtraction is positive) its state. The adder 1.2.p.t subtracts from the operand (the central element of the image section) coming from the second input 19.p.t of the arithmetic unit, the operand coming from the first input IS.p.t of the arithmetic unit

jQ

129916

The ka (the next element of the image section), the sign of the subtraction operation goes to the first control input, the key IS.p.t and the last bit of the second input of the second switch 14.p.t of the arithmetic unit.

The number of elements in the column (respectively, in the row) of the image area being processed can be an even number. However, in this case it is necessary to determine which of the two (or four) elements located closest to the center of the image,

 is the central element of the plot. From this choice are dependent for the first 2 and second 3 delay lines. Increased performance is achieved by full parallelization.

2Q of the computational process, as well as improved organization of calculations in the arithmetic units of the device during the performance of the SVR operation. A device containing C2K + 1) x (2L + l) numeral blocks forms each new output count in each new key.

0

five

0

five

0

five

Claims (1)

Invention Formula A parallel video processing device containing an input switch, a control unit and the first computing unit of each k-th device group (, 2K + l), where 2K + 1 is a number equal to the number of elements in the column of the image section being processed, each computing unit contains arithmetic the block and the multiplier, the output of which is connected to the first input of the arithmetic block, characterized in that, in order to increase productivity by fully parallelizing the computational process, The first and second delay lines are given, each is in K (2L +) registers, where (2L + 1) is a number equal to the number of elements in the row of the image section being processed, and each k- device group contains 2L computational blocks (respectively, with numbers 2, 3, ... 2L + 1), with the 1st computing unit (1 1.2L + 1) of the k-th group containing the first and second switches, the input register) and the trigger, and the arithmetic unit of the 1st b kok group contains per the second and second switches of the arithmetic unit, the key, the adder, the counter and the result register; moreover, in the arithmetic unit of the 1st ko block: 4 groups, the first input of the arithmetic block is connected to the first input to the sum of the torus, the sign bit of which is respectively connected to the first control the key input, with the first bit of the first input and from the heading, with the bit of the second input of the second switch of the arithmetic unit, the outputs of the remaining digits of the adder from the higher bit to the younger one are connected respectively from the second to the last the bits of the first input of the second switch of the arithmetic unit, from the first to the last bits of the second input of which are connected to the logic zero level of the block, the outputs of the second switch of the arithmetic block and key are connected respectively to the inputs of the parallel reception and to the counting input of the counter, the output of which is connected respectively to the input the result register and the second input of the first switch of the arithmetic unit, the first input of which is the second input of the arithmetic block, the output of the first switch a If the chemical unit is connected to the second input of the adder, the output of the result register is the output of the arithmetic unit, the outputs of the second and first switches of the 1st block of the k-th group are connected respectively to the first input of the multiplier of the 1st block of the k-th group k with the input of the input register The 1st block of the k-th group, the output of which is connected respectively to the second input of the multiplier of the 1st block of the k-th group, to the second input of the arithmetic block of the 1st block of the k-th group and to the first input of the first switch (1 + 1) -th block of the k-th group (except for 1 2L + 1), the output of the input p The registrar (2L + l) -ro of the k-th group block is connected to the first input of the first switch of the first block (k + 1) -th group (except k 2K-H), the output of the input register (2L + I) ro block (2К- And the) group is connected to the first input of the first switch of the first block of the first group, the direct output of the trigger of the 1st block of the k-th group is connected respectively to the control input of the second switch of the 1st block of the k-th group and to the information input of the trigger ( 1 + 1) ten 15 20 25 zo 35 40 45 50 five the block is the k-th group (except for 1 2L + I), the inverse trigger output (2L + l) -ro of the k-th block of the group is connected to the information WUOD trigger of the first block (k + 1) -th grupp (except for 2K + 1 ). the inverse trigger output (2L + l) -ro of the block (2K + 1) group is connected to the information input of the trigger of the first block of the first group; the first information input of the device is respectively connected to the input of the first delay line and the first input of the input switch, the second information input of the device respectively connected to the input of the second delay line h by the second input of the input switch, the output of which is connected to the second input of all the first switches, the outputs of the first and second delay lines are connected respectively by the first second h in The signals of all the second switches, the outputs of all the arithmetic units of the device are bit-wise combined and are the information output of the device, the input of the device operation mode is connected to the first input of the control unit, respectively, with the control input of all the first switches of the arithmetic units, to the first control input of all adders and with the control input of all the second switches of the arithmetic units, the input of the initial installation of the device is connected to the second input of the control unit, the input of the sequence pulse pulse J is connected to the third input of the control unit, respectively, with the information input of all keys and the synchronization inputs of the first and second delay lines, all input registers, all triggers, all multipliers and all result registers, respectively; first, second, third and fourth outputs the control unit is connected respectively to the control input of the input switch, to the control input of all the first switches, to the installation input of all triggers and to the write enable input to the second factor multipliers, a fifth output of the control unit is a control output of the apparatus, the first and second outputs of the control unit group are connected respectively to the input resolution recording all input registers and a second control input of all summato-. The third group of outputs of the control unit is connected respectively to the second control input of all the keys and to the control input of all counters, the fourth group of outputs of the control unit is connected to the control the input of all result registers, each (K-1) (2L + 1) output by a card of the output group of the control unit is connected to the corresponding input of the 1st block of the k-th device group. FIG. one 18l1 FIG. 2 W.K.I FI.3 z # 3 25 25 Figm