SU1229754A1 - Arithmetic unit - Google Patents

Abstract

The invention relates to computing and can be used to build conveyor information processing means. The purpose of the invention is to increase productivity in a conveyor mode. The essence of the invention is that the device comprising an adder, a multiplier, three buffer registers, two multiplexers, further comprises six multiplexers, two delay blocks, four tuning registers, a structure code register, three shift registers, a tuning delay counter, a decoder for the counting module, trigger, shaper of the start-up delay code, training sequence block, two blocks of modifying sequences, comparison circuit, addend blocking circuit, blocking circuit eating, AND gate, OR gate, AND gate NOR, and inverter drive with distinctive settings bonds. 2 Il. S Yu Yu with 01 4ib

Description

The invention relates to computing and can be used to construct conveyor processing means.

The purpose of the invention is an increase in productivity in a conveyor belt.

FIG. 1 shows a diagram of an arithmetic unit; in fig. 2 - time diagram of work.

The arithmetic unit contains an adder-subtractor 1, multiplier 2, switch 3, multiplexer 4, switch 5, multiplexer 6, switches 7-10, output 11 of the result, delay elements 1–2 and 13, output 14, block 15 prohibition elements, block 16 elements OR, input 17 of the setting code, block 18 of memory, settings registers 19-22, structure register 23, shift registers 24-26, counter 27, decoder 28, EXCLUSIVE OR 29, multiplexers 30-33, trigger 34, the element OR 35, the elements And 36 and 37, the element NOT 38, information inputs 39-41, the input 42 of the accompanying feature, the input 43 settings enable, 44 setup end inputs, 45 and 46 modifying feature inputs, typlexer 31 output 47, outputs 48-51 bits of multiplexer 30, inputs 52 and 53 of subtractor 1, outputs 54 and 55 of multiplier 2, output 56 of multiplexer 32 .

The adder-subtractor 1 and the multiplier 2 implement the pipeline method of performing operations, which implies the presence in them of intermediate (buffer) registers. The number of such registers from input to output in each of the blocks and 2 determines the own (logical) delay of these blocks. Multiplexers 46, 30-33, used in the device, have the encoding presented in table. 1-4, respectively.

0101010101010101

001 1001

001 1001 1 00001111

0000 I

001 1001 0000111

0000000001 1 1 1 1 I

Table I

Table 2

T a b l and c a 3

Control inputs

Multiplexer 31

Multiplexer 32

Register bits 25 coming out

Register bits 26 coming out

00 40

01 10

45 P

E is the supply voltage.

Table

001 1001 1 00001111

Information input coming out

E.

The arithmetic unit is intended to perform in the conveyor mode the operations described in table. five.

Table 5

Note. X, X, X data entering the inputs 39-41, S is the result at the output of the adder -calculator 1, + - addition or subtraction.

When the conveyor performance of these operations, the following options are possible for passing information through the device, defining its structure: device input-accumulator-reader device output, device input — adder-reader, “multiplier — device output, device input

Continuation of the table. And

E 29 27 27 E 29 29 E

ten

15

20

25

thirty

five

0

S

roiastva - multiplier - adder-calculator-output device; device input - device multiplier output.

Assign to these structures, respectively, the codes 0,1,2,3.

The installation of the necessary connections defining the device configuration is called a setting. In the setting process, it may be necessary to organize its delay for more than one clock period from the moment an external command was received from the input 43 of the setting resolution. This is possible. When the last element of the old structure becomes the first element in the new structure and in some other cases. At the same time, the beginning of the installation of the new structure is delayed by the number of cycles required to complete the processing of the elements in the old structure.

The setup of the device, depending on the operation being performed, is made by inputting to I7 a setup code. From its value, from memory block 18 to setting registers 19-22 in the sequence determined by the structure code, received by structure register 23 and converted into clock signals by multiplexer 30, control information is received, which specifies the necessary switching in multiplexers 4 and 6 and switches 3, 5, and 7, and also controls the mode of operation (addition or subtraction) of adder-subtractor 1, depending on the operation as per tab. 6

Adder 1

12297546

Tableb Multiplier 2

Output 1

Input 52 I Input 53

2 3 4 5 6 7 8 9

10 1 I 12 13 14 15 16 17

 M - the result of the output of the multiplier 2.

The proposed setting is called the delay delay adjustment, static.45 The value of delays is given in

In the transition from the old struk- table.7.

Tours to the new occurs Table 7

Old code

structures 0000

Code of the new structure

1 1 122223333 0123012301230123

About About About About L, About

Note,) - own delay, respectively, of the adder-subtractor and multiplier.

Itsab

Output 1

Input 54 I Input 55

S S CH g, S S O O O O O

The delay & is performed by the EXCLUSIVE OR, 29 element and multiplexer 33,

In case of equality of U and the contents of the striker 27 at the output of the multiplexer 33 logical unit.

At single values at the inputs 43 and 44, in this case, a negative pulse is generated at the inverse output of the E 37, which is set in register 23 with the code of the new structure and the first digit of the shift register 24 is entered, which determines the beginning of sequences.

Depending on the structure code, it transforms the sequence of the positions of the running unit in register 24 and the sequence of clock pulses that control the registers 19–22 in the construction site.

The data arriving at the inputs 39-41 form sequences. Within the same sequence, the static setting defined by the memory unit 18 is stored. To mark these sequences together with the data coming in on. one of the inputs 39-41, the input 42 receives a sequence of accompanying signs, with the help of which the beginning and end of the data sequence are distinguished. Since the result of processing at output 11, depending on the structure code, is held relative to the input data for different number of cycles, in order to preserve the correct marking of the output data sequence, delay elements 12 and 13 are inserted into the device, which, by means of appropriate switching, form for the sequence of accompanying signs The data conveyor composed of blocks 1 and 2. In this case, by the delay value, element 12 corresponds to adder 1, and element I3 to multiplier 2.

To change the setting in pro-. The process of executing a single command uses dynamic tuning based on the signals of inputs 45 and 46. These signals, like signal 42, form a sequence that is synchronous with one of the input data sequences. According to these signals, the delayed correspondence is in the image

five

About 5

0

typelexers 31 and 32, blocking the addendum arriving at the input of the adder from the output of multiplexer 4, or blocking the multiplier at the input of the multiplier from the output of the multiplexer 6. At the outputs of the blocks 15 and 16 elements, the arithmetic codes zero and one are valid. With the help of signals, modifications to inputs 45 and 46 provide a fairly wide variety of operations with a fixed static setting. The formation of the necessary delay of the output signals of the multiplexers 30 and 3 is carried out using the shift registers 25 and 26, respectively.

Consider the execution of y in the device. y + a. bj and the following expressions dl + q, favoring the time diagram (Fig. 2). The time t corresponds to the appearance at the input 43 of the permission to perform the first operation of the first expression. Since the device is in the initial state (at the input 44 a high level acts as a sign of the end of the previous operation), a start signal is generated without delay at the output of the element And 37, the trailing edge of which at the inputs 39 and 40 begins to receive data a and bj. At the same time, multiplexer 30 provides the following sequence of control signals at the inputs of switches 3 and 5 of multiplexers 4 and 6. Simultaneously with the first data pair, switching takes place at switch 5 and multiplexer 6, after two cycles, when the first product appears at the output of the multiplier 1, switching is performed at switch 3 and multiplexer 4 and. still after the clock, when the result appears at the output of the adder, the input in switch 7 is selected. At time t, input 43 receives the second permission to compute the new expression. Since the device is still occupied with the calculation of the previous expression, the calculation of the new expression is delayed. At time t, input 44 indicates that the sequence of data involved in the calculation of the first expression is terminated. Since the device still continues the calculation of the first dissolution, the structure switches at the moment t, i.e. the signal at the output of the AND 37 element is formed only two cycles after the appearance of the feature, after which the re-switching is performed in the switches 3, 5 7 and multiplexers 4 and 6 according to the code value of the new structure equal to one. In this case, the beginning of the execution of a new expression within two cycles takes place in parallel with the termination of the calculation of the old expression.

Formula of Invention

An arithmetic unit containing an adder-subtractor, a multiplier, a memory unit, four tuning registers, a structure register, two multiplexers, three switches, a shift register, a trigger, a block of bar elements, a counter, an element EXCLUSIVE OR, a decoder, and the first information input device is connected to the first information inputs of the first and second switches; the second information input of the device is connected to the first information inputs of the first and second multiplexers; the output of the first multiplexer is connected The output of the first switch and the output of the block of the inhibit elements are connected to the first and second information inputs of the subtractor, the output of which is connected to the second information inputs of the first and second multiplexers, the multiplier output is connected to the second information input of the first the switch and the third information input of the first multiplexer, the input of the device configuration code is connected to the address input of the memory block, the outputs of which are connected according to Twain to data inputs configuration registers of the first to fourth and the structure of the register, the outputs of the first and second bits of the counter are connected to inputs of the decoder, an output of first discharging the first configuration register coupled to the control input of the first kommuttora, the outputs of the second and third bits of the first configuration register

connected to the first and second control inputs of the first multiplexer respectively; the output of the first bit of the second tuning register is connected to the control input of the second switch; the outputs of the second and third bits of the second tuning register are connected respectively to the first and second control inputs of the second multiplexer; the output of the third The tuning register is connected to the control input of the adder-subtractor, characterized in that, in order to increase productivity in a conveyor mode of operation, it contains two delay elements, fourth to sixth switches, block of OR elements, second and third shift registers, two AND elements, NOT element, third to sixth multiplexers, with the third information input of the device connected to the fourth information input of the first multiplexer and the third information input of the second the multiplexer, the fourth information input of which is connected to the multiplier output, the second information input of the second switch is connected to the output of the adder-subtractor and the first information input p The second switch, the second information input, the control input and the output of which are connected respectively to the output of the multiplier, the output of the fourth setup register and the output of the device, the input of which is connected to the first information inputs of the fourth and fifth switches, the outputs of which are connected respectively to the inputs of the first and the second delay elements, the outputs of which are connected to the corresponding information inputs of the sixth switch, the control input and output of which with Connected respectively to the control input of the third switch and the output of the device sign, the outputs of the first and second delay elements are connected respectively to the second information inputs of the n - th switch and the fourth switch, the control inputs of which are connected respectively to the outputs of the fourth bits of the second and first setting registers, output n In addition, the first register setting is connected to

h

the first input of the OR element, the output of which is connected to the control input of the prohibition block, the output of the second multiplexer is connected to the information input of the block of OR elements, the output of which and the output of the second switch are connected respectively to the multiplier and multiplicative multiplier inputs, the outputs of the structure register bits are connected to the corresponding control inputs of the third multiplexer, whose information inputs are connected to the outputs of the corresponding bits of the first shift register, the output of the bits of the third meter An ultiplexer is connected to the so-called inputs of the respective tuning registers, the outputs of the first and second bits of the register are connected to the corresponding control inputs of the fourth and fifth multiplexers, the information inputs of which are connected respectively to the outputs of the bits of the second and third shift registers whose inputs are respectively, the first and second inputs of modifying device characters, the outputs of the fourth and fifth multiplexers are connected respectively to the second input of the IL element and a control input

2Ч7т412

the block of elements OR, the input of the end of the device Pasteur is connected to the first input of the first element AND and the input of the resolution resolution of the counter, the input

5 of the prohibition account which is connected to (ha -) - m output of the decoder (t is the counting module), the outputs of the first and second bits of the counter are connected to the corresponding inputs of the IC- to KEY OR element, the output of which and the output of the first digit of the counter are connected respectively to the first and second information inputs of the sixth multiplexer, the first and second

15 control inputs of which are connected respectively to the output and information input of the structure register, the output of the sixth multiplexer is connected to the second input of the first element I, the output of which is connected to the input of the trigger and the first input of the second element I, the second input and inverse output of which are connected respectively to the output trigger and clock

25 the input of the register of the structure, the input of the first shift register through the element is NOT connected to the inverse output of the second element AND, the third input of the first element AND is

30 input enable device settings.

L

ij

FIG. 2

Editor M. Bianar Order 2450/48

Compiled by A. Klyuev Tehred O. Gortvay

Proofreader S. Shekmar

Circulation 671. Subscription VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow,, Raushsk nab ,, d. 4/5

Production and printing company, Uzhgorod, st. Drive on,

Proofreader S. Shekmar

Claims (1)

Claim An arithmetic device comprising an adder-subtractor, a multiplier, a memory block, four tuning registers, a structure register, two multiplexers, three switches, a shift register, a trigger, a block of inhibit elements, a counter, an EXCLUSIVE OR element, a decoder, the first information input of the device being connected to the first information inputs of the first and second switches, the second information input of the device is connected to the first information inputs of the first and second multiplexers, the output of the first multiplexer is connected to the information input of the block of inhibit elements, the output of the first switch and the output of the block of inhibit elements are connected respectively to the first and second information inputs of the adder-subtractor, the output of which is connected to the second information inputs of the first and second multiplexers, the output of the multiplier is connected to the second information input of the first switch and the third information the input of the first multiplexer, the input of the device configuration code is connected to the address input of the memory block, the outputs of which are connected respectively with the information inputs of the setup registers from the first to the fourth and the structure register, the outputs of the first and second bits of the counter are connected to the decoder input, the output of the first bit of the first setup register is connected to the control input of the first switch, the outputs of the second and third bits of the first setup register are connected respectively to the first and the second control inputs of the first multiplexer, the output of the first discharge of the second setup register is connected to the control input of the second switch, the outputs of the second and five bits of the second setup register are connected respectively to the first and second control inputs of the second multiplexer, the output of the third setup register is connected to the control input of the adder-subtracter, characterized in that, in order to increase performance in the pipelined mode of operation, it contains two delay elements, switches with fourth to sixth, block of OR elements, second and third shift registers, two AND elements, NOT element, third to sixth multiplexers, the third information input of the device connected to the fourth information input of the first multiplexer and to the third information input of the second multiplexer, the fourth information input of which is connected to the output of the multiplier, the second information input of the second switch is connected to the output of the adder-subtractor and the first information input of the third switch, the second information input, control input and output , which are connected respectively with the output of the multiplier, the output of the fourth setup register and the output of the result of the device, the input is accompanying the first sign of which is connected to the first information inputs of the fourth and fifth switches, the outputs of which are connected respectively to the inputs of the first and second delay elements, the outputs of which are connected to the corresponding information inputs of the sixth switch, the control input and output of which are connected respectively to the control input of the third switch and the output of the sign devices, the outputs of the first and second delay elements are connected respectively to the second information inputs of the fifth and fourth com utatorov, control inputs of which are connected respectively to the outputs of the second and fourth bits of the first configuration register, the first configuration of the fifth register is connected to the discharge outlet I 229754 I 2 by the first input of the OR element, the output of which is connected to the control input of the block of prohibition elements, the output of the second multiplexer is connected to the information input of the block of OR elements, the output of which and the output of the second switch are connected respectively to the inputs of the multiplier and the multiplier, the outputs of the bits of the structure register are connected to the corresponding the control inputs of the third multiplexer, the information inputs of which are connected to the outputs of the corresponding bits of the first shift register, the output of the bits of the third mule The multiplexer is connected to the clock inputs of the corresponding setup registers, the outputs of the first and second bits of the register structure are connected to the corresponding control inputs of the fourth and fifth multiplexers, the information inputs of which are connected respectively to the outputs of the bits of the second and third shift registers, the inputs of which are the first and second inputs, respectively modifying the signs of the device, the outputs of the fourth and fifth multiplexers are connected respectively to the second input of the OR element and to by the branching input of the block of OR elements, the input of the end of the device settings is connected to the first input of the first AND element and the counter enable input of the counter, the counter prohibition input 5 of which is connected to the '(t-1) -th decoder output (w is the counting module), the outputs of the first and the second bits of the counter are connected to the corresponding inputs of the element IS10 KEY OR, the output of which and the output of the first category of the counter are connected respectively to the first and second information inputs of the sixth multiplexer, the first and second 15 control inputs of which are connected s, respectively, with the output and the information input of the structure register, the output of the sixth multiplexer is connected to the second input of the first AND element 20, the output of which is connected to the trigger input and the first input of the second AND element, the second input and the inverse output of which are connected respectively to the trigger output and clock input 25 structure register, the input of the first shift register through the element is NOT connected to the inverse output of the second element And, the third input of the first element And is 30 input permission settings of the device. 414039 Fig. 1. ti Tz ij tb sync Ze Ώ. 4 / ^ /////// ^ i V7777772272222 / 27/27. 44— 4J - 31 ~ 48_. 49__ 51_ fifty__ 34 -55 # LJ / M ΕΞ I _ΓΊ _________ — ___ Γ ~ ~ Ί__ ~ Ί__ of FIG. 2