SU1416940A1 - Linear interpolator - Google Patents

Abstract

The invention relates to automation and computing and can be used to graphically construct straight-line segments with positive increments. This increases the speed of the interpolator by decreasing the division factors of the 4, 5 frequency dividers by a number of times equal to the greatest common divisor of the specified increments iX and DU. The interpolator contains a block 2 start-stop, a generator of 3 pulses, counters 6, 7, trigger 8, elements I 9-11, block 1 normalization, 1 mud.

Description

The invention relates to automation and computing and can be used in graphic terminal devices for building straight line segments in increments of x 0 and u y 0.

 The purpose of the invention is to increase the speed of the interpolator.

The drawing shows a functional diagram of a linear interpolator.

The linear interpolator contains a block 1 normalization, a block 2 start-stop, a generator of 3 pulses, dividers 4, 5 frequencies, counters 6, 7, trigger 8, and elements 9 - 11.

Normalization unit 1, which normalizes the binary increment codes DH, iY by simultaneously shifting these codes to the right until at least one low-order bit is single, can be implemented, for example, on the shift registers 12, 13, to the low-end outputs the bits of which are connected to the inputs of the element OR 14, the output of which through the element NOT 15 is connected to the inputs of the element 2 AND-OR 16 and to the output of the readiness sign of the normalization unit 1, the output of the element 2И-OR 16 through the element 17 delay connected to one of the inputs of the element 2I-or 16 and k in moves. controlling the shift of registers 12, 13, the other input of element 2I-OR 16 through delay element 18 is connected to the inputs of the record of registers 12, 13 and to the input of data of the normalization unit 1.

Unit 2 controlling the pulse generator 3 can be implemented, for example, on counters 19, 20 and element 21.

 The frequency divider 4 can be performed, for example, on a multiplexer 22, a comparison circuit 23 and a counter 24 in a similar manner as a divider 5 on a multiplexer 25, a comparison circuit 26 and a counter 27.

The interpolator works as follows.

Before the start of interpolation, counters 24, 27 of the frequency dividers 4, 5, counters 19,20 of block 2 are set to the zero state, and the binary codes X 0, are set at the inputs of the increment setting. The impulse arriving at the input of the Z interpolator trigger sets to zero the counters 6, 7, the trigger 8 and the output 0

five

0

five

0

five

0

five

0

five

leads to the recording of information in shifts1) 1st registers 12, 13 of block 1. If the lower bits iX and uY are zero, then the unit potential from the output of the NOT 15 element allows the passage of an interpolator trigger delayed on delay element 18 through element 2I-Ш1И 16 to the shift control inputs 12, 13. The information is shifted one bit to the right. If the newly lower bits of the registers 12, 13 are zero, then the pulse from the output of element 2I-OR 16, which is delayed by the delay element 17, is again fed to the inputs of the register shift control 12, 13. The information is shifted more by one bit to the right. This continues until at least one of the low-order bits of registers 12, 13 is non-single. In this case, the output potential of the IL 14 element is set to a single potential, and the output of the NOT 15 element is zero, which prohibits the passage of pulses through the 2I-OR 16 element. Thus, the conversion codes for the 6X increments, fiY, to the normalized LH codes, uY dividing the LH, Y codes by the greatest common divisor K (, a multiple of degree 2: K, 2, which leads to an increase in the interpolator's speed at the initial stage, From; the output state of the element OR 14 from O to 1, coming to the information recording inputs counters 19, 20 block 2, zan Osit codes LH, uY in counters 19, 20, which leads to the appearance of a single potential at the output of the NE 21 unit, which triggers the pulse generator 3. The pulses from the generator 3 output go to the clock inputs of the frequency dividers 4, 5, and the potential from the inverse trigger output 8, connected to the control inputs of the multiplexers 22, 25, allows the LH and UY codes to pass to the inputs of the comparison circuits 23, 26 from the outputs of block 1. When the codes yX or uY coincide with the codes at the outputs of the counters 24 or 27 at the output of the comparison circuit 23 or 26, a pulse appears that sets the corresponding counter to the zero state and arrives at the output of the corresponding frequency divider. Thus, at the first stage, pulses with frequencies f / uY and f / fiX arrive at the outputs X, Y of the interpolator;

ten

where f is the pulse frequency from generator 3.

A single potential from the inverse output of the trigger 8 permits the passage of pulses from the outputs of dividers 4, 5 frequencies through elements 9, 10 to the counting inputs of counters 6, 7, which carry out the counting of pulses from frequency dividers 4, 5. If the LH and uY codes have the greatest common divider Kj ,, then the nth pulse from the output of the 5 frequency divider and the mth pulse. From the output of the divider 4 frequencies will coincide in time, where n LH / K ", m". , At the same time, at the output of the element 11, an impulse is formed that sets the trigger 8 into one state. The zero potential from the inverse output of the trigger 8 prohibits further passage of the pulses from the outputs of dividers 4, 5 frequencies through the elements 9, 10 to the counting inputs of counters 6, 7 and allows passage to the inputs of circuits 23, 26 comparing codes from the outputs of counters 6, 7 through multiplexers 22, 25, Thus, now the pulse frequency arriving at the output bus X, Y of the interpolator is equal to f Kj / uX, i.e. The OQ speed of the interpolator at the second stage increases Kj times.

The pulses from the outputs of the interpolator increments arrive at the counting inputs of counters 19, 20 of block 1, working with the start input of the pulse generator, the output of which is connected to the clock inputs of the first and second frequency dividers, the trigger output is connected to the first inputs of the first and second elements And, the second inputs of which connected to the outputs of the first and second frequency dividers, respectively, the output of the first frequency divider is connected to the first input of the third. element And, the output of which is connected to the input of the trigger installation, the reset input of which is connected to the input of & Y / K, j. 5 interpolator starts, incremental outputs

20

25

The scientific research institutes of the first and second coordinates of which are connected to the first and second inputs of the signs of the operation of the start-up block, differing in that, in order to improve speed, two counters and a normalization block are entered into it, the first and second information inputs of which are connected to the first and the second inputs of setting the increments of the first and second coordinates, respectively, the outputs of the first and second normalized normalization block numbers are connected to the first inputs of setting the division factor of the first and second frequency dividers with responsibly, the second inputs of the division ratio connected to the outputs of the first and second counters respectively counting inputs of which are connected to the outputs

subtraction. When resetting the score - - the second and first elements And respectively 10

Oq

five

The scientific research institutes of the first and second coordinates of which are connected to the first and second inputs of the signs of the operation of the start-up block, differing in that, in order to improve speed, two counters and a normalization block are entered into it, the first and second information inputs of which are connected to the first and the second inputs of setting the increments of the first and second coordinates, respectively, the outputs of the first and second normalized normalization block numbers are connected to the first inputs of setting the division factor of the first and second frequency dividers with responsibly, the second inputs of the division ratio connected to the outputs of the first and second counters respectively counting inputs of which are connected to the outputs

the second and first elements AND

Chips 19, 20 at the output of the NAND 21 element, a zero potential is formed, which stops the operation of the generator of 3 pulses. This interpol completes.

Claims (1)

Claims of the invention. Linear interpolator containing 45 pulse generator, two frequency dividers, a start-stop unit, a trigger and three AND elements, the inputs for setting the increments of the first and second coordinates of the interpolator are connected to the first and, in turn, input, the start of the interpolator is connected to the inputs of resetting the first and second counters and with the input of the data entry of the normalization block, the output of the sign of which is connected with the input of the entry of the sign of the mode of the start-up block, the outputs of the first and second frequency dividers are connected to the outputs of the increments of the first and second coordinates of the interpolation Pa, the output of the second frequency divider is connected to the second input of the third element, And the output of the trigger is connected to the control input of the multiproximity input of the unit mode setting by launching the division coefficients of the first ka-stop, the output of which is connected to the second frequency divider. correspondingly, the input, the start of the interpolator is connected to the reset input of the first and second counters and to the data entry input of the normalization block, the output of which is connected to the input of the input of the mode of the start-stop unit, the outputs of the first and second frequency dividers are connected to the outputs of the increments of the first and second coordinates of the interpolator, the output of the second frequency divider is connected to the second input of the third element I, the output of the trigger is connected to the input of the control of the multi 1 division of the coefficients of the first and torogo frequency dividers.