SU1283753A1 - Device for dividing binary numbers - Google Patents

Abstract

The invention relates to the field of computing, in particular to electronic digital computers. The device contains the registers of the dividend, the divider and the quotient, the adder, the control unit, the trigger. In order to improve speed, the device includes a switch and a shift signal generator. The device performs a dividing operation without restoring the remainder with skipping the add cycles by the shift signal generated in the shift signal generator. The method of forming the shift signal used in the device provides the maximum possible acceleration of speed with logical methods: the mathematical expectation of the number of shifts by. one addition is equal to 3, the maximum possible number of additions does not constitute half of the total number of particular bits. 3 yl, .1 tab. i (L

Description

The invention relates to computing, in particular to electronic digital computers.

The purpose of the invention is to increase the speed of the device.

Let D be the value of the divisor, and B the value of the dividend (or the next remainder), then the quotient (or the younger part of the quotient) B

In x d

D (1)

expression (1) is 5

6

have boundary

five

depending on the value of B; and D (on the left - the composition of actions performed with a positive balance; on the right - with a negative balance). Using the data in the table, it is possible to create a logical formula that covers all cases in which a loop containing only

shift, denoting bj and dj j-e bits, respectively, of the current balance B; and divider D, after minimizing, formulas for performing a shift cycle for a positive FX residue, (bjVb ,, vb, d) Vb,

.4b ,,)

residual value:

X d

II

X d

If the current balance is smaller,

/ V; / I D, G2)

THEN in the next cycle, you only need to perform a shift.

If the current balance is in absolute value greater than in, t, e.

/ B; / I D,

(3)

then you need to perform a cycle containing addition and shift.

If the inequality holds

I D / B; I d

(four)

in the process of dividing those values of B and B and out, it is possible to produce both addition with a shift, and only a shift. Comparing to the balance of the selector type of the next cycle in accordance with conditions (2), (3) and (4) it is possible to provide the minimum possible number of summations dn of any values of the quotient.

The whole range of variation of the divider

ji: D 1 can be divided into several sub-bands, for each of which you can specify the value of the low order residue, starting with which cycles of a different type are performed,

All data are summarized in a table reflecting the composition of the performed tsiki dp of negative balance 20 F bo b, (b, Nb, vd ,, vd, vb4

. v (b ,,).

The resulting formulas can be combined into one, if you make a replacement

25

but;

 bj DK v bj.OK

0

five

0

five

0

five

Then the shift function, (a, jV a, vdjVd va4 (a, va4d,) (5)

Ha FIG. 1 shows the block diagram of the proposed device; Fig. 2 is a functional block diagram of the control unit; FIG. 3 is a functional diagram of a shift signal generator.

The device contains a divider register 1, a dividend register 2, a private register 3, an adder 4, a control unit 5, a trigger 6, a switch 7, a shift signal generator 8, an input 9 and an output 10 of the device.

The control unit 5 consists of a generator of pulses P, distributors 12-14 pulses, elements OR 15 and 16, elements AND 17 and 18, counter 19, switch 20, Decoder 21 zero, first 22–5 fifth outputs and first 27, second 28 and the third is 29 entrances.

The shift signal generator contains the elements AND 30 - 34 and the elements OR 35-37.

The device performs the division of n-bit normalized binary numbers represented in direct codes, the quotient is also formed in the direct code. Registers 1 and 3 have one additional bit, register 2 has two additional bits.

bit At the same time, registers 2 and 3 contain shift chains to the left, 1, can be not shift. The adder 4 is a (n + 2) -dot combiner type adder. Three-giger 6 is a normal D-trigger with an additional initial setup input and direct and inverse outputs. If trigger 6 is in the single state, then switch 7 passes to its output the inverse code of the five most significant bits of register 2 of the dividend, otherwise, their direct code.

The operation of the control unit coincides with the operation of the control unit of the prototype device.

If Fj.l, then the division cycle contains only a joint shift of registers 2 and 3 to the left by the control signal from output 22 of block 5, the common F 0, then in the loop, the codes of registers 1 and 2 are preliminarily performed, and then the combined shift the contents of registers 2 and 3 to the left. Since register 2 contains two additional bits, the code of the dividend in it is shifted to the right by one bit relative to the divider code in register 1, This is due to the fact that for some values of the B-remainder and divider D, the addition must be done for residual codes containing zeros in the two most significant bits. If trigger 6 is in the single state (as, for example, in the 1st division cycle) and F 0, the pulse passes through the output 23 of block 5 to the control input of the issuance of the additional register 1 code of the divider — the additional register code 1 is represented as inverse code and single signal supplied to the low-order transfer input of the adder 4) If trigger 6 is in the zero state, adder 4 adds the forward code received from register 1 with the code from register 2, After a specified time interval is a signal on in Hur outlet distributor 13, which is supplied to the reception control information input register 2 and a control input of the flip-flop 6, At receipt of this signal is performed in the recording code register 2 sum obtained in the adder 4, and

 5 Yu

2837534

Also, the installation of a trigger 6 senior bits of this amount .. In this case, the trigger 6 is set to one

five

five

the state, if the foremen of the sum of the sum is equal to one, otherwise the trigger 6 is set to the zero state. In each cycle in the high order of register de reg, one digit of the quotient is formed, which is transmitted to the low order of register 3 as a result of a joint shift of these registers.

The number of determined bits of the quotient for one addition is equal to three. The number of summations does not exceed + 2.

Claims (1)

Invention Formula 20 A device for dividing binary numbers, containing registers of the dividend, divisor and quotient, adder and control unit, the output of the register private is the output of the device, the input of the device is connected to the information input of the register divider, the output of which is connected to the first information input of the adder, the second information input of which is connected to the output of the register of the dividend, the information input of which is connected to the output of the result of the adder, the output of the high register of the dividend is connected with the input of the lower bit of the register of the private, the first output of the control unit is connected to the inputs of the shift control of the dividend and private registers, the second and the third the outputs of the control unit are connected to the control inputs of the issuance, respectively, of the additional and direct divider register codes; the fourth output of the control unit is connected with the control input of receiving information of the register of the dividend, the fifth output of the control unit is connected to the input of the sign bit setting. The divider register, which is different in that, in order to increase speed, a switch, a trigger and a shift signal generator are inserted into it, containing five AND elements and three OR elements, the first input of the trigger setup to 1 is connected to the fifth output of the control unit, the fourth output of which is connected to the second input of the trigger setup to 1, the informational trigger input is connected to the high end output of the adder, the first and second information inputs of the switch are connected to direct and inverse the outputs of the five most significant bits of the register of the dividend, the first and the second bits of the switch output are connected respectively to the first inputs of the first and second elements AND the shifter of the shift signal, the third and fourth bits the switch output is connected to the first and second inputs of the first OR element, the third input of which is connected to the output of the third element AND, the first input of which is connected to the fifth discharge of the switch output and the first input of the fourth element And the second register output of the divider is connected to the fourth input of the first the OR element and the first input of the fifth element AND, the second input of which is connected to the first input of the first OR element, the fifth input of which is connected to the second input The composition of the actions performed in the cycle depending on the values of B; and D 837536 the fourth element And with the release of the third bit register divider, the output of the fourth bit of which is connected to the second input of the third 5 of the AND element, the output of the first OR element is connected to the second input of the second AND element, the output of which is connected to the first input of the second OR element, the second input of which is connected 10 with the output of the fifth element AND, the third input of which is connected to the output of the third element IL, the first input of which is connected to the second input of the first OR element, the output of the fourth AND element is connected to the second input of the third OR element, the output of the second OR element is connected to the second input the first element And, the output of which is connected to the first A control input 20, the second and third inputs of which are connected to the first and second control inputs of the switch, and the forward and inverse outputs of the trigger, respectively, 25, but. Note, DK is a cycle containing addition with an additional divider code and PC shift — a cycle containing a stack with Lr m, 1m divider code and shift; C is a cycle containing only a shift; ZK is a forbidden combination, while if ZK is located on the left side, then it cannot occur with a positive balance, and if on the right side, then with a negative balance, the sign indicates the bits whose envs do not show the effect on cycle. 1283753 8 Continuation of the table fpuz.l (od FC 2nd entrance (Reg. 5 Compiled by N. Markelova Editor L. Pchelinska Tehred L. Serdyukova Proofreader L. Patay Order 7А42 / 47 Circulation 670 Subscription VNII1Sh State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 ipuz.2 uf uff 1st approach