SU1539774A1 - Pseudorandom series generator - Google Patents

Abstract

The invention relates to computing, for example, pseudo-random sequence generators, and can be used to solve problems of statistical modeling and simulate random processes. The aim of the invention is to enhance the functionality of the generator by increasing the length of the pseudo-random sequence being generated. The pseudo-random sequence generator contains a clock pulse generator, a reversing shift register, two modulators for the first and second modulators, the first and second AND elements, a switch, a frequency divider and a T-flip-flop. The generator generates pseudo-random sequences using an N-bit register with a modulo two in feedback. The purpose of the invention is achieved by the fact that after 2 ^N -1 clock cycles of the generator, the direction of information shift in the register automatically changes and the feedback circuit is switched, which is achieved by using a frequency divider and a T-trigger entered into the generator. 1 il.

Description

The invention relates to computing and can be used to solve static modeling problems and simulate random processes.

The purpose of the invention is to expand the functionality of the generator by increasing the length of the generated pseudo-random sequence.

The drawing shows a functional diagram of the generator.

The pseudo-random sequence generator contains a generator of 1 clock pulses, a reversing shift register 2, the first 3 and the second 4

two modulators, the first 5 and the second 6 And elements, the switch 7, the frequency divider 8 and the T-flip-flop 9.

A pseudorandom sequence generator implements a method of forming pseudorandom sequences using an n-bit p shift register with a modulo-two adder in feedback.

The generator works as follows.

With the help of the control input of the switch, a specific type of feedback used in the formation of pseudorandom sequences with

sd

with so

Јъ

offset information in register 2 shift in forward and reverse directions. In other words, the switch 7 connects to the inputs of the adders 3 and 4 modulo two specific bit outputs of register 2, selected from the condition of ensuring the formation of a pseudo-random binary sequence of maximum length.

At the time of the initial | the keys in register 2 write the initial value (write chains are not shown), T-flip-flop 9 is set to some arbitrary state. Suppose that it is in a single state. Then the unit 2 input signal is fed to the shift control right register, which ensures that it is transferred to the right content shift mode (toward the higher bits). When each next clock pulse arrives at the clock input of register 2 from clock generator 1 pulses, 25 in this case, the information contained in the register is shifted by one bit to the right while the new value is written to the low-order bit of the register. The specified new value comes from the output of the second adder 4 modulo two through the second element 6, opened by the signal from the direct output of the T-flip-flop 9. This closes the feedback circuit necessary to form a pseudo-random 5 sequence of maximum length - us 2i-1. After 2p-1 cycles of work on the Wits signal at the output of the frequency divider 8, which will transfer the T-flip-flop 9 to the opposite (zero) state. As a result, register 2 is shifted to the information shift mode to the left (in the direction of the lower bits),

40

and the feedback is closed through the first element And 5, and the signal from the output of the first adder 3 modulo two is recorded at each clock cycle in the high register bit 2. The presence of a divider 8 frequency and T

trigger 9 ensures a double period of the generated pseudo-random sequence of 2 (2 -1), while retaining such properties of the M-sequence as the equal probability of occurrence on the period

/" five

0

five

Ode all binary numbers from 1 to 2i-1, exceeding by one the number of unit symbols over the number of zero.

Claims (1)

Invention Formula A pseudo-random sequence generator containing a clock pulse generator, a reversing register, a shift, two first and second modulo adders, a first and a second And elements, and a switch, the first output of which is connected to the first input of the first modulo-two adder; the outputs of the reversible shift register, the control input of the switch is the input of the assignment of the form of the generated generator sequence, the first and last bit outputs of the reversing register shift hectares are connected to the second inputs of the first and second modulo two adders, respectively, the output of the first modulo two adder is connected to the first input of the first element I, the output of which is connected to the input of the last digit of the reverse shift register, the output of the second modulator adder two is connected to the first the input of the second element And, the output of which is connected to the input of the record of the first discharge of the reverse shift register, the output of the clock pulse generator is connected to the clock input of the reverse shift register, which distinguishes In order to extend the functionality by increasing the length of the pseudo-random sequence being generated, a frequency divider and a T-trigger are introduced into the generator, the direct output of which is connected to the second input of the second And element and the shift control input to the right of the reverse shift register, the inverse output The T-flip-flop is connected to the second input of the first element I and the input of the left-shift shift control of the reverse shift register, the output of the clock generator is connected to the input of the frequency target, the output of which It is connected to the counting input of the T flip-flop, the second output switch connected to the first input of the second adder of modulo two.