SU1746373A1 - Function system generator - Google Patents

Abstract

The invention relates to automation and computing and can be used for spectral analysis of signals when they are decomposed into systems of functions. The purpose of the invention is to expand the functionality of the generator due to the formation of 2MN systems of discrete basis functions M (the number of values accepted by the functions, 2nN the dimension of the system of functions). The generator contains counters 1 and 2, a selector of 3 clock pulses, a shift register 4, a driver of 5 time intervals, switches 6 and 7. The adder 8 is modulo M / 2. sign definition node 9, shift register 10, block

Description

2

About GJ XJ

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ki 11 and 12 elements AND, groups 13 and 14 of the inputs of the system setting functions, input 15 clock pulses, output 16 functions, output 17 function numbers in the system, output 18 end of the function period, block 25 elements OR Expanded functionality is achieved by introducing additional units: switches, clock selector, time interval generator, sign definition node, block of elements OR 1 or

The invention relates to automation and computing and can be used for spectral analysis of signals when they are decomposed into systems of functions.

The prototype contains two n-bit estimators (M-2n-dimension of the system of functions), n shift registers, n elements NOT, n blocks of elements I, modulator mod N / 2, clock input, function set task input, function output, the output of the end of the period of the generated functions, the output of the number of the generated function, in which the input of the first counter is connected to the generator input jack and the synchronization input and shift registers, the output of the first counter overflow is connected to the counting input of the second counter, to the write control inputs and register the shift offset and the output of the end of the period of the generated generator functions, the bit outputs of the second counter are connected to the output of the number of the generated generator function and to the control inputs n of the blocks of elements And, od One of the i-ro group of the shift register (I - 1 Nl / 2, i 1, n, m is the size of the group defined by the number of bits in the binary representation of the number M / 2, M is the even integer) is connected to the I x 2 and the bit group of the input of the set of functions of the generator function, the first output N / 2 and the bit group of the 1st shift register through the i-th element is NOT connected to the first input of the group The serial input of the i-ro shift register, its outputs are at m - 1 st M / 2 th digit group of the th shift register, respectively, connected to inputs 2, m + 1 of the sequential input group of the i-ro shift register, outputs 1 , m + 1 M / 2 th digit group of i-ro shift register are connected to the group of information inputs of the t-ro block of elements And, the outputs of blocks of elements And connected to the inputs of the adder modulo M / 2

The disadvantage of this generator is a limited class of basic functions systems formed by it (a class of 2MNr / 2 systems of basic functions is formed)

The purpose of the invention is to expand the functionality of the generator for

counting the formation of 2M systems of discrete basis functions (M is the number of values used by the functions N 2P -size of the system of functions)

The goal is achieved by the fact that

into the generator of systems of functions containing two counters, two shift registers n - 1 blocks of elements I (2n-N is the dimension of the system of functions), the modulo M / 2 adder (M is the number of values accepted by the functions), and the counting input of the first counter is The clock input of the generator, the overflow output of the first counter is the output of the end of the period of the function of the generator and connected to the counting input of the first counter, the output of which is the output of the number of the generator function, two switches are introduced, a clock selector intervals, a logical computing node, a block of OR elements, with N / 2 information inputs of the first switch and N / 2 information inputs of the second switch being the first and second

groups of inputs for setting the functions of the generator, the information output of the first counter is connected to the inputs of the clock selector and time generator, the output of the second counter

connected to the parallel input of the first shift register, whose serial input is connected to the generator zero level source, the first bit output of the first shift register is connected to the corresponding information input of the sign computation logic, k + 1 k - 1, n - 1) bit the output of the first shift register is connected to the k-th address input of the first and second switches, the output

the first switch is connected to the first input of the block of elements OR. information output of the second switch is connected to the input of the first operand of the adder modulo M / 2, the sign output of the second

the switch is connected to the corresponding information input of the logical node calculating node, the output of which is single with the sign input of the first operand of the modulo M / 2 adder; the output of the modulo M / 2 adder is connected to the secondary input of the second shift register; the first bit output of the second shift register is output generator functions, k + 1 - and the bit output of the second shift register is connected to the information input of the k-ro block of elements I, the control input and output of the k-ro block of elements And connected to the k-th output of f the time slot adjuster and k + 1 input of the block of elements OR, the output of block of elements OR is connected to the input of the second operand of the modulo M / 2 adder, the overflow output of the first counter is connected to the read control input of the first switch , the control input of the first shift register and the input of the prohibition of the sign computing logic node, the shift inputs of the first and second shift registers are connected respectively to the output of the clock selector and the clock input m generator.

The drawing shows the functional diagram of the generator ().

The generator contains counters 1 and 2, a clock selector 3, a shift register 4, a shaper 5 time slots, switches 6 and 7, an adder 8 modulo M / 2, a logic calculation node 9, a shift register 10, blocks 11 and 12 of the AND elements , groups of 13 and 14 inputs of the function setting system, input 15 clock pulses, output 16 functions output 17 function numbers in the system, output 18 end of function period, block 25 elements OR

The generator forms the class MN of complex systems of discrete basis functions (or the class 2MN of systems of real basis functions) that take M values

SRI.

The generator implements a method of forming systems of discrete basis functions through given discrete transformation matrix G (2n) in the form of Kronecker products of factors. In accordance with this method, matrix G (a) is defined as follows

and (in,

, 2n

 ik

where W e -rr-, M 2 - the number of values

M

, 2n

received functions e-c-A on the interval (0.2 tg, D (rO, M / 2-1, K - an arbitrary integer.

The multiplication operation of the matrix factors 8 (1) follows the Crockecker product rule. The product of the degrees W and the formation of the values of the basis functions in the generator is performed according to the rule:

(UjtmodM / Z,

W W (si®S2)

D, A2 where si and S2 - signs of degrees W, W:

(2)

S0, if the sign of the degree W is positive,

1 if the sign of the degree W is negative.

p is the transfer formed when performing the operation of adding the exponents in (2):

0, if the selection of the integer M / 2 occurred an even number of times,

1, if the selection of the integer M / 2 occurred an odd number of times.

Thus, in accordance with (1) for selected M, K, N, during n iterations, M systems of complex basis functions can be formed by specifying N / 2-x generators G (2) as multipliers of the first iteration.

The generator works as follows

The elements of the generator matrices Gp) feed the first elements of each first row, respectively, to a group of 13 inputs of the task of the function system, and the second elements of each first row, respectively, to a group of 14 inputs of the task of the system of functions. The elements of the second rows of the generating matrices and the elements of the matrix factors of the subsequent iterations are generated automatically by the generator in accordance with (1). Counter 1 counts the clock pulses arriving at its input and forms the period of the function T N x t, where t is the period of the clock pulse. The overflow pulses of the counter 1 synchronize the operation of the generator according to the following algorithm. The front of the overflow pulse adds +1 to counter 2, writes to shift register 4; overflow time is resolved

reading of switch 6, the reading of switch 7 and the sign computing logic 9 is prohibited.

The values of the basis functions in accordance with (2) form the adder 8 modulo M / 2, the first input of which can receive the values of the first elements of the generator matrices from the output of the switch 6 or the values of the functions formed in previous iterations from the outputs of blocks 11 and 12. The second input of the adder 8 modulo M / 2 receives the values of the generated iteration factors from the output of the switch 7. managed by the shift register 4. The incoming clock edge generated values of the basis functions are written to the shift register 10 and output 16 functions of the generator.

Unlike the prototype, the proposed generator forms 2MN systems of discrete basis functions, which is its advantage.

Claims (1)

Invention Formula A generator of function systems containing two counters, two shift registers, n-1 blocks of elements I (2n-N is the dimension of the system of functions), a modulo M / 2 adder (M is the number of values accepted by the functions), with the counting input of the first counter is the clock input of the generator, the overflow output of the first counter is the output of the end of the period of the generator function and is connected to the counting input of the second counter, the output of which is the output of the generator function number, characterized in that, in order to extend the functionality of the generator and by forming 2MN discrete systems of basis functions, it comprises two switches, clock selector generator slots, the sign computation logic unit or block elements. moreover, the N / 2 information inputs of the first switch and the N / 2 information inputs of the second switch are respectively the first and second groups of system function inputs generator, the information output of the first counter is connected to the inputs of the selector clock pulses and shaper time intervals, the output of the second counter connected to the parallel input of the first shift register, the serial input of which is connected to the generator zero level source, the first bit output of the first shift register is connected to the corresponding information input of the sign calculating logic node, (k + 1) -th (k 1; n - 1) bit The first output of the first shift register is connected to the -m address input of the first and second switches, the output the first switch is connected to the first input of the OR block; the information output of the second switch is connected to the input of the first operand of the modulo M / 2 adder; the sign output of the second the switch is connected to the corresponding information input of the logical node calculating the sign, the output of which is connected to the sign input of the first operand of the modulo M / 2 adder, the output of the modulo M / 2 adder is connected to the serial input of the second shift register; the first bit output of the second shift register is by the output of the generator function, the (k + 1) -th bit output of the second shift register is connected to the information input of the k-ro block of the And elements, the control input and output of the k-ro block of the And elements are connected respectively to the kM output ohm shaper time intervals and (k + 1) th input of the block of elements OR, the output of the block of elements OR is connected to the input of the second operand of the modulo M / 2 adder, the output of the overflow of the first counter is connected to the control input of reading the first switch, the read inhibit input of the second switch, the control input for writing the first shift register and the input ban for the sign computing logical node, the shift synchronization inputs the first and second shift registers are connected respectively to the output of the clock pulse selector and the clock input of the generator.