SU1142845A1 - Device for implementing two-dimensional fast fourier transform - Google Patents

Abstract

A DEVICE FOR IMPLEMENTING TWO-DIMENSIONAL FAST FOURIER TRANSFORM, containing a fixed memory block, an arithmetic block, a memory block whose address input is connected to the information outputs of the first and second switches, the control inputs of which are connected to the first input of the adder and connected to the first output of the first switch the shift, the register, the information output of which is connected to the second input of the adder, the output of which is connected to the {| formation input of the register, characterized in that, in order to increase str. device actions, the address counter, the I element, the second shift register and the synchronizer are entered in it, the first output of which is connected to the counting input of the address counter, the output of the first discharge of which is connected to the first information input of the second switch and the first input of the I element whose output is connected to control input of the second register shift; the information output of which is connected to the address input of the constant memory unit, the control input of the first shift register is connected, to the output of the higher bit of the address counter, the output of the third bit of which is connected to the synchronization input of the register, the information output. the stroke of which is connected to the information input of the second shift register, the output of the second discharge of the address counter is connected to the second input of the element (O and I and the first information input of the first switch, the second information input of which is connected bitwise to the outputs of bits c (n + 3) - Go to I

Description

the output of the decoder, the output of the multiplier of complex numbers is connected to the information input of the buffer memory node, and the synchronization input of the accumulating adder is connected to the output of the element AND of the arithmetic unit, the first and second inputs of the multiplier of the complex numbers of the arithmetic block are connected to information outputs of the memory block and constant block respectively memory, the second output of the synchronizer is connected to

the counter input of the counter and the first input of the element AND of the arithmetic unit, the outputs of the first, second and third bits of the address counter are connected to the installation input of the counter, the control and second information inputs of the switch, the decoder input and the second input of the element And the arithmetic unit whose output accumulator adder is connected to the information input of the memory block.

The invention relates to computing and can be used for processing two-dimensional signals, in particular for digital image processing and space-time processing.

A device is known that contains an arithmetic unit, a complex trigonometric constant block, an ultra-fast memory block, a direct access block Cl.

A disadvantage of the known device is low speed and high hardware costs.

The closest in technical essence to the present invention is a device for realizing a fast Fourier transform (FFT) comprising a RAM, a persistent memory, an arithmetic unit and a control unit, the first, second and third outputs of the control unit being connected, respectively, to the inputs a fixed memory, an arithmetic unit and a random access memory, the first and second groups of inputs of the arithmetic unit are connected, respectively, to the output groups of the permanent and main memory, the control unit contains a register p, the first and second corpses of the And elements, the first and second counters, the adder, the address storage register and the address node of the address code, the first and second outputs of the mode setting node being connected to the first inputs of the AND elements, respectively, of the first and second groups, second the inputs of which are connected to the first output of the register, the second and third outputs of which are connected, respectively, to the first inputs of the adder and the mode setting node, the third and fourth outputs of which are connected, respectively, to the inputs of the first and second counters, first output The ports of which are connected, respectively, to the second and third inputs of the mode setting node, the fifth. The output is connected to the register input, the second outputs of the first and second meters are connected to the first inputs of the first and second switches, respectively, the second inputs of which are connected to the outputs of the AND elements. respectively, the first and second groups, the switch outputs are the device outputs, the adder output is connected through the address code access node to the device output and through the address storage register to its second input L2J.

However, the known device is characterized by low speed when calculating a two-dimensional FFT due to the necessity of sequential calculation of the FFT in rows and columns.

The purpose of the invention is to increase the speed (when calculating a domer FFT due to simultaneous calculation of the FFT in rows and columns).

The goal is achieved by the fact that the device containing a block of permanent memory, an arithmetic unit, a memory unit whose address input is connected to the information outputs of the first and second switches, the control inputs of which are connected to the first input of the adder and connected to the information output of the first register shift, the register, the information output of which is connected to the second input of the adder, the output of which is connected. To the information input of the register, the address counter, the AND element, the second shift register and sync are entered nizator, the first output of which is connected to the counting input of the address counter, the output of the first bit of which is connected to the first information input of the second switch and the first input of the And element whose output is connected to the control input of the second shift register, the information output of which is connected to the address input of the block memory, the control input of the first shift register is connected to the output of the higher bit of the address counter, the output of the third bit of which is connected to the register synchronization input, information The output of which is connected to the information input of the second shift register, the output of the second discharge of the address counter is connected to the second input of the element I and the first information input of the first switch, the second information input of which is connected bitwise to the outputs of bits c (n + 3) -th by (2p + 1) -th (n is the number of iterations) of the counting address, the outputs of bits 4 to (n + 2) of which are bit-wise connected to the second information input of the second switch, and the arithmetic unit contains the multiplier complex numbers, buffer memory node t, accumulating adder, switch, deprafter, And element and counter, information output of which is connected to the input of the decoder, installation input of accumulating adder and first information input of the switch, information output of which is connected to the address input of the buffer memory node, information output of which is connected to the information output the input of the accumulating adder, the control input of which is connected to the output of the decoder, the output of the multiplier of complex numbers is connected to the information input of nodes the buffer memory, and the synchronization input of the accumulating adder is connected to the output of 1 54 elements of the arithmetic unit, the first and second inputs of the multiplier of the complex numbers of the arithmetic block are connected to the information outputs of the memory block and the permanent memory unit, the second output of the synchronizer is connected to the counter the input of the counter and the first input of the element AND of the arithmetic unit, the outputs of the first, second and third bits of the address counter are connected to the installation input of the counter, the control and the second information the ionic inputs of the switch, the input of the decoder, and the second input of the element AND of the arithmetic unit, the output of the accumulating adder of which is connected to the Information input of the memory block. The proposed device allows us to perform the calculation of the FFT of a two-dimensional array of dimension N «N in n iterations (where), which is half as much as in the prototype. FIG. 1 shows the structural scheme of the device; in fig. 2 shows a functional diagram of an arithmetic unit; in fig. 3 - timing diagrams synchronizer. The device for the implementation of two-. The first fast Fourier transform (Fig. 1) contains a block of 1 RAM, an arithmetic unit 2, a block 3 of constant coefficients of coefficients, direct switches 4 and 5, an n-bit shift register 6, a (n-1) -digit iteration shift register 7, (2p + 1) bit counter of the address 8, element 9, (n-1) -discharge storage register 10, (n-1) -discharge adder 11, synchronizer 12. Arithmetic unit 2 ( Fig. 2) contains a multiplier 13 of complex numbers, a buffer memory node 14, accumulating adder 15, a switch (for two channels) 16, a decoder 17 characters, a counter 18, ale t And 19. The frequency of the pulses arriving at the X3 input of the arithmetic unit from the output of synchronizer 12 is four times higher than the frequency of the pulses arriving at the counting input of counter 8 from the other output of synchronizer 12. The information inputs of the switch provide the potentials logical O and 1, thus to get a series of pulses 0000001101010110 at the output with a frequency equal to the frequency of the pulses at the output of the first digit of the counter 18. In the proposed device, there is a non-redundant algorithm for simultaneous FFT counting in rows and columns pny array with replacement and thinning on time. The device works as follows. The initial array of N-N dimension is included in memory block 1 in binary-inverse order both in rows and in columns. In the initial state, the shift register 6, the storage register 10, the counter 8, the counter 18 and the accumulating adder 15 are cleared; logical bits 1 are entered in all bits of the iterative shift register 7, to the counting input of the address counter 8, the first output of the synchronizer 12 receives clock pulses by which (2n + 1) -disable counter 8 at the outputs generates successive codes that arrive at the information inputs of the first and second switches 4 and 5. At the output of the first switch 4, the write-read addresses of the operands from the operative block are formed memory in rows, at the output of the second switch 5 — by columns. The addresses of the exponential multipliers at the output of the storage register 10 are made by impulses from the output of the third bit of the counter 8 using the storage register 10 similarly to the prototype. Execution of FFT iterations in the proposed device consists in the sequential repetition of an elementary loop of the form. x + X2W + x x j + XjW-XjW-x W; X;, - XjW + XjW-x W x -XjW-XjW + x W, Where X ,,, Xji, Xj, x - respectively, the first, second, third, fourth operands extracted from 1 block of RAM ; W is an exponential factor retrieved from the block 3 of the constant coefficient memory. When performing a single elementary cycle in accumulator adder 15, it is necessary to perform the operation of summation with the following 11 characters: + + + + + + - + - +. therefore, at the output of the character decoder 17 a sequence of control pulses is formed: 0000001 1010101 10. Each elementary cycle in the arithmetic unit 2 is performed as follows. The low level of the impulse records the output of the third discharge of counter 8 from the RAM block 1 by sequentially reading four operands, multiplying them with the corresponding exponential factors (the first-operand is multiplied by one) and storing the received works into the node 14 of the buffer memory by addresses formed at the output of the switch 16 into two channels. By the high level of write-counting pulse from the output of the third bit of counter 8, in accordance with the control pulses of the summation sign from the output of the decoder 17 characters, the accumulating sum is first accumulated in accumulator 15 produced by node 14 of the buffer memory to the place of the first operand extracted from block 1 of the RAM; then a second summation and insertion into memory 1 is performed, and then the third and fourth. The squaring of the exponential multiplexes in the proposed device is carried out using the shift register 6 as follows. The exponential factor is generally written as “. .F (where k is the number of the multiplier, squaring the exponential multiplier is equivalent to doubling its number, and therefore doubling its address. The address of the exponential multiplier generated at the storage register 10 is entered into the bit shift register 6 so that the nth bit remains free, and if the doubling pulse is not input to the shift register 6 from the output of the AND 9 element, the address is not doubled and fed unchanged to the address input of the fixed memory block 3 When arriving at the input of the register of 6 shift of the doubling pulse from the output of the element And 9, the address entered in the register 6 of the shift by one bit towards the higher bits shifts. A doubling pulse is formed at the output of the element And 9 when the levels at the outputs of the first and the second bits of counter 8, i.e., for every fourth operand retrieved from the operational memory block 1. After each elementary cycle of the iteration of the dimensional FFT is completed, the transition signal from the logical 1 state to the upper counter 11

Pu, / 58 18 accumulative adder 15 is zeroed. After the first iteration is completed, the transition signal from the state of logical 1 to O of the most significant bit of counter 8 in the iteration register 7 of the shift shifts the information towards the lower bits, putting the logical O into the most significant bit and the device starts calculating the new iteration. Thus, the proposed device allows to increase the speed of calculating a two-dimensional FFT by simultaneously calculating the FFT in rows and columns. SHShLnnnn nnnn rninn nnnn nniin

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Claims (1)

DEVICE FOR IMPLEMENTING TWO-DIMENSIONAL FAST FOURIER TRANSFORM, containing a constant memory unit, an arithmetic unit, a memory unit, the address input of which is connected to the information outputs of the first and second switches, the control inputs of which are connected to the first input of the adder and connected to the information output of the first shift register, register the information output of which is connected to the second input of the adder, the output of which is connected to the information input of the register, characterized in that, in order to increase quickly. actions of the device, an address counter, an AND element, a second shift register and a synchronizer are introduced into it, the first output of which is connected to the counting input of the address counter, the first discharge of which is connected to the first information input of the second switch and the first input of the And element, the output of which is connected to the control the input of the second shift register, the information output of which is connected to the address input of the read-only memory block, the control input of the first shift register is connected. To the output of the high-order bit of the address counter, you the course of the third bit of which is connected to the register synchronization input, the information output of which is connected to the information input of the second shift register, ~ the output of the second bit of the address counter is connected to the second input of the And element and the first information input of the first switch, the second information input of which is connected bitwise to the outputs of the bits with (n + 3) -th to ⁵ (2n + 1) -th (n is the number of iterations) counter 'addresses, bits 4 and outputs the (n + 2) th digit by digit which is connected to the second data input of the second switch, when The arithmetic unit contains a complex number multiplier, a buffer memory node, an accumulating adder, a switch, a decoder, an I element, and a counter whose information output is connected to the decoder’s input, the accumulating adder’s installation input and the first information input of the switch, whose information output is connected to the address the input of the buffer memory node, the information output of which is connected to the information input of the accumulating adder, the control sign of which is connected to the decoder output RA, the output of the complex number multiplier is connected to the information input of the buffer memory node, and the synchronization input of the accumulating adder is connected to the output of the AND element of the arithmetic block, the first and second inputs of the complex number multiplier of the arithmetic block are connected to the information outputs of the memory block and the constant memory block, second output the synchronizer is connected to the counting input of the counter and the first input of the AND element of the arithmetic unit, the outputs of the first, second and third bits of the counter address They are connected to the installation input of the counter, the control and the second information inputs of the switch, the input of the decoder and the second input of the AND element of the arithmetic block, the output of the accumulating adder of which is connected to the information input of the memory block.