SU1073776A1 - Digital correlator - Google Patents

Abstract

A DIGITAL CORRELATOR containing a memory block whose output is connected to the input of the first accumulating adder, and the address input is connected to the multiplexer output, the memory block record input is combined with the input of the address counter of the recording and connected to the first output of the synchronization unit, the second output of which is unique. with the control input of the multiplexer, the read input of the memory block and the control input of the constant memory block, the output of which is connected to the first input of the read address generator, the second input of which is connected To the third output of the synchronization unit, the output of the read address generator is connected to the first information input of the multiplexer, the second information input of which is connected to the output of the write address counter, characterized in that, in order to increase the speed of the correlator, the input sample register is entered, the second accumulating adder and shift register, the control input of which is connected to the first output of the synchronization unit, and the output is connected to the information g HbiM input of the storage unit, information (L o A shift register is connected to the output of the second accumulating adder, the first input of which is connected to the output register of the input sample, the input of which is combined with the second input of the accumulating adder and is the information input of the correlator. 00 m | 05

Description

The invention relates to specialized computer hardware and is intended for cross-correlation processing of signals. Measuring the mutual correlation function (ICF) between the input and reference (deterministic) signals in real time requires processing the entire array of samples {determined by the complexity of the signal and the accuracy of the measurement parameters over time by two adjacent samples received at the input of the correlator. A digital correlator is known in which, in order to reduce the number of multiplication operations performed, the input information is pre-processed in the additional accumulative adder, in particular, the operands are combined into blocks with subsequent summation of the operands within. Thereby, replacement of a part of multiplication operations with a less laborious addition operation is achieved. The correlator contains memory blocks with random access to information, a multiplication unit, a series of accumulating adders, address counters, a synchronizer, and communication sort l. The disadvantage of this device is that although the number of multiplication operations is significantly reduced (in some cases not less than an order}, however, when analyzing high-frequency processes, the time allotted to perform even this relatively small number of multiplication operations is not enough Because of the use of slow-acting multipliers. I. The closest in technical terms to the proposed one is a digital correlator containing two memory delay units (CDW) values of samples of the input and reference signals. Alov, the inputs of which are the inputs of the correlator, the outputs are connected to the multiplier inputs, and the address inputs are associated with the corresponding address makers in the write and read modes, the multiplier output is connected to the information input of the Jtlpo memory block (BPP), the address inputs through which the multiplexer is connected either to the output of the address counter 4 in the write mode) or to the output of the read address generator, whose information input is connected to the memory of the address, the output of the control panel is connected to the accumulating adder, the generator p pulses (GI outputs connected to address makers, memory blocks of addresses, from the control of the multiplexer input and from the inputs to the record - reading of the BNP 2. This device allows N / Q (where -N is the number of CCF computational cycles, Q is the number of samples of the reference signal.) The time required for the multiplication operations to be reduced by reducing the number of multiplication operations. However, in a number of cases when processing fast processes, even when using ultrafast multipliers, the multiplication process takes considerable time. In such cases, the problem is solved by parallel connection of Several identical multipliers that are complex r rhythmic devices. The purpose of the invention. Improving the speed of the correlator. The goal is achieved by the fact that in a digital correlator containing a memory block, the output of which is connected to the first input | Liwa: a cyMiViaTopa, and the address input is connected to the multiplexer output, the write input of the memory block is combined and connected to the first input of the synchronization unit, the second output of which is connected to the control input of the multiplexer, the read input of the memory block and control of the input of the fixed memory block whose output is connected to the first input of the address reader The second input of which is connected to the third output of the synchronization unit, the output of the read address generator is connected to the first information input of the multiplexer, the second information input of which is connected to the output of the write address counter, the input sample register, the second accumulator and the shift register, the control input of which is connected to the first output of the synchronization unit, and the output is connected to the information input of the memory unit; the information input of the shift register is connected to the output of the second input A fuel adder, the first input of which is connected to the output of the input sample register, the input of which is combined with the second input of the second accumulating adder and is the information input of the correlator. . FIG. 1 shows a digital correlator block diagram; in fig. 2 is a block diagram of a read address driver. The correlator contains the input sample register 1, the first accumulator cyMi iaTop 2, the shift register 3 connected in series and the memory block 4, the second accumulating adder 5, the first input of which is connected to the output of register 1 of the input sample, and the second input is combined with the input of the sample register and is the input to the correlator. The input of the first accumulating adder 5 is connected to the output of memory block 4, sequentially connected synchronization block 6, address 7 write counter and multiplexer 8, output connected to the address input of memory block 4, the input of address 7 write counter is additionally connected to the write input of memory block 4 TI and a control input of the shift register 3, the second output of the synchronization unit 6 through the serially connected memory unit 9 and the read address generator 10 are connected to the second information input of the multiplexer 8, the stroke of the fixed memory block 9 is additionally connected to the control input of the multiplexer 8 and the read input of the memory block 4, the third output of the synchronization block b is connected to the control input of the address generator 10 addresses.

The read address driver is analogous to 2 and contains a counter 1 and an adder 12, the first input of which is connected to the output of the counter. The second input of the adder 12 and the input of the counter 11 are respectively the first 13 and second 14 inputs of the former, the output 15 of which is the output of the adder.

The synchronization unit 6, as in the known device 2, contains a crystal oscillator and a set of controlled, dividers, from the outputs of which the clock pulses of a certain frequency and duration are removed

The digital correlator works with the following image.

Each input sample is written to input sample register 1, where its doubled value is stored during the cycle, until the next incoming sample arrives.

Doubling the code in register 1 of the input sample is carried out by shifting it by one bit towards the high bits of register 1 relative to the bits of the second accumulating adder 2 of the same name. Thus, the outputs of the bits of register 1 of the input sample are connected to the bits of the accumulating adder 2, the numbers of which differ by one from the corresponding bit numbers of the register 1. Simultaneously, the input signal is sampled through the second accumulating adder 5 into the register 3; the offset from which the product of the input selection Orcs per unit (one of the values of the reference signal) is recorded in memory block 4. In shift register 3, the code of the input sample value shifts the bit towards the higher bit, thereby forming each code step at the parallel outputs of the code product shift register 3 by the row numbers 2 °, 2, ..., 2. During the shift of the bit grid code, the doubled value of the input sample from the register 1 of the sample enters the accumulating adder, where it is added to the input sample value previously recorded there, i.e., the output sample of the adder 5 is formed at the output of the accumulator 5 by a code equal to 3. This Institution in shift register 3 sequentially multiplied by the number of 2 °, 2, 2, 2,. 2 (multiplying by 2 ° does not take time), the results are fed to memory block 4.

Summation in accumulative adder 5 (formation of the input sample by odd-numbered values of the reference signal) and subsequent shift of the obtained binary product code by the bit grid of shift register 3 (formation of the input-sample products by the counted values of the reference signal). carried out until the code of this input sample is multiplied by all possible 5 values of the reference signal. Each cycle ends by resetting the accumulator 5 and the shift register 3 to zero. Thus, the average time to perform a single multiply operation is less than the time it takes to perform the cy cyvi operation and (usually, it is more laborious than a bit-shifted grid) due to the parallel execution of operations. The address 7 record counter in each cycle generates Q address codes, and in N cycles, NQ addresses, after which it zeroes out and the process of generating address address codes is repeated. Thus, the total memory capacity of memory block 4 is N Q cells (i-bit binary product is stored in each cell).

When calculating each ordinate of the CCF, the summation of 2 products coming from the output of memory block 4 is carried out by accumulating the memory cells in the accumulating adder. The read address generator 10 sequentially generates the addresses of the cells of the memory 4 with a constant memory block 9 (the memory of the read addresses) in which the N values of the address codes of the memory 4 are stored, taking into account the distribution of sample values of the reference signal over the implementation length (N) and the recording sequence in block 4 of the memory of the generated works. Changing read addresses from cycle to cycle is performed in address generator 10 by adding modulo the HQ code defining the cycle number with the code issued in this reading text by the permanent memory unit 9.

Thus, compared with the prototype, the time required for performing multiplication operations is significantly reduced by eliminating redundancy when performing arithmetic operations that compute the ICF ordinates.

In the prototype, the execution of one multiplication operation is spent: g of the ISS, and in the proposed correlating PGG, the average time spent on performing a similar operation is reduced more than 10 times using the common element base (the same degree of integration).

The proposed device, while preserving the accuracy parameters of the prototype, has a much larger b: astro action, a smaller amount of RAM and a simplified structure.

The time required for a prototype to perform a multiplication operation in a cycle is determined by how | lil, and by using ultrafast multipliers, and therefore complex, cumbersome and expensive, the time to perform one multiplication can be reduced to the time to perform one simple conditional logical operation (read, sum and so on). d.) In the proposed correlator, the average time for performing the multiplication operation is always than the time for performing one multiplication operation in the prototype, since the process of forming the products in the proposed device occurs in parallel: multiplication by an odd code in the accumulating adder by performing one totalization operation simultaneously in the shift register multiplication occurs by codes equal to 2, 2 2, ... 2 bitwise codes shift,

The total memory capacity of the correlator is reduced by V +2 Q cells (removal from

S of the prototype of two memory delay blocks with a total capacity of N + Q -1ecs, one memory block of addresses with a capacity of N cells and an increase in the memory capacity of the second block of addresses per N -Q cells).

0 In addition, general instrumentation

the costs are reduced due to the simplified structure of the multiplier {static register accumulating the adder and shift register) and removing devices for recording and reading addresses, two memory delay blocks.

Compared with the base object (correlator F 7016) proposed

The Q correlator has a wider processing bandwidth for input signals due to a higher (not less than 600 times) speed, there are no additional losses (4: 1.5%) in the accuracy of ICF ordinate measurements.

The use of devices with charge coupling (CCD) as a shift register makes it possible to increase the efficiency of the proposed device.

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ABOUT

Claims (1)

A DIGITAL CORRELATOR containing a memory unit, the output of which is connected to the input of the first accumulating adder, and the address input is connected to the output of the multiplexer, the recording input of the memory unit is combined with the input of the address recording counter and connected to the first output of the synchronization unit, the second output of which is connected to the control input of the multiplexer , the read input of the memory block and the control input of the block \ read-only memory, the output of which is connected to the first input of the read address generator, the second input of which is connected to to the fourth output of the synchronization unit, the output of the read address generator is connected to the first information input of the multiplexer, the second information input of which is connected to the output of the write address counter, characterized in that, in order to increase the correlator speed, an input sample register, a second accumulating adder and a shift register are introduced into it whose control input is connected to the first output of the synchronization unit, and the output is connected to the information- $ input of the memory unit, the information input of the shift register By connecting the output of the second accumulator having a first input connected to the output the input sample register, the input of which is combined with a second input of the accumulator and a data input of the correlator.