SU1124325A1 - Device for selecting signals - Google Patents

Abstract

A DEVICE FOR SIGNAL IMPLEMENTATION, containing a data register, whose information output is connected to the first input of a multiplier, the output of which is connected to the first input of the first adder, the information output of the result register is connected to the second input of the first adder and is an information output of the device, whose information input is an information input of the data register, a first and a second memory block, a second adder, characterized in that. in order to increase speed, the first and second counters are introduced into it, the OR element and the clock pulse generator, the output of which is connected to the first input of the OR element, the output of which is connected to the counting input of the first counter, the information output of which is connected to the first input of the second adder and address input the first memory block, the information output and input of which are connected respectively to the second input of the multiplier and the information output of the data register, the overflow output of the first counter is the output After completing the calculation of the device, it is connected to the stop input (L of the clock pulse generator, the input is: the trigger of which is the device start input and is connected to the second input of the OR element and the counting input of the second counter, whose information output is connected to the second input of the second adder, output which is connected to the address input of the second memory block, the information input and outputs of which are connected respectively to the output of the first adder and information input of the result register, and the third input of the ele. OR is the device mode input.

Description

The invention relates to geophysics, in particular to seismic exploration, and is intended to separate signals by convolution, i.e. of the type ,,, - V ,, x ,,., L..2.u..1}. A device for performing logical operations is known, comprising seven sections of a junction, each of which includes two multiplication blocks. The number of multiply-adding sections is variable and depends on the required device performance. A disadvantage of the known device is the high cost of the equipment. The closest to the proposed technical entity is a tool for processing an array of numbers that contains the register of the operator of numbers X, the register of the operator of numbers Y, a multiplication unit, four memory blocks, a second multiplication unit, two intermediate result registers, two and two result registers, the output of the data register is connected via smart ITEL to the first input of the first adder, the output of the result register is the output of device 2. The disadvantages of the known device are a large amount of equipment and the need to form arrays of numbers X and Y, to store these arrays, and the results of the sum of products loading the computer channel by sending data. The purpose of the invention is to increase the fastness. This goal is achieved in that the device containing the data register, the information output of which is connected to the first multiplier input, the output of which is connected to the first input of the first adder, the information output of the result register is connected to the second input the first adder and is the information output of the device, whose information input is the data input of the data register, the first and second memory blocks, the second adder, the first and second counters , the OR element and the clock pulse generator, the output of which is connected to the first input of the OR element, the output of which is connected to the counting input of the first counter, the information output of which is connected to the first input of the second adder and the address input of the first memory block, the information output and input of which are connected respectively to the second input of the multiplier and the information output of the data register, the overflow output of the first counter is the output of the end of the calculation of the device and is connected to the input of the generator stop that pulses, the startup input of which is the startup input of the device startup device and connected to the third input of the OR element and the counting input of the second counter, whose information output is connected to the second input of the second adder, the output of which is connected to the address input of the second memory block, information input and the output of which is connected respectively to the output of the first adder and the information input of the result register, and the third input of the OR element is an input of the device mode. Improving device performance is achieved by using two standard memory blocks, the amount of which depends on the conditions of the tasks. Placing an array of operator X in a memory block frees the computer from storing this data in its memory and from multiple transfers via a computer channel. Placing the result of the summation allows for adding the number y {multiplying it by the array X and simultaneously adding the result of the array X by yj, which also saves the time through the computer channel. The drawing shows the block diagram of the device. The device contains counters 1 and 2, a sweeper 3, a memory block 4, a result register 5, an adder 6, a multiplier 7, a memory block 8, an 8 clock pulse generator, an OR 10 element, a data register 11. The operation of the device begins with the insertion of an array,, X2, ..., memory block 8, whose cell addresses form counter 1, changing

31

the states of this counter are determined by the number of pulses when xf is applied.

After the entire X array has been inserted by the signal, the mode switches the element OR 10. The first number of the array arrives, resets the first counter 1, changes by one state on the second counter 2, the clock generator 9 is started, the pulses of which through the element OR 10 change the state the counter 1 and the output of the adder 3 are formed by the addresses of the cells of memory block 4 by the formula, the number j multiplied with the entire array X at the output of the multiplier 7, is added to the output of the register 5, the initial value of which is zero for each 4 memory cell. As a result, in

The last number stops the enumeration of the counter 1 addresses. The device waits for the next value. And so on until the last value.

To match the operating modes of the device and the computer in time, there is a buffer data register 11 at the device input, and a result register 5 at the output.

LUSe calculating all the values given in block pa 1233254

memory element 4 is recorded

tats:

Cells 1 2 m

X | Y,

four-

The last number stops enumerating the addresses of the counter 1. The device waits for the second value of Y. The second value of V y changes the value of counter 2 by one, at the output of adder 3, cell addresses + 1 are formed, i.e. the address of memory block 4 is different from the address of memory block 8 by +1. As a result, the output of multiplier 7 appears the results of array multiply, X2 ..., X, ..., X with the number y, and since the input of the adder 6 is the result of the previous summation, then in the cells of block 4 memory data is written in the following way

2 3 XzVi X, y,

at

Ug X Y, X ,, Hu ,, ,,

These are sent by the computer mainline.

A device built according to this scheme can work with any main line of a computer and will allow to increase processing speed in comparison with the known ones by combining in time the support of repeated enumeration of X values and simultaneous summation of the result with the previously obtained ones.

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D) S.KH.U.

Claims (1)

A device for signal acquisition, containing a data register, the information output of which is connected to the first input of the multiplier, the output of which is connected to the first input of the first adder, the information output of the result register is connected to the second input of the first adder and is the information output of the device, the information input of which is the information input data register, the first and second memory blocks, the second adder, characterized in that, in order to increase performance, the first and second counts are introduced into it clocks, an OR element and a clock pulse generator, the output of which is connected to the first input of the OR element, the output of which is connected to the counting input of the first counter, the information output of which is connected to the first input of the second adder and the address input of the first memory block, the information output and input of which are connected respectively, to the second input of the multiplier and the information output of the data register, the overflow output of the first counter is the output of the end of the device’s calculations and is connected to the generator stop input clock pulse, the trigger input of which is the trigger input of the device and is connected to the second input of the OR element and the counting input g of the second counter, the information output of which is ** connected to the second input of the second adder, the output of which is. It is connected to the address input of the second memory block, the information inputs and outputs of which are connected respectively to the output of the first adder and the information input of the result register, and the third input of the OR element is the input of the set mode KZ 4 ^ WITH N3 joint venture. 1 11