SU1418749A1 - Device for multiplying matrices - Google Patents

Abstract

The invention relates to a computational technique and can be used for matrix operations. The aim of the invention is to improve the speed. The device contains registers 1-4, memory blocks 5-8, registers 9-12, adders 13-16, registers 17-20, control block 21. The device performs simultaneous calculation of all elements of the result matrix. „3 silt

Description

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 The invention relates to computing and can be used for matrix operations.

The aim of the invention is to improve the speed

Fig. 1 shows the functional diagram of the device, Fig. 2 shows the functional diagram of the control unit, Fig. 3 shows the time diagram of the operation of the control unit,; The device contains registers 1-4, | blocky 5-8 memory, registers 9-12, sum | matory 13-16j registers 17--20 and block

.121 control, element 22 And comparison circuit | 23, trigger 24, generator 25 pulses, counter 26d comparison circuit 27, element 28, inputs 29and 29.4 elements of the first matrix, inputs 30.1-30.4 elements of the second matrix

: devices 9 outputs. 31 a 1-31.4 devices: cts.

i The device works as a leader, once:

Registers are working in mode. parallel recording of information. gistry. 17-20 also work in mode

parallel recording of information. Registers 1–4 operate in a mode of recording information in a ratios and in the sequential shift of informational information.

The device produces the multiplication of two matrices 22. Let us begin the consideration of the process of the device operation at the moment of receiving the queue values of matrix elements. B. In this case, on the third run of the control unit 21, there is a high potential (FIG. 36) allowing the registers to operate in a parallel information recording mode. The pulse from the fourth output of block 21 (FGGSv) records the elements of the matrix A into registers 1--4. In this case, the element all is written to register 1, the element a12 is written into register 1, and the element a21 is recorded into register 3 4 - element a22. In registers 9-12, the elements of the mat are written. At the same time, the element is written to the lower bits of registers 9 and 11: ,21,) and in the first order - element b11j to the senior

The bits of the registers 10 and 12 are the element b12, and in the younger ones the element b.22, registers 17–20 are zeroed by this pulse.

After receiving the elements of the matrices A and B, a high level of performance is generated at the second output of block 21 (fig3), which enables the operation of registers 1-4

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five

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in the sequential shift mode information. The pulses from the first output of the control unit 21 (FIG. A) start shifting the information towards the higher bits. In this block, blocks 5–8 of the memory are preliminarily recorded in the memory cells the result of multiplying the address code of these memory cells. As a result, the output of the memory blocks is. These always get the result of multiplying the input codes. Since the elements of the matrix A are bitwise received, it is necessary to accumulate the results of the bitwise multiplication in order to obtain the result of the matrix multiplication. This accumulation is carried out in accumulative adders executed on the adder and register. - In addition, during accumulation, the previous result is multiplied in the process of accumulation by two o. This is accomplished by the fact that the outputs from the registers go to the first inputs of the adders with a shift by one bit to the higher ones. This and carried out the multiplication by two. Writing information into registers 17-20 is carried out on the falling edge of a pulse from the first output of control unit 21; (FIG. 3d). Thus, at the end of the calculation, the output of the register 17 is an element of the matrix a11-Ы .1 + a12 |, B12, at the register output 18 - .b12 + a12.b12, etc. For the sake of understanding, let's write down the contents of the memory cells of memory block 5, depending on the input bits of registers 1 and 2; , V.OUT Exit Content

register-register-block 5

pa 1 pa 2 memory -.

About 1 About 1

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In the future, the operation of the device is similar. . .

Control device 21 operates

.in the following way,

The generator 25 accumulates a sequence of incoming pulses (FIG. Pro), Counter 26 counts these pulses. Comparison device 23 has a comparison code by one m / h bit smaller than the comparison code of device 27 o. Thus, device 23 triggers first, which switches trigger 24 to the zero state (Fig. 36). Then, the device 27 is triggered, which returns the trigger to the one state (Fig. 3d). When the trigger is in the zero state, one pulse passes through element 28 (Fig. 3b). When the trigger is in the single state, the pulses pass through element 22 ().

Claims (1)

Invention Formula A device for multiplying matrices containing two memory blocks, a sum, a torus, and a control block, is necessary so that, in order to improve speed, two memory blocks are additionally inserted into it. , twelve registers, with the information inputs of the registers from the first to the fourth are respectively connected to the inputs of the elements of the first matrix of the device from the first to the fourth, the first output of the reference block is connected to the inputs of the first to fourth synchronous pulses of the registers with the synchro rods O, on the eighth — the second output of the control unit, is connected to the inputs of the shift mode. The registries from the first to the fourth, whose recording mode input is connected to the third output of the control unit, the fourth output to 10 15 418749. Secondly, it is connected to the inputs of clock pulses from the first to fourth register and from the ninth to the twelve, as well as to the installation inputs in О registers from the fifth to the eighth, the inputs of the group of bits. The addresses of the first memory block are connected to the outputs of the first, second and second the ninth registers, the information inputs of the registers from the ninth to the twentieth 1st are connected respectively to the inputs of the elements of the second matrix of the device from the first to the fourth, the inputs of the group of address bits of the second memory block are connected to the outputs of the first, second and ten that reg The inputs, the group of bits of the address of the third memory block are connected to the outputs of the third, fourth, and eleventh registers, the groups of bits, the addresses of the fourth memory block are connected to the outputs of the third, fourth, and twelve registers, the outputs of the memory blocks from the first on the quarter are connected respectively to the first inputs of the adders from the first to the quarter, the outputs of which are connected respectively to the information inputs of the registers from the first to the quarter, the outputs of which are connected to the outputs of the device with the first to the fourth and the second inputs of the adders from the first to the fourth. 20 25 thirty Thebes.2 but 1 I I I I I I I I I I 1 I LI ULJJ L 3 1 i M i 1 I i 1 I 11LLLLM Fi.Z