SU1751858A1 - Device for calculation of remainder to modulus of binary number - Google Patents

Abstract

A device for calculating the absolute value of a binary number refers to computing and can be used in specialized computing devices operating in a JUICE. The purpose of the invention is to reduce hardware costs. The goal is achieved by reducing the convolution block, the switch, and the redistribution of links between the remaining blocks. The device contains an input register 1. a convolution unit 2, a modulo-3 adder, a unit 4 multiplied by a constant modulo, a switch 5, registers 6 and 7, a group of clock inputs 8.1–8.4, output 9. 1 sludge.

Description

The invention relates to computer technology and can be used to interface computing devices operating in a system of residual classes. 5

A device is known for calculating the remainder modulo a binary number, containing the first and second registers, the input register, the first and second switches, the unit of multiplication by a constant modulo and 10 adder modulo.

A disadvantage of the known device is. high hardware costs.

Closest to the invention is a device for calculating the remainder of 15 modulo a binary number containing an input register, first and second convolution blocks modulo, first and second registers, first and second commutators, a constant multiplier module modulo and 20 modulo adders, moreover the first and second block and convolution modulo., and the outputs of the bits from the (1t-1) -th to (1 _t- t) -th input register are connected to the input of the first convolution block modulo (m> n. where η 25 module

K_ m, (K is the bit capacity of a binary number), the output of which is connected to the second information input of the first switch, the outputs of the bits from (Im - m-1) -ro through the (Im - 2m) input register are connected to the input of the convolution unit by the module whose output is connected to the input of the second term of the adder modulo, the output of the first switch is connected to the input of the multiplication unit by a constant modulo-.

a line whose output is connected to the input of the first term of the adder modulo, the output of which is the output of the device and connected to the information inputs 40 of the first and second register, the outputs of which are connected respectively to the first and second information inputs of the second switch, the output of which is connected to the first information input of the first 45 of the switch, the input enable shift of the input register, the control inputs of the first and second switches and the input enable signals of the first and second registers are connected respectively with the clock. 50 device group inputs.

A disadvantage of the known device is the high hardware costs. '

The aim of the invention is to reduce hardware costs. 55

This goal is achieved by the fact that from a known device containing an input register, two convolution blocks, two switches, a constant multiplication block, a modulo adder, two registers, it is possible to remove one convolution block modulo and one switch.

Then the device will contain an input register, a convolution unit, an adder modulo, a constant multiplier unit, two registers and a switch, and the outputs of the input register from (1 _t -1) to (1 _t- t) th are connected to the convolution unit , the outputs of the convolution unit are connected to the first inputs of the adder modulo, the second inputs of the adder modulo is the output of the switch, the output of the adder modulo is the input of the unit of multiplication modulo, its output is an input for storing intermediate results registers, their outputs are inputs of the switch.

The basis of the device is the following.

The binary K-bit number X can be represented as

X = a _K -i2 ^K ' ¹ + ... ai2 ¹ + ao2 ° (1)

Using calculations by the Horner scheme, we transform expression (1) to a form convenient for finding the remainder of x from the number X modulo P.

x = IXIp ~ I ... IEk-1 2 I _p + ... ai | p x x2 | ⁺ _p + aoGy (2)

Suppose that the selected module-has a variety of order n. We divide the binary representation of the number X into groups of m binary digits, moreover, m> n. Taking into account the partition, it transforms expression (2) to the form x = I ... I Ai | ⁺ p 2 ^t | ⁺ p + ...} Αι | ⁺ p G _P : (3)

Ai ⁼ 3im 2 + ... + aim-m + 1 2 + aim-m.

where I =] K / m [, ϊ = 1,1,

Denote Bi = I Ai Г _р and / 3 = 12 ^m Γ _Ρ , bringing (3) to the form:

x = I ... I Βιβ \ ⁺ ρ + В | -1 Гр · β \ ⁺ ρ + ... + ΒιΓρ (4)

Moreover, / 3 is a constant calculated in advance.

Thus, expression (4) allows you to implement the remainder of the original number modulo R.

The drawing shows a functional diagram of a device for calculating the remainder of the modulus of a binary number.

A device for calculating the remainder modulo contains an input register 1, a convolution unit 2, an adder modulo 3. A multiplier by a constant modulo 4. registers. 6 and 7, switch 5, output of device 9, group of clock inputs 8.1-8.4 of the device.

The input register 1, a functionally known element, has 1 _t bits, from 0 to the (1t-1) th control input, when a signal is fed to 5, the contents of register 1 are shifted m bits to the left.

The convolution unit 2 is a functionally known element. The outputs of the input register 1 from (1t-1) -th to (1t-t) -th are connected to convolution block 2.

Adder modulo 3 known functional element. The outputs of convolution unit 2 and the switch are connected to its inputs

5. The outputs of the adder modulo 3 are connected to the known element of the block 4 multiplication by a constant modulo. The output of block 4 is connected to registers 6 and 7, which are known functionally, which are in turn connected to switch 5. The 20 registers are written to registers 6 and 7 using clock pulses 8.3–8.4. The operation of the switch is controlled by pulse 8.2., The output of adder 3 is also the output of the device. -25

The device operates as follows.

In the initial state in register 1 is the code of the converted number X. Registers 6 and 7 are reset. thirty

At the first measure, the number Aj. defined by m high digits of the converted number X, are converted by convolution unit 2 to remainder B modulo P.

On adder 3 modulo 35 addition B occurs with zero, since switch 5 is connected to registers b or 7. which are reset to zero. In the block of multiplication 4 by a constant modulo multiplication by a constant /? modulo R. 40

Thus, at the end of transients at the output of the multiplication block 4, we have

IB) β \ p.

The result of the multiplication is recorded at the moment of arrival of the pulse at input 8.3. to register 6.

On the second conversion step, at the moment the pulse arrives at input 8.1, the contents of register 1 are shifted to the left by 50 bits. The switch 5 is connected to the input of the adder 3 register 6. The contents of the register 6 through the switch 5 is fed to the second inputs of the adder modulo 3. The first inputs of which receives the next 55 VM and the sum goes to the input of the multiplication block 4. At the end of transients, we have the result

II IB) /? | ⁺ p + Bi ll - /? | ⁺ p, which at the moment of arrival of the pulse to input 8.4 is recorded in register 7.

Further, the conversion process occurs in a similar way.

In the last (1-1) -th cycle, the final result is removed from the output of the adder 3 to the output of the device 9.

The proposed device lacks two units: a convolution unit and a switch, which provides the following savings. For instance. if the switch is built on AND circuits, then two-input I circuits are reduced by 2 ^t . If the convolution unit has a decoder and OR circuits and the decoder is pyramidal, then 4 (2 ^t ' ¹ - 1) two-input AND elements are required, as well as the costs of the elements OR, which will also grow with the growth of the module. The gain in equipment is obvious, while in terms of speed, the proposed device loses to the prototype in only one beat. The advantage of the proposed device is achieved by changing the connection between the convolution unit and the adder modulo and the unit of multiplication by a constant modulo.

Claims (1)

Claim A device for calculating the remainder of the absolute value of a binary number, containing an adder modulo, a unit of multiplication by a constant modulo, an input register, the outputs of / (1 _t -1) -th in (1t = t) -th of which are connected to the inputs of the convolution unit in to the module (where m> n, I =] K / m [, K is the bit capacity of the binary number, η is the bit capacity of the module), the information outputs of the first and second registers are connected to the information inputs of the switch, the input allows the shift of the input register, the control input of the switch, the input write permissions of the first and second registers are connected to the clock the inputs of the device group, characterized in that, in order to reduce hardware costs, the convolution unit outputs are connected to the first group of adders of the adder modulo, the second group of inputs of which are connected to the outputs of the switch, the adder output modulo is connected to the input of the multiplication unit by a constant a module whose output is connected to the information inputs of the first and second registers, the output of the adder modulo is the output of the device.