SU1695386A1 - Digital delay device - Google Patents

Abstract

The invention relates to computer technology, in particular to storage devices, and can be used as a multi-branch digital delay line with an adjustable delay time when building digital filters. The aim of the invention is to increase speed. The goal is achieved by introducing additional memory blocks 4. 1-4.N, 1 Il.

Description

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The invention relates to computer technology, namely to storage devices, and can be used as a multi-drop digital delay line with adjustable delay time when building digital filters.

The aim of the invention is to increase speed.

The drawing shows a functional diagram of the proposed device.

The device contains a counter 1, an arithmetic logic unit 2, a main memory block 3, additional blocks 4.1-4.N passwords, output registers 5.1-5.N, a clock input 6 of the device, information input 7 of the device, controlling input 8 devices, outputs 9.1-9.N devices.

 The device works as follows.,

Clock pulses are fed to the input of counter 1 and for each positive differential increase its contents by one, With the transition of the clock signal to the level of 1 block. 2 is set to broadcast information from input A to output, blocks 3 and 4.1-4. N memory - to read mode, output registers 5.1 to 5. M - write mode. In accordance with this setting, the data at the address set at the output of block 2 is read from memory block 3, 4.1-4.N and overwritten in the corresponding registers 5.1-5.M. Thus, the output information is set at the taps of the delay line. i With setting the clock signal to the level | About 2, the unit goes into the summation mode, the memory blocks 3 and 4.1–4. N - into the write mode, the output registers 5.1–5. N - into the read out mode. At the output of block 2, a code is set equal to the sum of the code from the output of counter 1 and the code specifying the pitch delay on input 8. At the address set at the output of block 2, the input information is recorded in memory block 3, the information from the first tap, those. from the output of register 5.1 to block 4.1 of memory, information from the second branch to block 4.2. memory

information from the last but one call - to

4.N memory block. Thus, information is recorded in the delay line. The maximum depth of the delay of the device is determined by the information capacity of the blocks 3 and 4.1-4.N of the memory.

The high speed and ability to control the depth of the delay allows the proposed device to be used in digital filtering devices.

Claims (1)

DETAILED DESCRIPTION OF THE INVENTION A digital delay device comprising a counter, the counting input of which is the clock input of the device and connected to the clock inputs of the main memory block and output registers, arithmetic logic unit whose output is connected to the address input of the main memory block, the information input of the memory block is the information input of the device, the output of the memory block is connected to the information input of the first register, register outputs are device outputs, characterized in that, with in order to improve the speed of the device, additional blocks of memory have been introduced into it, the address inputs of which are connected to the output of the arithmetic logic unit, clock inputs of additional blocks the memory is connected to the clock inputs of the counter and the arithmetic logic unit, the first information input of which is connected to the output of the counter, the input of the arithmetic logic unit delay value setting is the control input of the device, the information input of the first additional block is connected to the output of the first output register, the output the first additional block is connected to the address input of the second output register, the output of which is connected to the information input of the second additional memory block; the output is day output register is connected to the information input of the last additional memory block, the output of which is connected to the address input of the last output register.