SU1200289A1 - Microprogram control device - Google Patents

Description

The invention relates to computing and can be used in high-performance computing systems.

The purpose of the invention is to increase the speed of the firmware control device

Figure 1 shows the functional diagram of the firmware control device; Fig, 2 - the algorithm of the device; FIG. 3 shows the clock pulses supplied to the synchronous inputs of the device blocks.

The device will hold the memory block 1, the register of 2 micro-commands, the address counter 3, the micro-expansion register 4, the adder 5, the decoder 6, the And 7 element, the condition multiplexer 8, the information input 9, the condition input 10, the information output 11, inputs 12-14 clock pulses. Fig, 3 denotes the period Tz clock pulses or the cycle of operation of the device, the clock pulses 15 received at the device input 12, the clock pulses 16 received at the device input 13, the clock pulses 17 received at the device input 14.

The device is designed to work with a typical set of micro-commands. Suppose, for example, a microinstruction contains 16 bits, which are numbered from 0th to 5th 5th beginning with the youngest, Older 2 bits, 15th and 14th, define the format of the microcommand, and the code 00 contained in these bits, defines the 1st format, code 01 2nd format, code 10 - 3rd format, code 11 - 4th format. We suppose that format 1 corresponds to arithmetic, format 2 to logical operations, format 3 to load operations of the microcommand expansion register, format 4 to transfer operations. Suppose that in the 3rd format, the microcommand bits are distributed as follows: 15–14 is the microcommand format, .13 is the load direction of the microcommand expansion register; 12- type of transition (relative, absolute), 11-9- type of transition condition. (overflow, end of operation of the input-output block, t, d,); 8-0 - A (either the absolute address of the transition, or an increment to the current value of the counter 3 addresses).

Suppose that in the first format the transition operations are combined and arithmetic, i.e. for example, the 13th bit of the microcommand indicates the presence of a transition, while the rest determine the arithmetic by operation. It is logical dp

efficiency of the microinstructions system, such a combination can also be implemented in the microcommands of those formats in which there is at least one free bit, which will entail a change in the decoder circuit 6,

The first output of the register of 2 microinstructions connected to the first information input of the register 4 of the expansion of the microinstruction corresponds to 125 0) bits of the microinstruction, the second video input connected to the first control input of the register 4 and to the third input of the element 7, - 13 -th micro-command bit and, in the 3rd format, oti0 determines register 4 to be loaded either from register 2 or from device information input 9, and in the first format it determines the presence of a transition, the third output connected to the input

5 of the decoder 6, - (15-14) -th bits of the micro-command and determines its format,

In the micro expansion instruction register 4, the transition indication is loaded: the type of transition, the type of transition condition

0 and address A, toe. bits (12-o) register 2 microinstructions. The first output of register 4 is connected to the first information input of the adder 5 and 1 represents the code of either an increment of the relative transition address or the absolute transition address, the second output is connected to the control input of the selector 8 and represents the code of the type of transition condition, the third output

Q keys to the control input of the adder 5 and represents the code of the type of transition (absolute or relative),

On the adder 5, either a relative transition address is obtained by summing the base address coming from the second information input connected to the output of the counter 3 address and incrementing the address coming in on the first information input, or absolute, on the first information input.

Counter 3 addresses, depending on the value of the signal on the control 5 input The account / record connected to the output of the element 7, works either in the counting mode, or in the mode of recording the address of the transition from the information input connected to the output of the adder 5, First decoder output 6, connected to the second input of the AND element 7, corresponds to the first format of the junction microcommand, the second output, connected to the second control input of the register 4, corresponds to the third format of the microcommand and determines the resolution of the register 4 loading. The structure works as follows. With the arrival of the clock signal at the input 12 of the device from the block I of the microinstructions memory, register 2 is entered into the microcommand of loading the register 4 and in accordance with the code value of the first control input of the register 4 it is loaded, with the arrival of the clock signal at the input 14 of the device, or directly from register 2, or from the information input 9 of the device, and the second control input of register 4 receives the signal to discard the record from the second output of the decoder 6. After register 4 is loaded, the loop begins: from the first, they are selected sequentially from memory block I until a transition command appears, while at the second output of decoder 6 there is no signal allowing writing to register 4, and the Signal / recording of counter 3 address acts as an input signal 7 and causing the counting mode, since the second input of the element And 7 from the first output of the decoder 6 signal is not received. Counter 3 increases its content by one from the arrival of each clock pulse to the input 13 of the device. With the appearance on the register 2 microcommand transition. On the second output of register 2 and the first output of the decoder 6, signals appear, respectively, coming to the third and second inputs of the elements AND 7, If to i This moment came the signal of the condition of the transition to input 10 of the device then a transition condition signal appears at the output of multiplexer 8, determined by a signal code of the type of transition condition coming from the second output of register 4. At the output of AND 7, a signal appears that ensures that address 3 is output from the adder 5 output of the address code the first microinstruction cycle, and the process is repeated until completion of the cycle. With the end of the cycle, the transition condition is not generated, the transition condition signal is absent at the device input 10, and with the appearance of the micro-command transition at register 2 at the output of multiplexer 8 and therefore, at the output of element 7, the signal is absent unit 1, a micro-instruction is selected following the transition command.

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Claims (1)

(54) (57) A microprogram control device containing a memory block, a micro-register, a multiplexer, conditions, a decoder, an address counter, the output of which is connected to the address input of the memory block, the output of which is connected to the information input of the micro-register, whose sync input is connected to the input of the first clock pulse of the device, and the output with the output of the device, the information input of the conditions multiplexer is connected to the input of the conditions of the device, the sync input of the address counter is connected to the input of the second clock pulse of the device The output of the microcode instruction format command code is connected to the decoder input, characterized in that, in order to improve performance, it contains a microcommand expansion register, an adder, and an I element, the first and second information inputs of the microcommand expansion register being connected respectively to the output of the transition sign code microcommand register and information input of the device, outputs of the code of the transition address, condition code and code of the type of transition of the microcontrol expansion register are connected respectively to the first and the information input of the adder, the control input of the condition multiplexer and the control input of the adder, the second information input of which is connected to the output of the address counter, the input of the recording account of which is connected to the output of the And element, the first, second and third inputs of which are connected respectively to the output of the condition multiplexer, the first output of the decoder and the output of co / fa sign of the transition of the register of microcommands, the output of the adder is connected to the information input of the address counter, the second output of the decoder is connected to the input is enabled I write register microinstruction expansion, the clock input of the recording direction and which are respectively connected to a third clock input apparatus and the output characteristic code transition microinstruction register.