SU1117637A1 - Firmware control unit - Google Patents

Abstract

A MICROPROGRAM CONTROL DEVICE, containing two blocks of memory, a counter and a register, the output of the counter is connected to the address input of the first memory block, the output of which is connected to the information input of the register, the output of which is the output of the device, characterized in that in order to reduce the equipment, the clock input of the device is connected to the counting and clock inputs of the counter and the clock input of the register, the control inputs of the record and the account of the counter are connected to the first output of the second memory unit and to the control input of The register register, the second output and the information input of the second memory block are connected respectively to the information input of the counter and to the input of the logic conditions of the device, the output of the counter is connected to the address input (L of the second memory block.

Description

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The invention relates to digital computing and automation and can be used in microprogram control devices of computers.

A firmware control device containing a block is known; memory of microinstructions, the memory block of the initial addresses of the synchronization block, the register of microinstructions, the output of which is the output of the device, and the input is connected to the output of the memory array of microcommands РЗ

However, the device has a low speed due to the impossibility of combining the micro-command sample with the calculation of the address of the next micro-command.

Known microprogram set. control device containing microinstructions memory block, microinstructions register, initial addresses memory block, microinstruction address counter, AND group, read register, microinstruction chain length counter, synchronization block 2.

The disadvantage of the device is high hardware costs for its. implementation ..

The aim of the invention is to reduce equipment.

The goal is achieved by the fact that in a microprogrammed control device containing two memory blocks, a counter and a register, with. the output of the counter is connected to the address input of the first memory block, the output of which is connected to the information input of the register, the output of which is the output of the device, the clock input of the device is connected to the counting and clock inputs of the counter and the clock input of the register, the recording control inputs and the counting counter connected to the first output of the second memory block and to the register control input; the second output and the information input of the second memory block are connected respectively to the in-. by the formation input of the counter and with the input of the logical conditions of the device, the output of the counter is connected to the address input of the second memory block.

The device contains a counter I, a memory block 2, a memory block 3, a register 4, a clock input 5 of the device,

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input 6 logical conditions of the device, outputs 7 and 8 of the block 3.

The clock 1 contains the counting control input, such as the C2 input input and the y input, 2 recording controls. Register 4 contains the clock input Cr and input V of the control of the gate

The memory tray 2 is a permanent storage device.

, 0 Memory block 3 is a programmable logic array. Output 7 of memory block 3 is a sign (unit potential) of the presence of a conditional branch instruction, output 85 is the code of the initial address of the transition.

The firmware control device operates as follows.

At the initial moment of time, counter 1 is reset. On admission to

0 the input 5 clock pulse by the front of the pulse to the input C (at zero potential) sets the first address. Next, at this address From block 2, a micro-command is read and a clock pulse is cut at the input of the SL to read the micro-command into register 4. At the input 5, the next clock signal is received and the next micro-command is found.

O Thus, linear firmware sections are formed. When set to. counter. The address of the micro-command, which is a micro-command of the transition, is triggered by block 3 (logical conditions go out at input 6) and a single signal appears at output 7 (recording from input V to register 4 is blocked). From the output 8 of the block 3 to the information input of the counter 1, the code of the address of the transition is received. The next clock pulse (the front. On C a) the code of the address of the transition address is written (at the output 7, zero potential is set5). Next, a microcommand read at the address of the transition is written to the register 4 with a pulse slice.

. After performing the sequential

About these microinstructions of the transition on the corresponding pulse on dhrde 5 at the output of counter 1 appears the address of the microcommand of the return and linear sequence. From this address and the corresponding conditions from input 6, block 3 is triggered again.

The application of the invention allows to reduce the amount of equipment.

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Claims (1)

(57 ^ FIRMWARE CONTROL DEVICE, comprising two <memory, counter and register blocks, the counter output being connected to the address input of the first memory block, the output of which is connected to the register information input, the output of which is the device output, characterized in that, for the purpose of reduction equipment, the clock input of the device is connected to the counting and clock inputs of the counter and to the clock input of the register, the control inputs of the recording and counting of the counter are connected to the first output of the second memory unit and to the recording control input th register output and second informational input of the second memory block are connected correspondingly with the information vhodomschetchika and to the input logic conditions the device counter 18 output is coupled to the address input. second memory block.