SU1728849A1 - Programmable controller - Google Patents

Abstract

The invention relates to automation and computing and can be used in real-time control of systems. The purpose of the invention is the expansion of the field of application when managing systems according to a rigid time sequence diagram. The device contains an input pulse counter 5, an address counter 9, a program memory block 7, an output register 3 and a decoder 2. In addition, an encoder 12, AND elements 10,15, and OR 6 elements are included to ensure response to abnormal situations. , 17, as well as the demultiplexer 1 and multiplexer 11, pulse generator 16, four-bit shift register 14. In the device, the control program commands are sampled at different frequencies, and when an emergency situation occurs, it goes to the corresponding programs. 1 il.

Description

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The invention relates to automation and computing and can be used as a control device for real-time systems.

A control device is known comprising a serially connected address block, a memory block, an output register and a decoder, the output of which is the output of the device.

The disadvantage of this device is that it is not able to respond to abnormal (emergency) situations that may occur in the system controlled by this device.

The closest in technical essence to the present invention is a device for programmed control, comprising an input counter, the input of which is the input of the device, as well as serially connected address counter, memory block, output register and decoder whose output is the output of the device.

The disadvantage of this device is also the inability to respond to abnormal situations that may occur in the system it controls.

The aim of the invention is to expand the field of application when managing systems according to a rigid time cyclogram.

The goal is achieved by the fact that a program control unit containing a program memory block, the bit outputs of which are connected to the corresponding information inputs of the output register, the outputs of the higher bits of which are connected to the inputs of the decoder, the group of outputs of which are connected with a group of device outputs, as well as an input pulse counter, a delay element, the input of which is connected to the readout control input of the program memory block, and the output to the counting input counter addresses whose output is connected to the address input of a program's permanent memory block; a demultiplexer, multiplexer, encoder, first OR element, first AND element, prohibition element and control unit containing a four-bit shift register, whose information input is connected to the second output And, the first input of which is connected to the output of the pulse generator, the second input to the first output of the control unit and to the output of the second OR element, whose inputs are connected to the group of information inputs in a control unit whose output group is connected to a group

the information outputs of the four-bit shifting register, the first input of the first element OR is connected to the output of the input pulse counter, the output of the first element OR is connected to the read control input of the program memory block, and the second input to the first output of the group of information outputs of the control unit, the second the output of the group of information outputs to the input of zeroing the input pulse counter and the address counter, the third output to the first input of the first element I, the output of which is connected to the information input address and the second input with the output of the multiplexer, the control input of which is connected to the corresponding information input of the control unit input group, to the output of the decoder and to the control input of the demultiplexer, the first information input of the multiplexer is connected to the first output of the demultiplexer, the second output of which is connected to the input setup of the input pulse counter, and the group of information inputs of the demultiplexer is connected to the outputs of the lower bits of the output register, the counting input of the input Meters withstand pulses connected to the output element of the ban, the first input coupled to the first output of the control unit and the second input - to the output of the software for controlling the second multiplexer data input coupled to the output of the encoder, which input group connected with the group of information inputs of the device.

The drawing shows a structural diagram of the proposed device.

The device contains a demultiplexer 1, a decoder 2, an output register 3, a prohibition element 4, an input counter 5 pulses, an OR element 6, a program memory block 7, a delay element 8, an address counter 9, an AND 10 element, a multiplexer 11, an encoder 12 and a control unit 13. The latter contains a four-bit shift register 14, the element AND 15, the generator of 16 pulses and the element OR 17.

Each cell of the program constant memory unit 7 contains an operation code and a time interval code through which the next command should be executed. The initial recording in block 7 of the program permanent memory can be made by introducing an additional address input and the entry of the recording strobe (the initial recording circuit is not shown)

The device works as follows.

In the initial state, units of all pulses of the input counter 5 pulses are recorded, the counter 9 of the address is reset, which corresponds to the address of the first memory cell of the program 7 memory block, in the low-order digit of the four-digit shift register 14 a unit is written not shown).

Input frequency signal received on. the input 18 of the device for program control, the passage through the open on the control input of the prohibition element 4, causes the appearance of an overflow signal of the input pulse counter 5, which, having passed the OR element, goes to the read control of the program 7 of the program, reads the contents of the first memory cell in the output register 3. The operation code of the high bits of the register 3 is fed to the input of the decoder 2, and a control signal appears on the group of device outputs 19, which is fed to the control system mu. From the output of the least significant bits of the output register 3, the code of the time interval through which the next command should be executed, the passage of the demultiplexer 1, is written into the input counter of 5 pulses. The signal delayed by delay element 8 increases the contents of address counter 9 by one, forming the address of the next command of the control program. In the absence of an abnormal situation in the controlled system (signals at information inputs 20), the operation of the device is similar, i.e. after the execution of the 1st command after a specified time, the (1 + 1) - command is executed.

When an abnormal situation occurs in the system, one of the information inputs 20 of the device receives the corresponding device interruption signal. This signal, the pass element OR 17, closes the inhibit element 4 at the control input and opens the element 15. The signals of a certain frequency produced by the pulse generator 16 pass the open element 15 and enter the information input of the four-bit shift register 14.

According to the first pulse from the generator of 16 pulses, the contents of the input counter of 5 pulses and the counter 9 of the address are reset. The second pulse opens And 10 at the control input, and the code for the cause of the interruption, formed in the encoder 12, through the multiplexer 11 and the open element 10 is recorded in the address counter 9. This code is the block 7 cell address.

the program memory from which the emergency program is started. The third pulse at the first output of the group of information outputs of the control unit is a signal that, having passed the OR 6 element, is fed to the read control input of the program 7 memory, reads the contents of that cell whose address is written in the counter 9 of the address . On the fourth pulse from the pulse generator 16, a unit is shifted from the highest bit of the four-bit shift register 14 to the lower bit, which ensures that the next possible interrupt is performed. The duration of the signals at the information inputs 20 of the device must ensure the passage of four pulses from the generator 16 pulses.

The exit from the interrupt service routine is as follows. The last program instruction contains the code of the transition operation and the address of the first instruction of the program to be executed after the termination of the interrupt processing. After reading the last instruction of the processing program, the operation code from the upper bits of the output register 3 is fed to the decoder 2. In accordance with this operation code, a single signal appears at the output 21 of the decoder 2, which goes to the control inputs of the demultiplexer 1, multiplexer 11 and element OR 17. With this signal, the demultiplexer 1 and multiplexer 11 are switched and the control unit 13 is started up, which generates the previously described sequence of control signals. At the same time, the address part of the command, the transition from the output register 3 through the demultiplexer 1, the multiplexer 11, as well as through the element 10, is written into the previously zeroed address counter 9, and then through the element 6 it outputs a read control signal. The device proceeds to the execution of the necessary program.

Claims (1)

Claims An apparatus for programmed control comprising a program storage unit, the bit outputs of which are connected to the corresponding information inputs of the output register, the outputs of the higher bits of which are connected to the group of inputs of the decoder, the group of outputs of which are connected to the group of outputs of the device, as well as the input pulse counter, delay element whose input is connected to a control read the input of the program memory block, and the output with the counting input of the address counter, the output of which is connected to the address input of the program memory block, characterized in that, with the aim of expanding the application area when managing systems using a rigid time cyclogram, demultiplexers, multiplexer, encoder, first OR element, first AND element, prohibition element and control unit containing a four-bit shift register, whose information input is connected to the output of the second element AND, the first the input of which is connected to the output of the pulse generator, the second input to the first output of the control unit and the output of the second OR element, the outputs of which are connected to the group of information inputs of the control unit whose output group is connected to the group of information inputs of the four-bit shift register, the first input of the first element OR connected to the output of the input pulse counter, the output of the first element OR is connected to the read-through control of the input of the program memory block, and the second input to the first output of the group ppa infor0 five 0 five control outputs of the control unit, the second output of the group of information outputs to the input of zeroing the input pulse counter and the address counter, the third output to the first input of the first element AND whose output is connected to the information input of the address counter, and the second input controlling the output of the multiplexer the input of which is connected to the control unit and the corresponding information input of the input group, the output of the decoder and to the control input of the demultiplexer, the first information input of the multiplexer is connected to the first you the demultiplexer stroke, the second output of which is connected to the input of the initial setup of the input pulse counter, and the group of information inputs is connected to the outputs of the lower digits of the output register, the counting input of the input pulse counter is connected to the output of the prohibition element, the first input of which is connected to the first output of the control unit and the second input is connected to the input of the device for program control, the second information input of the multiplexer is connected to the output of the encoder, the input group of which is connected to the information group onnyh input device.