SU1014119A1 - Steeping motor control device - Google Patents

Description

This invention relates to electrical engineering; namely, the management of sh-. roBbfM engine. A device for controlling a stepper motor is known, comprising a multivibrator, a switch, a starting device connected to the elements: delays; the outputs of which are connected to the switch G1. The disadvantage of this device is that it does not provide the braking of the stepping motor from the maximum frequency reached in the acceleration mode. It is also known a device for controlling a stepper motor, containing a clock generator, a controlled key, a counter, divider, delay element and distributor. The device is designed to increase the speed of the stepper motor, which is provided by feeding the second pulse to the distributor with a frequency less than the frequency of the input pulses, with the subsequent signals of the second pulse of the series arriving at the distributor with a natural frequency. Moreover, in the device implementations,; holding the last impulse of aria 2 ,. However, in this device, it is not possible to accelerate the stepper motor to the maximum frequency without losing information (skip testing) The closest in technical essence to the proposed requirement is a device for controlling a stepper motor, containing a pulse distributor, a key, a reversible counter, a circuit and pulse generator, the output of which is connected to the key signal input. This device provides a smooth increase in the frequency of the stepper drive during acceleration and a decrease in the frequency when braking with speed. limited by the characteristics of the stepper motor and the load, and in the steady state - relay tracking 38 with the frequency of triggered pulses 3. However, to achieve the maximum frequency in minimum time by changing the frequency of the control pulses E transient modes (acceleration braking) realizes the optimal law control of the drive operation, while changing the frequency of the control pulse can be performed either smoothly or in jumps. A disadvantage of the known device is the impossibility of implementing the optimal law of controlling the mode of operation of the drive in transient conditions, for example, an abrupt frequency change with the development of a specified number of pulses at each increment (decrease) of frequency, which leads to a decrease in speed. The aim of the invention is to increase the speed of a stepper motor. The goal is achieved by introducing a program device, a frequency divider, And element, switch, counter, logic comparator, element into a device containing a pulse distributor, a key, a reversible counter, a comparison circuit and a pulse generator, the output of which is connected to the key signal input. a memory and a synchronizer divider, the first input of which is connected to the first output of the counter connected to the first input of the switch and to the control input of the key connected by the output to the second input of the divider-synchronizer pa connected by the first output to the first input of the memory element, the second output to the first input of the element I, the third output to the first input of the frequency divider connected by the second input to the fourth output of the synchronizer divider and the first input of the program device connected by the second input to the output switch 5 by the first output - with the first input of the comparison circuit, the second output with the third input of the frequency divider connected by its output to the input of the pulse distributor, the first: the input of the reversible counter and the first input the second input is connected to the first input of the logic comparator, the second input to the output of the reversible counter and the second input of the element I connected to the second input of the comparison circuit connected to the second input of the switch connected by the third input to the second input of the reversible counter the logic comparator and the second input of the memory element connected by the output to the third input of the element I. Such an embodiment of the device allows to realize any law of changing the frequency of operation of the steps about the motion of bodies in transient modes (smooth change and abrupt changes with the development of a specified number of control pulses at each frequency increase). Due to this, the device is able to work according to the optimal law of frequency change (for each specific drive) in transient modes, ensuring maximum speed. The drawing shows a functional diagram of the device for controlling a stepper motor in a single-line image. The device contains software device 1 with input 2 records, reversible counter 3 divider 4 frequencies, counter 5 with control input 6, key 7, divider-synchronizer 8, switch 9, generator 10 pulses, pulse distributor 11, logic comparator 12, memory element TI 1J, comparison circuit 1, element AND 15 (for each bit of a reversible counter), the device operates as follows,. The software device 1 on input 2 is written the program of transient modes (acceleration braking), optimal for a specific stepper drive, consisting of constants. (in binary code) increments of frequency and constants (in binary code) of the number of control pulses necessary for testing at each increment (decrease) of frequency. Software device 1 may consist, for example, of a memory device 16 of constants of the number of pulses, memory device 17 of frequency constants, multiplexers 18 and 19, and you; one register 20, the volume of memory devices 16 and 1.7 depends on the law implemented in the program. In the initial state of the circuit, the reversible counter 3. the frequency divider k and the counter 5 are in the zeroed state. The zero state of the counter 5 intended for. receiving and testing the setpoint (number of control pulses), through input 6 locks key 7 and zeroes the synchronizer divider 8, the initial state of switch 9 corresponds to a sample of 19 frequency constants and the number of pulses at the first address of the memory devices 17 and 16 of software device 1, Recording the setpoint in counter 5 (the counter state is different from zero) key 7 is opened and the constant frequency of the pulse generator 10 is fed to the input of a two-bit divider synchronizer 8, the second synchronizing pulse of which is writes the code corresponding to the first value of the frequency of operation of the Engine and contained at the first address of the storage device 17, the frequency divider C and the code corresponding to the number of working pulses at that frequency and containing the first address of the storage device 16 into the output register 20 the overflows from the synchronizer divider 8 are input to the frequency divider k. Overflow pulses from frequency divider k follow with a predetermined frequency f f fr de f (frequency of pickup of a stepper motor) and go to pulse distributor 11 to form diagrams of a stepping motor and further amplify power pulses. Simultaneously, the pulses from the output of the divider k are fed to the inputs of the reversible counter 3 and counter 5, Logic comparator 12 compares the codes of the reversible counter 3 and counter 5. The signal at the output of the logic comparator 12 appears when mi p (where m - corresponds to the counter code 5 a p - code rever: smart counter 3). Counter 5 works only on subtraction. If there is a setpoint in the counter 5 at the output of the logic comparator 12, the signal is absent, which corresponds to the operation of the reversible: adding 3 matcher. In the initial state, the memory element 13 is in the zero state and is transferred to the single state by the third synchronizer synchronizer 8, After testing a specified number of pulses at the frequency fj, the comparison circuit H is triggered according to the first sync pulse of the synchronizer divider 8, the signal from the output of the comparison circuit 14 switches the switch 9 to a sample of frequency codes and numbers pulses at the following address of memory devices 16 and 17. Codes of frequency and number of pulses corresponding to

5 10

fz and HI, are recorded in frequency divider i and 8, output register 20 of software device 1 by the second synchronizer pulse of synchronizer divider 8. Moreover, the value of the number of pulses is programmed in the form where n is the number of pulses specified for testing at the frequency f and A is the number of pulses set for testing on frequency f ,,. The pulses from the output of the divider k follow with a frequency. After a given number of pulses have been tested at this frequency, the process of frequency increment is repeated and the engine accelerates. When the condition is fulfilled, the signal from the output of the logic comparator 12 switches the memory element 13 to the zero state, the reversible counter 3 to the subtraction, the switch 9 to the reverse reading of addresses, the npvt switch with a certain delay selects the code of the number of pulses at the previous address. At the same time, the zero state of the memory element 13 blocks the operation of the element 15. At the sampling time, the first sync pulse of the synchronizer divider 8 excludes the possibility of sampling the next frequency value when the codes of the reversible counter 3 and the register 20 of the program device 1 coincide at the time the logic comparator 12 is triggered.

The second sync pulse rewrites the code of the number of pulses at the previous address to the output register 20. of software device 1, and the third sync pulse switches memory element 13 to one state, allowing operation of the And 15 element.

Thus, the pulses from the output of the frequency separator have the frequency at which the logic comparator is triggered.

Switching to frequency and the corresponding number of pulses119

testing will occur when comparing the codes of the number of pulses of the reversible counter 3 operating on the subtraction, and the output register 20 5 of the software device 1. This triggers the comparison circuit and fetches the frequency codes and the number of pulses from the memory devices 17 and 16 c. initial address, which is provided by reversing the operation of the switch 9. Information is being worked out (the number of pulses at the corresponding frequency) and the stepping drive is braked until the moment of the rate recorded in the counter 5. At the same time, the counter 5 is zeroed, the key J is closed and the device returns to its original state.

The width of the counter 5 is selected based on the maximum angular range of the engine, the width of the reversing counter 3 is half the size of the counter 5.

The frequency of the pulse generator 10 and the width of the frequency divider k are determined by the specified range of acceleration - deceleration frequencies and the minimum discreteness of the frequency and frequency variation. The minimum number of testing pulses during acceleration and deceleration at each frequency value is one pulse.

At the last addresses, I remember “their devices 17 and 16 of software device 1 should record the frequency code corresponding to the minimum frequency of the drive, and the zero code of the number of pulses to be tested. This ensures testing at the maximum setpoint frequency recorded in counter 5 and exceeding (in the number of pulses) the total number of pulses for acceleration and deceleration.

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Claims (1)

DEVICE FOR MANAGEMENT A STEP ENGINE containing a pulse distributor, a key, a reversing counter, a comparison circuit, and a pulse generator, the output of which is connected to the signal input of the key, which is important in order to increase the engine speed ; introduced a software device, a frequency divider, an AND element, a switch, a counter, a logic comparator, memory elements and a divider-synchronizer, the first input of which is connected to the first output of the counter connected to the first input of the switch and to the control input of the key connected by the output to the second input a divider-synchronizer connected by the first output to the first input of the memory element, the second output to the first input of the And element, and the third output to the first input of the frequency divider οαβ? separated by the second input with the fourth output synchronizer and the first input of the software device connected by the second input to the output of the switch, the first output - with the first input of the comparison circuit, and the second output - with the third input of the frequency divider, connected by its output to the input of the pulse distributor, the first input of the g counter and the first input of the counter connected by the second output to the first input of the logical comparator, the second input - with the output of the reverse counter and the second input of the element And connected to the second input of the comparison circuit, Connections output to a second input switch connected to the third input of the second input of down counter, the output of logical comparator and a second input of the storage element output is connected to the third input element I. SU .. „1014119 1 101