SU1372589A1 - Apparatus for controlling m-phase stepping motor with step splitting - Google Patents

Abstract

The invention relates to electrical engineering. The purpose of the invention is to simplify the device for controlling a tn-phase stepping motor by reducing the capacity of the permanent storage devices. The control unit contains m one-bit permanent storage devices (ROM) 1.1-1.t, to the outputs of which 2.1-2.t power amplifiers are connected, switching the windings of 3.1-3.t engine. Reversible 4 and non-reversible 5 counters are connected to the 1.1-1. ROM ROM inputs. The latter is connected to a decoder 6 and a divider 7 with a variable division factor. In order to reduce the required capacity of the ROM 1.1-1.t, the current information through the windings 3.1-З.т motor is written to the 1.1-lm ROM in binary code, and when reading the information, each memory cell is connected to the output of the ROM 1.1-1.t. a time proportional to the weight of the bit in the binary code that this cell represents. 2 Il. f (L

Description

3.7

J./TJ

with vj ND SL

CX)

The invention relates to the control of electrical machines and can be used in a precision stepper motor.

The purpose of the invention is to simplify by reducing the capacity of the permanent storage devices.

FIG. 1 shows a functional diagram of the device; in fig. 2 - timing diagrams explaining the operation of the circuit.

The device contains (Fig. 1) single-bit permanent storage devices (ROM) 1.1-1.t by the number of channels of the power amplifier, key amplifiers 2.1-2.P power connected to the phases 3.1-3.m of the engine, reversible binary counter 4, non-reversible binary counter 5, frequency divider 6 with a variable division factor, the output of which is connected to the clock input of the irreversible counter 5, decipheror 7, the outputs of which are connected to the frequency divider ratio setting 6 inputs, and inputs with the outputs of the non-reversible counter 5. Output the divider 6 with a variable division factor is connected to its setup input to the initial state, and the clock input is connected to the high-frequency clock pulse (T) bus. The clock input of the reversible counter 4 is connected to the low-frequency clock pulse bus (T (). The input of the direction of recalculation of the reverse binary counter 4 is connected to the reverse bus (set of rotation direction) of the Reverse engine, and its zero reset input is connected to the bus of the initial zero state setting) ABOUT.

The device works as follows.

In the initial state, a device setup signal is given to the buses. In this case, counters 4 and 5 (Fig. 1) are set to the zero initial state and the first rows of their matrices are selected through the internal row decoders of storage devices 1.1-1. In accordance with the required direction of rotation of the engine, a single or zero level is applied to the reverse potentials.

From the bus T. receive high-frequency pulses at the clock input delhi

five

0

five

0

five

0

five

6 frequencies, and from the last output to the input of a non-reversible counter 5. Since the outputs of the bits of the non-reversing counter 5 are connected to the ROM inputs, the first memory cells of the first rows of the matrices will be connected to the ROM outputs. Since the outputs of the decoder 7 are also connected to the outputs of the bits, all its inputs will have zeros and, therefore, the unit will turn on its first output, which in turn will be applied to the first input of the division factor setting. In this case, the division factor of divider 6 is equal to one, and the first clock pulse from the Tg bus will result in the unit appearing at the output of frequency divider 6, but since the output of frequency divider 6 is connected to its initial setting input, the last one condition. A short pulse at the output of the frequency divider 6, applied to the input of the non-reversible counter 5, will cause a change in its state, and at the output of its lowest bit is one unit. To the outputs of the ROM. 1.1-1.m, the second cells of the first rows of matrices are connected, and the decoder 7 has a unit on its second output, which is applied to the second input of the frequency divider 6 setting. In this case, its division factor is two. Consequently, the pulse at the output of the divider 6 in the Vits only after the arrival of the second clock pulse, counting from the moment of its last setting to the initial state. After the appearance of the second pulse at the input of the non-reversible counter 5, the third memory slots of the first rows of the matrices are connected to the 1.1-1. ROM outputs, and the decoder 7 has the unit at its third input, this means that the division factor of the frequency divider 6 is four. Consequently, the next pulse at the output of the divider 6 is in accordance with the Vits after the arrival of the fourth clock pulse, counting from the moment of its last setting to the initial state.

Thus, the first cells of the memory lines of the matrices of the ROM are connected to their outputs during one clock interval, the second cells - within two clock intervals, the third cells - within four clock cycles.

intervals, k-cells - for 2 clock intervals. After the non-reversible counter 5 reaches its maximum value and then is reset to its original state, the process will be repeated. If the row of the matrix with the length of 1 memory cell contains the number A, then the average current is 1 (.р flowing through the winding of the stepping motor is equal to

one..

R R,. 2

05 AL

where E is the voltage of the power source; R - winding resistance

govogo engine. Since A may vary from

l

O to 2, then the current through the winding can

change from o to

Kn r

, Trail

As such, having 1 cells in a row, we can record two different values of current through the winding or realize a split ratio of 2. After the low-frequency clock pulse arrives on the bus T "to the clock input of the reversing counter 4, the output of its lower bit is one unit, and the outputs of the ROM 1.1-1. T connect the second rows of matrices in which the new values are written currents through the windings 3.1-Z.t stepper motor.

In the 1.1-1.t ROM, any laws of change of currents in the windings of a stepper motor can be written. One of the possible options is shown in FIG. 2, where, for simplicity, the fragmentation factor is four for a four-phase stepper motor with phases F1, F2, FZ, F4.

The advantage of the proposed device is a considerably smaller compared with the known memory size of the ROM. This is due to the fact that the current information through the motor winding is recorded in binary code, and when reading information, each memory cell is connected to the output of the ROM for a time proportional to the weight of the bit in the binary code that the given cell represents. The required capacity of the ROM for the proposed device is determined by the formula

f (s,. G1 +) E 2 1

Q

five

0

0

five

five

where n is the realizable fragmentation factor;

m is the number of phases of the engine;

E - required ROM capacity. Substituting the values of m 4 and p 256, we get

E. 2 8192 bits,.

which is 32 times less than for a known device. Introduced a decoder and a frequency divider with a variable division factor are produced in the form of ready-to-use chips.

Reducing the capacity of the ROM will reduce the cost of the device and increase its reliability, while significantly reducing the time required to write information to the ROM, reducing the scrap rate, since the likelihood of write errors increases in proportion to the recorded information.

Taking into account that the known ROMs have a limited amount of memory, the use of the proposed device will allow increasing the maximum achievable crushing ratio of the engine pitch. Thus, for example, in the well-known 8192-bit ROM, the maximum crushing factor for a four-phase motor is achieved, only 32, and for the proposed one, 256, therefore, positioning accuracy will increase by eight times.

Claims (1)

Invention Formula A device for controlling a t-phase stepper motor with a split pitch containing m power amplifiers connected to the motor windings by outputs, an installation bus in the zero state, m single-bit permanent memory devices whose outputs are connected to the inputs of power amplifiers, reversible and non-reversible the counters connected by the outputs to the corresponding inputs of the permanent storage devices, the clock input of the reversible counter is connected to the low-frequency clock pulse bus, and the task input is directed recalculation - to the bus Reverse, characterized in that, in order to simplify by reducing the capacity of the permanent storage devices, a frequency divider with a variable division factor and a decoder, whose inputs are connected to the outputs of the non-reversible counter, are entered into it, the outputs - to the inputs of the division factor division frequency clock input TB TH p p p p p p p p p p p p p p p p p FIG. 2 the latter is connected to the high-frequency clock bus, the output is connected to its initial setup input and to the clock input of the non-reversible counter, and the zero setting inputs are connected to each other and connected to the zero setting bus.