SU1577066A1 - Reversible pulse distributor for controlling step motor - Google Patents

Abstract

This invention relates to electrical engineering and can be used in a discrete multimode electric drive. The purpose of the invention is to increase reliability by eliminating failures with erroneous combinations of input signals. The distributor contains a clock bus 6, control buses 7, reverse 8, stepper motor switches on 13, two tires 9, 10 for selecting the correctness and two buses 11, 12 for switching mode selection, a binary counter, read only memory 4, two AND-2 elements 3, two inverters 14, 15, element AND 16 and element OR 5. Improving reliability is achieved by providing, with the help of the entered inverters and element AND, a one-to-one correspondence between potential signals on the switching mode selection buses and information supplied to the binary inputs. wow counter. 1 il.

Description

01101 1 1 00X01 1 1 01001 1 1

1 110101 10X0101 1 100101

1011 101

one

100X1011 10101011

Four Phase BD:

0-7 eight-stroke switching 1-12-2-23-3-34-4-41

1-7 Four stroke switching 12-23-34-41

0-6 Four stroke 1-2-3-4

Three Phase BD:

8-13 Six-stroke switching

1-12-2-23-3-31

9-13 Three stroke switching

12-23-31

8-12 Three stroke switching

1-2-3

Circuit phase BD:

16-27 Twelve-cycle switching 12-123-23-234-34-345-45-456-56-561-61-612

17-27 Six-stroke switching

123-234-345-456-561-612

16-26 Six-stroke switching 12-23-34-45-56-61

Note: X is any state.

Both the counting module of binary counter 1 and the address field of ROM 4 (with the exception of the first digit of the address code) are set accordingly. type SD with only two potential signals on buses 11 and 12 of the choice of switching mode. Switching tact is determined additionally by the levels of potential signals on buses 9 and 10.

When the potential signal level on the reverse bus 8 changes, the address codes change in the reverse order, ensuring that the information recorded in the ROM is read in reverse order and thus the reversal is completed and the stepper is rotated.

engine in the opposite direction.

When a potential signal of the prohibition of counting is applied to the control bus 7, binary counter 1 is stopped and information is saved, thereby providing a fixed position for the stepping motor. If in the given on bus 13 of turning on of the stepping motor it is necessary to file for-; If the output signal is high, then, at all outputs of ROM 4, regardless of the state of the address inputs, signals of the same (high) level are obtained, ensuring the de-energization of the stepper motor windings while preserving information on the status of the distributor. This mode is effective if you need long stops of the stepper motor in the process of working without losing information.

Thus, the proposed reversing pulse distributor for controlling a stepper motor in comparison with the known one possesses higher reliability, providing a one-to-one correspondence between potential signals on switching mode selection buses and information supplied to the information inputs of a binary counter, thereby eliminating incorrect combinations of input signals could cause bad situations in the well-known.

Invention Formula

Reversing pulse distributor for controlling a stepper motor, contains a clock bus, control and phase buses, the first and second switching mode selection buses, the stepper motor start bus, a binary counter, read only memory, an OR element, and the first and second AND NOT elements the first inputs of which are connected respectively to the first and second buses of the selection of the switching tact, the second input of the first element is NOT connected to the output of the first bit of the binary counter, the clock input, the inputs of the resolution of the account and the counting directions of which are connected respectively to the clock bus, the control bars and the reverse, the output of the first NAND element is connected to the second input of the second NAND element, the output of which is connected to the first address input of the permanent storage device, the second and third address inputs of which are connected respectively, to the outputs of the second and third bit D ° in a binary counter, the output of which is of the bit bit is connected to the first input of the OR element, the second input of which is connected to the first bus-; no switch mode selection, output

connected to the fourth address input of the permanent storage device, the fifth address input of which is connected to the second switching mode selection bus, allowing the input

connected to a stepper motor start-up bus, characterized in that, in order to increase reliability by eliminating failures in case of erroneous combinations of input signals,

the first and second inverters and the element I are entered, the output of which is connected to the fourth information input of the binary counter, the first input is connected to the second selection bus

switching mode and combined with the input of the second inverter, the output of which is connected to the third information input of the binary counter, the second information input of which is combined with the second input of the element And through the first inverter connected to the first bus of the switching mode selection, and the first information input connected to the high potential bus .

Claims (1)

Claim The reversible pulse distributor for controlling a stepper motor, contains a clock bus, control and reverse buses, first and second switching mode selection buses, a stepper motor enable bus, a binary counter, read-only memory, an OR element, the first and second AND-NOT elements, the first inputs which are connected respectively to the first and second buses for selecting the switching clock, the second input of the first element is NOT connected to the output of the first bit of the binary counter, the clock input, the inputs of the resolution of the account and job directions of the Account, which are connected respectively to the clock bus, control and reverse buses, the output of the first AND-NOT element is connected to the second input of the second AND-NOT element, the output of which is connected to the first address input of the permanent storage device, the second and third address inputs of which connected respectively to the outputs of the second and third bits of 10 bits of the binary counter, the output of the fourth bit of which is connected to the first input element ^ OR, the second input of which is connected to the first circuit ^ not select the switching mode, output 35 mated to the fourth address input of the read-only memory, the fifth address input of which is connected to the second switching mode selection bus, the enable input 20 is connected to the turn-on bus of the stepper motor, characterized in that, in order to increase reliability by eliminating failures with erroneous combinations of input signals, 25 introduced the first and second inverters and the And element, the output of which is connected to the fourth information input of the binary counter, the first input is connected to the second selection bus 30 of the switching mode and combined with the input of the second inverter, the output of which is connected to the third information input of the binary counter, the second information input of which is connected to the second input of the And element and through the first inverter is connected to the first switching mode selection bus, and the first information input is connected to the high potential bus 40 l.