RU1784946C - Step-motor programmed control device - Google Patents

Abstract

The invention relates to automation and can be used for multi-mode control of a stepper electric drive based on three- and four-phase motors. In order to increase the reliability of a device for programmatically controlling a stepper motor by eliminating interference signals at the device outputs and redundant states when controlling a three-phase stepper motor, the first 7 and second 8 NAND elements and the second HE 6 element with a new set of couplings are additionally introduced into it. which made it possible to eliminate address redundancy and thereby eliminate interference signals at the outputs of multiplexers 11, 13, and 14, while simultaneously eliminating the reasons for the prototype's faulty or emergency screens ations, since at the address inputs of multiplexers 11, any state reversible binary counter 15c account module 8, 13 and 14, when controlling a three-phase stepping motor is supplied only regular codewords while ensuring correct translation to 6. Table 1 ,, 1-yl.

Description

The invention relates to automation and can be used for multi-mode control of a stepper electric drive based on three- and four-phase motors.

A device is known for programmatically controlling a three-phase stepper motor, comprising a reversible binary counter with a clock input and a reverse input, an OR element, first and second elements NOT, AND elements NOT. I. EXCLUSIVE AND / GY, single vibrators, the first and third multiplexers, the outputs of which are the outputs of the device, the lower address inputs are connected to the output of the And element, the higher address inputs are connected to the third bit output of the reversible binary counter, the parallel recording enable input of which is connected with single vibrator output

The disadvantage of this device is limited operational capabilities and increased complexity. The device does not provide typical switching modes of a four-phase stepper motor with a rather complicated organization of correct conversion to 6 using a large number of elements, including a single vibrator, the output pulse of which must be rigid in its temporal parameters with clock pulses.

Closest to the achieved result and technical nature of the proposed device is a device for programmatically controlling a stepper motor, comprising a motor selection bus, a reversible binary counter with a clock input and a reverse input, an OR element, an AND element, the first element NOT, executed on three buses selection of the switching mode with a switch for supplying the corresponding potential signals; the unit for setting the switching modes, the first, second, third and fourth multiplexers, the outputs of which are the output devices, the first information input of the first multiplexer is connected to the first output of the commutation mode setting unit and combined with the second and fourth information inputs of the second and fourth multiplexers, the second information input of the first multiplexer is connected to a common bus and combined with the third fourth and first information inputs, respectively second, third and fourth multiplexers, the third information input of the first multiplexer is combined with the fourth, first and second infor the inputs of the second, third and fourth multiplexers, respectively, and is connected to the output of the OR element, the first input of which is connected to the bus for selecting the switching clock, the second input is connected to the output of the first bit of the reversible binary counter, the second parallel recording input of which is connected to the common bus , the reverse input is combined with the input of the first element NOT, the output of which is connected to the third input of the parallel recording of the reversible binary counter, the output of the second bit of which is connected to the first input And, the output of the third category is connected to the senior address inputs of the first, second, third and fourth multiplexers, the lower address inputs of which are combined, the fourth information input of the first multiplexer is connected to the first, second and third information inputs of the second, third and fourth multiplexers and connected to the second output of the commutation mode setting unit, the third output of which is connected to the third information input of the third multiplexer.

A disadvantage of the known device is the low reliability when controlling a three-phase stepper motor and the operation of the reversible binary counter in the 6-count mode. Writing a zero code or a code of the number 5 to the counter is performed according to the notch received at the parallel recording enable input when the outputs The second and third bits of the counter show high-level signals, which corresponds to the code of the number 6 or 7, i.e. excess state. When providing switching modes for the windings of a three-phase stepper motor, these signals are abnormal and. entering the address inputs of the multiplexers, cause the appearance of interference signals in the form of slots and slots at the outputs of the device. When, for example, low-level signals are applied to buses 10 and 11. Which corresponds to the selection of one of the symmetrical switching modes, overwriting the data in the counter is accompanied by the appearance of low-level signals at all outputs of the device, i.e., a short-term emergency reset of the output, which may cause a malfunction.

The aim of the invention is to increase reliability by eliminating interfering signals at the outputs of the device and redundant states when controlling a three-phase stepper motor.

The goal is achieved in that in the device for programmed control of a stepper motor containing an OR element, an AND element, a first element NOT. the unit for setting the switching modes, the first, second, third and fourth multiplexers, the outputs of which are the outputs of the device, the first information input of the first multiplexer is connected to the first output of the unit for setting the switching modes and combined with the second and fourth information inputs of the second and fourth multiplexers, the second information input of the first multiplexer is connected to a common bus and combined with the third, fourth and first information inputs of the second, third and fourth of multiplexers, the third information input of the first multiplexer is combined with the fourth, first and second information inputs of the second third and fourth multiplexers, respectively, and is connected to the output of the OR element, the first input of which is connected to the switching clock select bus, the second input is connected to the output of the first bit reverse binary counter, the second parallel input of which is connected to the common bus, the input of the reverse device and the reverse binary counter are combined with the input of the first element E, the output of which is connected to the third input of the parallel recording of the reversible binary counter, the output of the second category of which is connected to the first input of the element And, the output of the third category is connected to the senior address inputs of the first, second, third and fourth multiplexers, the lower address inputs of which combined, the fourth information input of the first multiplexer is connected to the first, second and third information inputs of the second, third and fourth multiplexers, respectively, and the unit is connected to the second output and the commutation modes, the third output of which is connected to the third information input, of the third multiplexer, additionally introduced the first and second NAND elements and the second NAND element, the input of which is combined with the clock input of the reversible binary counter, the output is connected to the first input of the first And NOT, the second input of which is combined with the first input of the second AND-NOT element and is connected to the motor selection bus, the third input is connected to the output of the first bit of the reversible binary counter, the fourth input is combined with the high m address input of the first multiplexer,

the lowest address input of which is connected to the output of the AND element, the second input of which is connected to the output of the second AND-NOT element, the second input of which is connected to the output of the third bit of the reversible binary counter, the first parallel recording input of which is connected to the common bus, and the enable input parallel recording connected to the output of the first element AND NOT.

Comparative analysis with the prototype shows that the claimed device is distinguished by the presence of new elements: the first and second AND elements, the second element NOT, as well as a new set of connections between these elements and the other elements of the device, including new links to the reverse of the binary counter.

With the introduction of the first and second NAND elements and the second NAND element with the specified new set of connections with the rest of the element of the mr-g device, the above mentioned new properties ensure higher reliability by their interaction. When implementing the switching modes of the windings of a three-phase stepper motor, the device eliminates the inherent address redundancy inherent in the well-known solution, which not only eliminated notches and slots at the device outputs, but also prevented the occurrence of malfunctioning situations, the current, as in any possible state of reversing two, which reads 1 (; MODULE of account 8 to the address inputs of the multiplexers, including the control of a three-phase stepper motor under ayubs t bp kb standard code combinations.

The drawing shows a functional diagram of a device for programmatically controlling a two-wire switch.

The device contains a bus 1 clock pulses SHING 2, 3 and 4, respectively, reverse, select the clock cycle of the switching and motor, the first 5 and second used elements NOT, the first 7 and second 8 elements AND NOT, element AND 9. block 10 of the setting switching modes, the first 11 , second 12, third 13 and fourth 14 multiplexers, a reversible binary counter 15 and an OR element 16, the first input of which is connected to the switching clock selection bus 3, the second input is connected to the output of the first bit of the reversible binary counter 15, the output of the second bit of which is connected with first entry ohm of the element IE, the first and second inputs of the parallel recording are connected to the common bus, the third input of the parall recording is connected to the output of the first element NOT 5, the input of which is connected to the reverse needle 2 and

combined with the reverse input (± 1) of the reversible binary counter 15. the clock input of which is connected to the bus 1 of the clock pulses and is combined with the input of the second element HE 6, the parallel recording enable input with the output of the first AND-NOT 7 element, the first input of which is connected to the output the second element is NOT used, the second input is combined with the first input of the second AND-NOT element 8 and connected to the motor selection bus 4, the third input is combined with the second input of the OR element 16, the fourth input is connected to the output of the third bit of the reversible binary counter 15 and is combined with the second input of the second AND-NOT 8 element, the output of which is connected to the second input of the And 9 element. The output of which is connected to the lower address inputs (L) of the first 11, second 12, third 13 and fourth 14 multiplexers, the outputs of which are are the outputs of the device, the senior address inputs (B) are connected to the output of the third bit of the reversible binary counter 15, the first information input of the first multiplexer 11 is connected to the first output of the commutation mode setting unit 10 and combined with the second and fourth information input by the second 12 and fourth 14 multiplexers, respectively, the second information input of the first multiplexer 11 is connected to a common bus and combined with the third, fourth and first information inputs of the second 12 of the third 13 and fourth 14 multiplexers, respectively, the third information input of the first multiplexer 11 is combined with the fourth, the first and second information inputs, respectively, of the second 12. third 13 and fourth 14 multiplexers and is connected to the output of the OR element 16, the fourth information input of the first multipl Ksor 11 associated with the first, second and third data inputs, respectively the second 12, third 13 and fourth multiplexers 14 and connected to the second output of the switching unit 10 specifying the mode, the third output is connected with the third informational input of the third multiplexer 13.

A device for programmatically controlling a stepper motor operates as follows.

In order to implement the required switching mode of the phase windings of the selected stepper motor, in the block 10 for setting the switching mode, when preparing the device for operation, the necessary code is dialed (for example, via switches) in accordance with the following

a table. Switching cycle, i.e. the selection of a symmetric or asymmetric switching mode is determined by the signal level on the clock select bus 3. On the

the motor selection bus 4 is supplied with a potential signal of a low level when using a four-phase stepper motor or high-level if necessary to provide switching modes for a three-phase stepper motor The direction of movement and, accordingly, the counting mode of the binary counter 15 (summing or subtracting) is determined by the level of the potential signal

5 on the bus 2 reverse. When a high level signal is sent to bus 2, the reversible binary counter 15 operates in the direct counting mode, summing up the negative impulses arriving at its clock input

0 from bus 1 of clock pulses and generate a binary code on its bit outputs increasing by one at the end of each clock pulse. The signal from the output of the first bit of the reversible binary counter 15 is fed to the second input of the OR element 16 and either participates in the process of push-pull switching of signal levels at the corresponding information inputs of multiplexers 11-17 (at low

0 signal level on bus 3 and asymmetric six-cycle or eight-cycle switching mode) or is excluded from this process when a high-level signal is applied to the first input of OR element 16

5 from bus 3 and thereby maintaining a constant unit potential at the output of element 16 under symmetrical three- and four-stroke switching modes.

The signals from the output of the first bit of the binary binary counter 15 simultaneously arrive at the third input of the first AND-NOT 7 element. At the second input of this element when implementing switching modes for a three-phase stepper motor

5, a high level signal is maintained even after applying the fifth clock pulse in the forward count, i.e. after as a high-level signal in terms of power and at the output of the third bit of the reversible binary

0 counter 15, at the second, third and fourth inputs of the first AND-NOT 7 element, there will be high-level enable signals providing the passage of the sixth clock pulse through this element5 to the enable input of the parallel recording of the reverse binary counter 15 Thus, the sixth clock pulse has a reversible binary counter 15 when the direct count and control of a three-phase stepper motor is reset, does not respond when

At the same time, the same pulse has its own input, which is blocked by a low-level signal at the counter recording enable input. The account lock is released only after the restoration of a high level signal at the recording permission input, i.e. with some time delay due to the passage of the clock pulse through the second element NOT 6 and the first element AND-NOT 7.

Address Code arriving at the junior (A) and senior (B) address inputs of the multiplexers 11-14 and providing alternately sampling the information inputs of the multiplexers (i.e., certain code combinations in accordance with the table below), is formed from the signals taken from the output of the And element 9 (the least significant bit of the address) and the output of the third bit of the reversible binary counter 15 (the most significant bit of the address), and the signal from the output of the second bit of the reversible binary counter 15 is fed to the first input of element And 9, while the second input is ent And 9 in the recalculation mode to 6. i.e. when controlling a three-phase stepper motor, the signal from the output of the third bit of the counter 15 is inverted with the help of the second element AND-NOT 8, ensuring the maintenance of the zero potential at the output of the element And 9 with a high level signal at the output of the third bit of the counter 15 and thereby correct generation of the address code when controlling a three-phase stepper motor under conditions of complete absence of cuts and slits in the address inputs of multiplexers 11-14 (the information at the output of the second multiplexer 12 does not use when controlling a three-phase stepper motor).

When changing the direction of the worked out movement by applying a low-level signal to the reverse bus 2, the counter 15 starts working in the reverse counting mode, decreasing its contents by one at the end of each clock pulse. After reaching the zero state, the counter 15 will go to state 7 at the next clock pulse, in which high level signals are removed from all its bit outputs, which, when controlling a three-phase motor, correspond to an address code with a unit in the high order. At the second, third and fourth inputs of the first AND-NOT 7 element there are high-level enable signals and the next clock pulse passes through this element to the enable input of the parallel recording of reverse

binary counter 15, blocking its clock input and causing the number 4 to be written into the counter, taking into account the signal inversion on the first NAND 5. element. The address code (10) does not change, corresponding to the one set when controlling a three-phase stepper motor. When the following clock pulses are applied, the address code is further correctly changed and thereby the information inputs of the multiplexers 11 are read in the reverse order, which ensures the rotation of the rotor of the stepper motor in the opposite direction.

To implement the switching modes of the windings of a four-phase stepper motor, a low-level signal is supplied to the bus 4, blocking the first 7 and second 8 AND-NOT elements. The high-level signal from the output of the first AND-NOT 7 element blocks the recording of information in the binary counter 15 operating under the given conditions in the counting mode 8. The high-level signal from the output of the second AND-NOT 8 element allows the signal to pass from the output of the second bit of the reverse binary counter 15 to the lower address inputs of the multiplexers 11-14, regardless of the state of the signal at the output of the third bit of the counter 15, which ensures the correct formation of the address code when controlling four-phase stepper motor. Information is then taken from all the outputs of the device, the reverse is processed in the same way as above.

Thus, the inventive device for programmed control of a stepper motor has, in comparison with the known technical solution, higher reliability due to the elimination of abnormal address code combinations when controlling a three-phase stepper motor, which not only led to the appearance of interference signals at the outputs of the device, but also in a number of cases, they could cause a malfunction or emergency.

Claims (1)

The claims A device for programmatically controlling a stepper motor comprising an OR element. element And, the first element is NOT, the unit for setting the switching modes, the first, second, third and fourth multiplexers, the outputs of which are the outputs of the device, the first information input of the first multiplexer is connected to the first output of the unit for setting the switching modes and combined with the second and fourth information inputs respectively of the second and fourth multiplexers, the second information input of the first multiplexer is connected to a common bus and combined with the third, fourth and first information inputs, respectively horn, third and fourth multiplexers, the third information input of the first multiplexer is combined with the fourth m, the first and second information inputs of the second, third and fourth multiplexers, respectively, and is connected to the output of the OR element, the first input of which is connected to the switching clock select bus, the second input associated with outputting a first bit of a reversible binary counter; the second parallel recording input of which is connected to the common bus, the reverse input of the device and the reverse binary counter are combined with the input of the first element NOT, the output of which is connected to the third parallel recording input of the reverse binary counter, the second bit of which is connected to the first input of the element I. the third output the bit is connected to the senior address inputs of the first, second, third and fourth multiplexers, the lower address inputs of which are combined, the fourth information of the first multiplexer connected to the first, second and third information inputs of the second, third and fourth multiplexers, respectively, and connected to the second output of the commutation mode setting unit, the third output of which is connected to the third information input of the third multiplexer, characterized in that that, in order to increase reliability by eliminating interference signals at the device outputs and redundant states when controlling a three-phase stepper motor, the first and second AND-NOT elements and the second NOT element are introduced into it, the input of which is combined with the clock input of the reversible binary counter, the output is connected to the first input of the first AND-NOT element, the second input of which is combined with the first input of the second AND-NOT element and connected to the engine selection bus, the third input is connected to the output of the first bit of the reversible binary counter, the fourth input is combined with the highest address input of the first multiplexer, the lowest address input of which is connected to the output of the AND element, the second input of which is connected to the output of the second AND-NOT element, the second input of which is connected to the output of the third bit of the reversible counter. the first parallel recording input of which is connected to the common bus, and the parallel recording enable input is connected to the output of the first AND-NOT element.