SU1541755A1 - Reversing distributor of pulses for control of m-phase stepping motor - Google Patents

Abstract

This invention relates to electrical engineering and can be used in a discrete electric drive. The purpose of the invention is to simplify the distributor. To do this, it includes a reversible counter with a preset and a decoder in the form of an idle storage device, the H inputs of which are connected to the discharge outputs of the reversing counter, the M outputs to the inputs of power amplifiers, (M + 1) to the output to the resolution input records of the reverse scentch, whose N information inputs are connected to the N outputs of the decoder, taken from the mentioned M outputs. When a write enable signal appears on these outputs, the necessary code appears at the time of recording. 1 il.

Description

The invention relates to the control of electric machines and can be used in a multi-mode discrete electric drive.

The purpose of the invention is to simplify the pulse distributor.

The drawing shows a functional diagram of a pulse distributor for controlling a reverse t-phase stepper motor.

The reversible pulse distributor contains a clock bus T, a directional bus H, connected through a block of logic elements 1 to the inputs of forward +0 and reverse (-1) counter 2, made with the possibility of pre-recording the number, outputs 01, C ,. . . , On binary reversible counter 2 is connected to the corresponding), 2 ,,. ,, ,, n inputs of the decoder 3, made in the form of a permanent storage device, to n + 1,., O, n + k inputs of the decoder 3 are connected to the operating mode selection bus Y1,. The m outputs of the decoder 3 are connected to the inputs of the power power amplifiers (not shown i, of which n outputs are connected to the information inputs of the binary reversing counter 2, and (n + 1) the output of the decoder 3 to the enable input of the write counter 2. The block of logical elements 1 contains two logical NANDS 4 and 5, to the first inputs of which the clock bus T is connected, and to the second inputs to the directional bus H, and to the logical &

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element 5 is via inverter 6, the output of logic element 4 is connected to the input of the forward (+1) account, and the output of the logic element to the input of the reverse (-1) account of the binary reversible counter 2.

The distributor works as follows.

Clock pulses are received on the bus Tc. When a signal is transmitted along the bus direction 1, the clock pulses through a logical edge 4 blocks of logic elements arrive at the input of the direct (+ 1) counter 2 counter, the last counts from 0 to 2m-Is the outputs of the counter 2 Ql-Qn connected to the address inputs of the decoder Ze cause changes in the state of the outputs according to the information recorded in the decoder 3, forming a temporary m-channel sequence of switching pulses of the control windings of the stepping motor according to the selected algorithm total, the selection of the memory section of the decoder 3 with the necessary switching algorithm is carried out on the bus selection mode Y1, .. ,, YK. When a 2m pulse arrives at the (m + 1) th output of the decoder 3, a logical O appears, and at this time, the n outputs of the decoder 3 connected to the information inputs of the counter are fed to the logical O. This code is written in the (2uch + 1) th memory element of the decoder 3.

Code O is recorded in counter 2, set to the initial state, and the cycle of operation is repeated. The recording time of the code from the information inputs is so short that it does not affect the j-channel switching sequence of the stepping motor and does not affect its operation. Similarly, the device operates when the signal O travels on the bus, the clock pulses arrive through the logic element 5 of the logic element block 1 to the input of the inverse (-1) counter of the counter 2. Counter 2 counts from 2 t -1 to O. on (t + 1) th

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the output of the decoder 3, a potential equal to O, arriving at the synchronizing input of counter 2, appears at the information inputs of counter 2, a code corresponding to the (2--1) -th state of the outputs of the distributor and it is written to counter 2. Thus, applying to the bus H a logical O on the first m outputs of the decoder 3, the reverse m-channel sequence of switching pulses of the control windings of the stepper motor is generated. .

The table shows the recording of information in a storage device for the 12-cycle switching of a six-phase motor.

 Using the same outputs of the decoder to control the engine and to write information to the counter reduces the storage capacity and the number of connections, which generally simplifies the pulse distributor,

Claims (1)

Invention Formula A reversing pulse distributor for controlling a g-phase stepper motor comprising a clock bus, operating mode selection buses and a directional bus, a block of logic elements, a decoder and a reversible counter with a preset, the outputs of n-bits of which are connected to the corresponding decoder inputs, m outputs of which connected to the inputs of the power amplifiers, the mode selection bus being connected to the remaining inputs of the decoder, and the inputs of the counting direction of the reversible counter are connected via the unit l Optical elements with a clock bus and a directional bus, characterized in that, with the simplification circuit, the decoder is provided with an additional (m + l) output connected to the write enable input of the reversible counter whose information inputs are connected to the n outputs of the decoder taken from the numbers mentioned t, the outputs of the decoder.