SU1675850A1 - Stepping motor programmable controller - Google Patents

Abstract

The invention relates to automation and computer technology and can be used in automatic control systems for stepping electric drives of optical scanning devices with increased requirements for reliability of operation. In order to expand the reliability of operation in a device containing a program setting block, a mode setting block, the invention relates to automation and computing technology and can be used in automatic control systems of a stepper electric drive of optical scanned devices with increased requirements for reliability of operation. The purpose of the invention is to increase reliability by controlling more failure situations. FIG. Figure 1 shows the functional diagram of the device for software modulation of the AND element, three OR elements, clock and strobe pulse formers, phase switch, three triggers, the OR element, the EXCLUSIVE OR element, a multiplexer, a logic unit and two reverse shift registers with a new set of connections . With asymmetrical switching modes, each clock pulse generated by a clock pulse causes a shift recorded when the code combination device is turned on in one of the registers corresponding to the next stepping motor after the shift, while the contents of the other register equal to the actual code combination during normal operation of the stepper electric drive at the outputs of the phase switch after the completion of transients, it is compared by the mode setting unit with the state of the electric drive. In case of deviation of the actual state from the given one, incl. when the power supply disappears, the phase windings are cut off or short-circuited, the device generates a failure signal used to interrupt the program. 2 hp f-ly, 3 ill. stepping motor; in fig. 2 is a diagram of the mode setting block; in fig. 3 shows an example of filling the phase switch. The device contains a program setting block 1, a mode setting block 2, the first 3 and second 4 elements AND, the first 5, the second 6, the third 7 and the fourth 8 OR elements, the sync pulse shaper 9, the strobe pulse shaper 10, the phase switch 11 their outputs with a stepper motor 12, the first 13, the second 14 and the third 15 triggers, the element EXCLUDING with Os VJ ate 00 ate about

Description

ALSE OR 16, first 17 and second 18 reverse shift registers, multiplexer 19 and logical switch 20.

Logic switch 20 includes a selector-multiplexer 21, elements OR 22i-22m according to the number of outputs of the switch 11 phases, and elements 2I 23h-23t according to the number of outputs of the switches 11 phases.

The mode setting unit 2 (Fig. 2) contains a code comparison element 24, an OR-NOT 25 element and an AND 26 element, the number of inputs of each of which is equal to the number of the switch outputs 11 phases, a ZILI-NE element 27 with gating.

Phase switch (Fig. 3) contains a reversible counter 28, the element OR-NOT 29, multiplexers 30-32, amplifiers 33-35.

The device works as follows.

When the device is turned on, a low-level signal is set at the installation output of the program setting unit 1, which is active for a certain (10 µs - 1 ms time interval) (initial setting signal) and causes the 11 phase switch to block at this time and de-energizes the windings of the stepper motor 12. Proceed further through the element OR 5, operating in inverse logic, at the first input of the strobe-pulse former 10, a low level signal causes the output of the strobe pulse 10 low-level signal which blocks the operation of block 2, thereby causing a high level signal at its output, which is a signal of no failure and permits the operation of block 1 of the program in normal mode. The strobe pulse shaper 10 can be performed, for example, on the basis of a trigger, the setup input to the zero state of which is connected to the output of the first element OR 5, the setup input to the single state is connected via a delay element to the output of the clock 9 of the sync pulse, and the inverse output connected to the gate input of unit 2.

When setting, for example, an asymmetrical switching mode with the inclusion of a different number of stepper motor windings in adjacent output clock, to set the switching mode of unit 1, a high level signal is set, and the initial setting signal in this case sets the third trigger 15 to single condition. The trigger 14 is set to the same state by the same signal, which in turn is conditioned by a low level signal from the inverse output

installation of the trigger 13 in a single state. At the same time, the low level signal from the inverse output of the trigger 14 is also fed to the input of the element OR 6, which provides

addition of low level signals. Thus, from the output of element 6, the inputs of the 7 and 7 and 8 elements operating in the inverse logic receive a low level signal, and regardless of the state of the trigger 15, the low level enable signal is maintained at the inputs of the And 3 and 4 elements.

At the end of the initial setup signal, a high signal appears at the setup output of the program 1 block

5, which sets the phase switch 11 to its initial state, determined by the levels of potential signals at the inputs of the switch 11 to set the switching mode and the number of active phases. When setting, for example, the minimum number of excited phases in the initial state in the case of an asymmetrical switching mode to the input of specifying the number of excited phases from

5 of the program setting unit 1, a low level signal is applied (with a high level signal at the input for setting the switching mode). When the switch is installed, the 11 phases are reset to the corresponding

At the outputs of the switch, high-level signals will appear that cause the recording of certain windings of the stepper motor 12.

By the signal difference from O to 1 to

5 the installation output of the program setting unit 1 and thus the output of the element OR 5 starts the driver 9 of the sync pulse generating a negative pulse that passes through

0 open elements And 3, 4 and is fed to the shift inputs of the reverse shift registers 17 and 18. At the write inputs (E) of these registers there is a low level signal taken from the inverse output

5 flip-flop 14 and which is a signal for enabling parallel recording of information into registers, performed at the end of the clock pulse, i.e. by its transition from O to 1. A reversing shift register 17 at the same time records a code combination present at the outputs of the switch 11 phases and corresponding to the minimum number of excited phases (for example, 100 ... 0) of a stepper motor. The code combination written to the reversible shift register 18 is removed when the address00 selector-multiplexer 21c address of the output of the element group OR 22i-22m is zero and, thanks to their circular inclusion (when operating in positive logic), is one logical unit larger than the code combination at the output of the switch 11 phases, corresponding to the inclusion of the windings of the stepping motor 12 in the next switching cycle, for example, 110 ... 0) when driving in the forward direction, given by the high level of the output signal at systematic way unit 1 specifying program.

Simultaneously with recording information into the reverse shift registers 17 and 18, the trigger 15 switches the sync pulse from O to 1 and switches to the zero state, providing a low level signal at the address input of the multiplexer 19 and passing the code combination written to the reverse shift register 17 through the multiplexer 19 on the information inputs b of block 2. By the difference of the sync pulse from 0 to 1 to the trigger 14, a low level signal is recorded from its information input,

At the inverse output of this trigger with a certain time delay, caused by the recording of information, a high level signal appears that translates the reverse shift registers 17 and 18 and the shift mode of the recorded information and releases the trigger 13, at the inverse output of which due to the delay the trigger 14 continues to maintain a low level signal. When setting, for example, a forward movement (high level of the signal at the output of the direction of block 1) from the output of the EXCLUSIVE OR 16 element to the input of the OR 6 element, a high level signal is applied. At the first input of this element there is also a high level signal and thus a high level signal is sent to the first inputs of the OR 7 and 8 elements, which at the zero state of the trigger 15 causes the low level resolution signal to remain at the input of the AND 3 element, while And 4 is blocked by a high level signal from the output of the element OR 8.

After the sync pulse is finished, the output of the strobe pulse generator 10 with a certain time delay required to complete the transient processes in the reverse shift registers 17 and 18 and multiplexer 19 appears a high level signal, the unlocking unit 2. The first information inputs of this block are fed the code combination from the outputs of the switch 11 phases, and the second information inputs bi receives information from the outputs of the multiplexer 19,

recorded in the reverse shift register 17. If both code combinations are equal, the output of the code comparison element 24 included in block 2 (Fig. 2) is a low level signal. During the initial powering of the stepper motor and the presence of at least one switched on and at least one de-energized windings from the outputs of the elements OR 25 and I 26, low level signals are also removed and thus with a regular turn on of the stepper electric drive, the signal is present at the output of the block 2 after removing the strobe high level, allowing further operation of block 1 of the program in the set mode.

When a negative clock pulse program is given to the clock output of block 1, this pulse passes through the first element OR 5 and is fed to the gateway shaper 10 input, at the output of which a low level signal appears, blocking block 2. At the end of the clock pulse i.e. on its transition from O to 1, a code combination is formed at the outputs of the phase switch 11, shifted by one step in the forward direction (110 ... 0) and causing the corresponding switching of the windings of the stepping motor 12. At the same time, the shaper starts the same transition of the clock pulse 9 of the sync pulse and the negative pulse from its output passes through the open element I 3 to the input of the shift of the reverse shift register 17, causing further information from the O and 1 shift of the information recorded in this register by one step per second. Direction and the appearance at its outputs of a code combination (010 ... 0) corresponding to the next (by the second clock pulse) switching on the windings of the stepping motor. At the same time, the sync pulse from O to 1 confirms the state of flip-flop 13 (in the absence of a reverse signal) and flip-flop 14, while flip-flop 15 switches the sync pulse to single state by opening the I 4 element, as well as providing passage to code combination from the outputs of the reverse shift register 18, in which the information (110 ... 0) is recorded, which coincides with the code combination at the outputs of the switch 11 phases during the regular step development,

After the end of the sync pulse and the removal with the corresponding strobe delay, the outputs of block 2 continue to maintain a high level signal confirming

after the completion of transients no failure or failure situation. When issuing a new clock pulse, the described cycle repeats with the only difference that the negative sync pulse from the output of the former 9 enters through the AND 4 element at the input of the shift of the register 18, causing its transition from O to 1 to shift the data recorded in this register and code combination (0110 ... 0) at its outputs, while the second inputs of block 2 receive a code combination (010 ... 0) from the outputs of register 17, corresponding to the information on the first inputs of block 2 during normal operation of an electric drive . The clock pulse from the output of the former 9 switches further the trigger 15 to the zero state, ensuring the passage of the next clock pulse through the element 3. Thus, each clock pulse in asymmetrical switching modes causes a shift of the code combination in one of the registers (i.e. the formation of the next specified code combination ) and comparing the content of the second of the registers, which is equal during the normal operation of the stepper electric drive to the actual state of the latter after the passage of the clock pulse and the completion of the transition processes.

When changing the direction of movement by issuing a low level signal to the output of the direction of block 1 of the program, as well as when setting the reverse movement when the device is initially turned on, the inputs of the EXCLUSIVE OR element are given the same (low) level and low level signals the output of this element, entering through the elements OR 6-8 to the inputs of elements AND 3 and 7, permits the passage of a sync pulse from the output of the former 9 through both the elements AND 3 and 4 to the shift inputs of both registers 17 and 18 and synchronous with Vig recorded in these resorts (data in the reverse direction, after which the comparison results in the contents of one of the registers, equal in the absence of failures in the operation of the code combination at the outputs of the switch 11 phases shifted by the clock pulse respectively (or the difference from O to 1 after signal initial setup) in the opposite direction.

If in the asymmetrical switching mode, the number of the excited phases of the stepper motor 12 in the initial state is set to the maximum (for example, 110 ,,. 0) by issuing a high level signal at the output to set the number

of the excited phases of block 1, this combination will be present at the outputs of the phase switch 11 and will be written into the reversible casing register 17 after the stepping electric drive is reset to its original state, while the code combination is written to the reversing shift register 18 (when the signal level is high, the address input of the selector-multiplexer 21) from the outputs of the group of elements And, and contains, thanks to the circular inclusion of these working in the positive logic elements, one logical unit less in comparison codeword output switch 11 phases corresponding inclusion stepper motor windings 12 in the next switching cycle (010 ... 0) when moving in the forward direction. After recording the information and installing the trigger 14 in the zero state, the device operates, including and when processing the reverse, as described.

In the case of choosing a symmetric switching mode by outputting a low level signal to the output to set the switching mode of block 1, the trigger 15 is fixed in the zero state and does not react further to the incoming clock pulses, causing the content of the reverse shift register 17 to be compared with the data on the first information inputs of the block 2, since the low level signal is constantly maintained at the address input of the multiplexer 19 in this case. At the shift input of the first register 17, each clock pulse arrives through the constantly open first element 3, while the phase switch 11 generates a sequence of code combinations corresponding to the symmetric mode (for example, 110 ... O, 0110) ... Oh, etc.).

Providing a comparison of the actual state of a stepper electric drive with a given mode of operation for such basic parameters as the number of phase windings included in each, their shift by each cycle, the change in the number of phase windings during asymmetrical switching modes, as well as tracking changes in the direction of motion and, if necessary , correct shift, incl. taking into account transients, the device generates a failure signal in case of any deviation of the actual state from the specified operating mode after the transient processes have been completed and the strobe has been removed. Post-assignment exit

the block mode to the program setting block; the failure signal causes an interruption of the executed program and can be additionally used for alarm signaling, blocking of the controlled object, etc.

The failure signal is issued by the device even if the power supply disappears after turning on the stepper motor drive, the breakage of all phase windings or shorting of all windings on the power bus, including and in the event of an abnormal de-energizing of the windings during parking (not by issuing, a low level signal to the installation output of the program setting unit 1). In all these cases, at the output of an OR-NOT 25 element or an AND 26 element, depending on the type of failure situation, a high level signal appears, which, after removing the strobe, causes a low level signal at the output of the OR-NOT 27 element with gating (Fig. 2 ), i.e. signal failure, exceeding the execution of the current program.

Thus, the proposed device for programmed control of a stepper motor possesses, in comparison with the known, higher reliability, providing in the process of working out a given program step-by-step control of the switching sequence of the phase windings of a stepper motor, the number of windings activated each time and the number of windings included with asymmetrical switching modes. In case of any deviation from the specified mode of operation, incl. in the event of breaks or short circuits in the phase windings, the device promptly generates a failure signal, which can be used to interrupt the program, block the object, and give an alarm almost immediately after the occurrence of the faulty situation.

Claims (3)

Claim 1. Device for programmed control of a stepper motor, comprising a program setting block, a mode setting block, first and second elements AND, first, second and third elements OR, clock generator, gate generator and phase switch, group of information outputs of which are connected to the stepping motor, and the clock input of the counting direction and the setup input are connected to the corresponding outputs of the program setting block, the input of which is associated with the output of the mode setting block, characterized by m, in order to enhance reliability by providing a greater number of control failure situations, it introduced first, second and third flip-flops, a fourth OR gate, an exclusive OR. first and the second reversible shift registers, a multiplexer and a logic switch, the inputs for setting the number of excited phases and the switching mode of the phase switch are connected to the corresponding 0 outputs of the program setting block, the setup and clock outputs of which are connected to the first and second inputs of the first OR element, the output of which is connected to the first input of a 5 L strobe pulse and to the input of the clock generator, the output of which is connected to the first inputs of the first and second elements I. with clock inputs of triggers and with the second input of a gate-pulse generator connected to the gate of the mode setting unit, the first group of information inputs of which are connected to the outputs a phase switch and to a group of informational inputs of the first reverse shift register and a logic switch, the address input of which is combined with the input of the phase switch for setting the number of excited phases, and 0 outputs are connected to the group of information inputs of the second reverse shift register, the reverse input of which is combined with the direction input of the phase commutator, with the information input of the first trigger, with the first input of the EXCLUSIVE OR element and with the reverse input of the first reverse shift register, the discharge outputs of which are connected to the first group of information inputs 0 multiplexer, the second group of information inputs of which are connected to the bit outputs of the second reverse shift register, the outputs are connected to the second group of information inputs 5 of the mode setting unit, and the address input is connected to the forward output of the third trigger, the zero-setting input of which is connected to the input for setting the phase switching mode. installation input 0, the single state is connected to the installation input of the phase commutator and to the installation input to the single state of the second trigger, whose information input is connected to the common bus, and the output is connected to the first input of the second OR element and to the installation input to the single state of the first trigger, the output of which is connected to the second input of the EXCLUSIVE OR element connected by the output to the second input of the second an OR element whose output is connected to the first inputs of the third and fourth OR elements, the second inputs of which are connected respectively to the forward and inverse outputs of the third trigger, and the outputs are connected to the second inputs of the first and second elements AND whose outputs are connected to the shift inputs of the first one, respectively and the second reverse shift registers, recording inputs of which are connected to the output of the second trigger. 2. The device according to claim 1, characterized in that the logic switch comprises a selector-multiplexer, elements OR by the number of outputs of the phase switch and elements AND by the number of outputs of the phase switch, the first inputs of the first element OR and the first element AND are connected to the first inputs the second OR element and the AND element, as well as the corresponding input from the group of information inputs of the logic switch, the second inputs of the second OR element and the second AND element are connected to the second input from the group of information inputs of the logic switch, The second inputs of the second element OR and the second element AND are connected to the second input from the group of information inputs of the logic switch, to the first inputs of the third elements OR and AND, the second inputs of the last elements OR and AND are connected to the last input of the group of information inputs of the logical switch, with the second inputs of the first the elements OR and AND, the outputs of all the elements OR are connected to the first group of information inputs selector-multiplexer, the second group of information inputs of which is connected to the outputs of the elements And, the address input is connected to the corresponding input of the logic switch, the outputs of the selector-multiplexer connected to the group of information outputs of the logic switch. 3. Device pop. characterized in that the mode setting block contains a code comparison element, an OR-NOT element and an AND element, the number of inputs for each of which is different for the number of outputs of the phase commutator, a ZILI-NOT element with gating, the output of which is connected to the output of the mode setting block, the gating input which is connected to the corresponding input of the element ZILI-NOT with gating, the group of inputs is connected to the outputs of the elements OR-NOT, Both and the output of the code comparison element, the first group of inputs of which is combined with the corresponding inputs of the AND, OR-NOT elements and connected to the first group of information inputs, and the second the group of inputs is connected to the second group of information inputs of the mode setting block, $ /. / FIG. 2 / KUtf%