SU1640811A1 - Device for detecting failures of stepped electric drives - Google Patents

Abstract

The invention relates to electrical engineering, namely to control of electrical machines, and can be used in control systems of stepper motors with any number of phases and multi-mode switching in discrete automated electric drive systems with increased requirements for the reliability of its operation. The purpose of the invention is to enhance the operational capabilities by providing control of the states of a stepper motor during asymmetrical switching. The device contains a synchronization unit 7, a first ring reversible shift register 8, a code comparison unit 10, a one-shot 11, a trigger 13 and an OR element 16, a second ring reversing shift register 9, a second 14 and a third 15 triggers, two elements EXCLUSIVE OR 25, 26, six elements AND 19-24, the second 17 and third 18 OR elements and the multiplexer 27 “With asymmetrical switching modes of the stepper motor windings, each clock pulse causes a shift of the code combination recorded when the device is turned on in one of the registers 8, 9, ormiru thereby following a predetermined switching state of the actuator, while the contents of another register equal during normal C5 i

Description

.

The invention relates to electrical engineering, to the control of electric machines, and can be used in control systems of stepper motors with any number of phases and asymmetrical switching mode in discrete systems of automated electric drive with increased requirements to the reliability of its operation.

The purpose of the invention is to expand the operational capabilities by providing control of the state of a stepper motor during asymmetric switching.

Fig. 1 shows a functional diagram of an apparatus for detecting failures in a stepper motor drive; in fig. 2 shows the stress plots at the nodal points of the device circuit, with the index number of the element (including the busbars) shown in FIG. L for which the diagram is shown.

A device for detecting a failure in a stepper electric drive equipped with 1 clock pulse (Tact) tires, 2 engine turn on tires (On. NS), 3 reverse and 4 switching mode choices (Mode) connected to the switch inputs 5 phases, the outputs of which are connected to the corresponding the phases of the stepper motor 6, contains a synchronization unit 7, the first 8 and second 9 ring reverse shift registers, the code comparison unit 10, the first 11 and the second 12 single-vibrators, the first 13, the second 14 and the third 15 triggers, the first 16, the second 17 and third 18 elements OR, from the first the sixth elements And 19-24, the first 25 and second 26 elements EXCLUSIVE OR and the multiplexer 27, whose address input is connected to the forward output of the second trigger 14, the first (1) and second (2) inputs of the multiplexer 27 are connected to the outputs of the first 8 and second 9 ring reversing shear pe25

20 th 30 th,

35, 40 45 50 55 gistors, the reverse inputs of which are connected to the bus 3 reverse, the recording resolution inputs (E) are connected to the output of the first single-oscillator 11, the shift inputs (C) of the first 8 and the second 9 ring reverse shift registers are connected to the outputs of the second, respectively 17 and the third 18 OR elements, the first inputs of which are connected to the outputs of the first 19 AND second 20 And elements, the second inputs are combined and connected to the output of the third 21 And elements, the third inputs are connected to the outputs of the first 23 and sixth 24 And elements, the first inputs to toryh connected

the direct and inverse outputs of the second trigger 14, the second inputs are connected to the output of the fourth element And 22 and combined with the first input of the first element And 19, the second input of which is combined with the input of the second one-one vibrator 12 and connected to the output of the first single-oscillator 11, connected with its input with the bus 2 bus connected to the installation input to the unit state of the second trigger 14, the setpoint input to the zero state of which is connected to the switching mode selection bus 4, and the counting input connected to the first output of the synchronization unit 7 and combined with the clock input of the third trigger 15, the information input of which is combined with the first inputs of the first 25 and second 26 elements EXCLUSIVE OR, the first input of the second element AND 20, connected with its second input with the output of this one-shot 12, and connected to the bus 3 reverse , inverse and direct outputs of the third trigger 15 are connected to the second inputs of the first 25 and second 26, respectively, EXCLUSIVE OR elements, the outputs of which are connected to the first inputs of the third 21 and fourth 22 And elements, the second inputs of which are connected to the first m output synchronization unit 7, the first and second inputs of which are combined with sootvetst516

the input elements of the first element OR - 16 and are connected to the bus 1 of clock pulses and the engine starting plug 2, the output of the first element OR 16 is connected to the input of setting the first trigger 13 to zero, the input of which is connected to the second output of unit 7 synchronization, and the output of the first trigger 13 is connected to the gating input of the code comparison unit 10, the output of which is the device output, the first comparison inputs (A) are connected to the corresponding outputs of the switch 5 phases and are connected to the bit inputs the recordings of the first ring reversing shift register 8, the first bit input of the second ring reversing shift register 9 is connected to the high potential bus (the connection in FIG. 1 is not specified), and the second and subsequent bit inputs of this register are connected to by shifting one bit to the right, the corresponding bit inputs of the first register record 8 (tOe0 first to second, second to third, etc., except for the last input of the first register record 8 that is not used when the device is in operation), The second inputs (B) of the comparison block 10 Comparison of the codes are connected to the outputs of the multiplexer 27 Block 10 of the comparison codes can be performed on one element of the comparison of codes in the case of a stepper electric drive based on a four-phase motor, an element of OR-NO 3 with strobing and elements of OR-NOT and And with the number of inputs equal to the number of phase windings of the stepping motor, the inputs of the elements OR NONE and AND are combined in pairs with each other and connected with the first inputs of the comparison of the comparison element of the codes connected to the outputs of the switch 5 phases, the second input The code comparison element s are connected to the multiplexer 27 outputs, and the code comparison element outputs, the OR-NOT and AND element are connected to the inputs of the OR-NOT element 3 with gating, the gating input of which is associated with the output of the first trigger 13.

The device operates as follows:

When turning on the device and stepper motor at the moment of time

 , 0 5 0 o,. Q

five

five

116

T1 (Fig. 2) on the bus 2 turn on the engine (diagram 28) sets a low potential causing blocking the switch 5 phases and de-energizing the windings of the stepper motor 6 "The low signal from the bus 2 turning on the engine goes through the first element OR 16 to the input R the first trigger 13 and sets the trigger to the zero state (diagram 29), and the low level signal from the output of the first trigger 13, which arrives at the gating input of the code comparison unit 10, blocks it, causing a high level signal at the output and 10 and preventing the issuance of low-level signal due to the de-energized state of the stepping motor 6.

When setting the asymmetrical switching mode of the windings of the stepper motor 6, the switching mode selection bus 4 (diagram 30) is supplied with a high signal unlocking the second trigger 14 at input R, and the low signal from the bus 2 sets this trigger to one state (diagram 31) . The state of the third trigger 15 after switching on the device can be any. Let, for example, this trigger be set to the zero state (diagram 32), while its information input from the reverse bus 3 (diagram 33) is given a high level signal giving the right movement „

At time T2 (FIG. 2), a potential high level signal is applied to the engine turn-on bus 2, which sets the switch of the 5 phases to the initial state and thus provides a certain switching state of the stepper motor, for example, powering up in the case of a four-phase stepper motor first its windings corresponding to code combination 1000 (1 - phase of SM is switched on, 0 - de-energized) 0 The first one-shot 11 and BL are started at the time T2 by the signal differential on bus 2 turning on the engine (transition from O to 1) 7 to synchronization to tory can be formed, for example, in two serially connected monostable multivibrator and a delay element.

The first one-shot 11 produces, after start-up (diagram 34), a negative pulse, which is a parallel recording resolution signal and arriving at the write resolution of the first 8 and second 9 ring reverse shift registers. During this signal, the first output of the synchronization unit 7, triggered by, the differential signal at pin 2 (diagram 35), a negative pulse arrives at the second inputs of the third 21 and fourth 22 elements, the duration of which is determined by the time required to complete the transition 5 phases and windings of the stepping motor 6 when the initial switching state is set, since the fourth element of AND 22 is blocked by a high level signal arriving at its first input from the output of the second element EXCLUSIVE OR 26, at the inputs of which there are signals of different levels (high signal from bus 3 reversals and low signal from direct output of the third trigger 15), and the third element And 21 is opened by a low level signal from the output of the first element EXCLUDE - DIEE OR 25, to the inputs of which a signal the same (high) level, the negative impulse from the first output of the synchronization unit 7 passes through the third element AND 21 (diagram 36), goes to the second inputs of the second 17 and third 18 OR elements, also working in the inverse logic, and is fed from the outputs of these elements to the inputs of the shift of the first 8 and second 9 registers; 1000 and 1100 respectively, write down registers 8 and 9C, the first output pulse from the synchronization unit 7 is also supplied to the count input of the second flip-flop 14 and the clock input of the third flip-flop t5. By the difference of this pulse from O to 1 at the same time point T 3, the second trigger 14 is transferred from one to the zero state (diagram 31), allowing the passage of negative signals

0

five

0

five

0

five

0

five

0

five

through the fifth element And 23, as well as the receipt of data from the output of the first register $ (code combination 1000) through the multiplexer 27 (with the zero state of its address input A) to the second comparison inputs of the code comparison block 10, while in the third flip-flop The 15 high level signal present at the information input will be rewritten to the direct output of the trigger 15 (diagram 32), causing the low level signal to appear at the output of the second element EXCLUSIVE OR 26, allowing the passage of negative pulses through the fourth element AND 22t T This element 21 is then blocked by a high level signal from the output of the first element EXCLUSIVE OR 25. After writing data to the first 8 and second 9 registers and setting the second trigger 14 to the zero state on the first (A) and second (B) inputs Comparison of block 10 Comparison of codes contains the same code combinations (1000), confirming the normal operation of the drive, however, block 10 is locked with a low level signal arriving at its input gating and output of the first trigger 13. The strobe is removed at the moment of time T 4 due to the installation of the first trigger 13 in the unit state by a negative clock pulse received at the input S of the first trigger 13 from the second output of the synchronization unit 7 (diagram 37), which generates this pulse by the signal differential (at the time of the TZ) at its first output with some time delay required for completion of transients in the first 8 and second 9 registers when recording or shifting data, as well as in block 10 of code comparison

The equality of the codes on the first (A) and second (B) inputs of the comparison of block 10. after removing the strobe at time T4 in the absence of code combinations (0000) and (1111) on the first input of block 10 causes the signal to remain high at the output of block 10 , t0e0 at the output of the device and thus confirms the absence of a failure in the operation of the step-electric drive after its initial installation

y16

until a clock pulse is applied at time T5 (Figure 38).

The negative clock pulse passes through the first element OR 16 and sets the first trigger 13 to the zero state, the signal from the output of which blocks the code comparison unit 10. At the end of the clock pulse, i.e. after its transition from 0 to 1 at the time Tb at the output of the switch 5 phases, the code combination 1100 (with asymmetrical switching mode) appears, causing switching of the windings of the stepping motor 6 and working out the last step to the right. At the same time point Tb, the synchronization block 7 is triggered by a clock pulse transition from 0 to 1 and a negative pulse taken from its first output (chart 35) is fed through the open fourth 22 (chart 39) and fifth 23 (chart AO) elements And to the third input of the second element OR 17 and passes from the output of this element to the input of the shift of the first register 8, causes at the time T7 its transition from 0 to 1 shift recorded in the first register 8 data to the right and the appearance of code combination 0100 at its output. A negative impulse from the first output of the synchronization unit 7 also goes to the counting input of the second trigger 14 and by its transition from 0 to 1 switches the trigger 14 to the one state (diagram 31, time T7), which leads to blocking of the fifth element And 23 and resolution the passage of negative pulses through the sixth element And 24. The high level signal at the address input of the multiplexer 24 simultaneously causes the passage to the second inputs (B) of the comparison of the data block 10 from the output of the second register 9, i.e. code combination 1100, which is already present during normal operation of the electric drive at the first inputs (A) of block 10, and thus at the output of block 10 after the transients have been completed and the gate has been removed at time T8 by the signal from the second output of synchronization block 7 (diagrams 29) continues to maintain a high level signal. When a new clock pulse arrives at time T9, the described cycle repeats with only

eleven

ten

five

5 0 5 0 0 5 0 5 Q

the difference that the negative pulse from the first output of the synchronization unit 7 goes through elements 22 and 24 (diagram 41) and 18 to the input of the second register shift 9, causing the shift from 0 to 1 to shift the data recorded in this register and the occurrence of code combination 0110 to its output, while the second inputs of the comparison block 10 receives the code combination 0100 from the output of the first register 8, corresponding to the information on the first inputs of the block 10 during normal operation of the electric drive. Thus, each clock pulse in asymmetrical switching modes causes a shift of the code combination in one of the registers (i.e., the formation of the next specified switching state) and a comparison of the contents of the second of the registers equal to the actual state of the latter after the passage of the clock pulse and completion of transients.

When the direction of movement is changed by applying a low level signal to the 3-reverse bus, for example, at time T10 (diagram 33), the arrival of a clock pulse at time T11 (diagram 38) initially causes the blocking of block 10, i.e. exhibition strobe. At the transition of a clock pulse from 0 to 1 (at the end of it) at time T12 at the output of switch 5, Laz appears (taking into account the previous state) code combination 1100, shifted one step to the left and causing the step motor to go 6 steps left At the same time T12, synchronization unit 7 is started and a negative pulse from its first output (diagram 35) passes through the open third element 21 and 21 (diagram 36) to the second inputs of the second 17 and third 18 OR elements and is fed to the shift inputs of the first 8 and second 9 registr ditch The transition of this pulse from 0 to 1 at time T13 in the registers shifts the recorded data, causing (taking into account the previously performed shift operations and the signal level at the reverse inputs) the appearance of code combinations 1000 and 1100 at the outputs of the first 8 and second 9 registers, respectively . At the end of the negative impulse from the first

the output of the synchronization unit 7 at time T13 the second trigger 14 switches to one state (diagram 31), providing locking of the fifth 23 and unlocking of the sixth 24 AND elements, the flow of data from the output of register 9 (code combination 1100) through the multiplexer 27 to the block 10 comparison, on the first inputs of which at the moment during normal operation of the electric drive the same code combination is formed. In the third trigger 15, the low level signal at the information input is rewritten at time T13 (diagram 32) to the direct output of the trigger, which causes the third 21 to be locked and the fourth 22 unlocked. After the transients in the drive, registers and the comparison block are completed at the moment time T14, the signal from the second output of the synchronization unit 7 removes the strobe while maintaining the high level signal (that is, the no-failure signal) at the device output with

In the next switching cycle, a negative pulse from the first output of the synchronization unit 7 goes through the elements 22, 24 and 18 to the shift input of the second register 9, causing the code pattern 1001 to appear at its output, while the contents of the first register 8 are output for comparison, t . code combination 1000, while simultaneously preparing for the passage of the next pulse through elements 22, 23 and 17 to the input of the shift of the first register 8C For any deviation of the actual switching state of the stepping electric drive from the specified states recorded in registers 8 and 9, alternately shifted in each tact and issued for comparison, for example, when a short circuit of one of the included windings of the motor 6 or the closure of the non-switched winding on the power bus, as well as any abnormal change in the code combination at the output com 5 utatora phases codeword causes changes at inputs A code comparing unit 10 (including the occurrence of combinations of

11. ”with 1 or 00 ... O on these inputs) results in the appearance of a low-level signal, i.e., the signal is refused by the device output after removing

15

20

in 25 30, 5 0 d

55

strobe. This signal can be used, for example, for alarm signaling, blocking of the clock bus, emergency shutdown of a stepper motor drive, etc.

If, when the stepper motor drive and the device are turned on, for example, at time T15 (chart 28), the third trigger 15 (chart 32) is set to the zero state, and a low-level signal is given to the reverse bus 3 (chart 33) that specifies the movement to the left and coinciding with the signal level at the forward output of the third trigger 15, the negative pulse from the first output of the synchronization unit 7 (diagram 35) passes through the open fourth element AND 22 (diagram 39) and goes to the first input of the first element And 19, to the second input of which from exit first a monostable multivibrator 11 (diagram 34) is provided a negative pulse generated by this One-Shot timer differential signal on bus 2 at a time T15, and the input is simultaneously write enable first 8 and second 9 registers. Thus, during the action of the parallel recording resolution signal, a negative impulse is received at the input of the shift of the first register 8 through the first element AND 19 and the second element OR 17, at the end of which at time T16, the initial code combination 1000 is generated at the time T16 the moment at the output of the switch 5 Laz and the bit inputs of the register 8. To the input of the shift of the second register 9 a negative pulse passes from the output of the fourth element And 22 through the open sixth element And 24 (diagram 41), tr This element OR 18 also writes the code combination 1100 (taking into account the unit at the first bit input of the record of this register) with its differential from 0 to 1 at the same time point T16. At the end of the pulse at the first output of the synchronization unit 7 at time T16, the zero state of the third trigger 15 is confirmed, and the second trigger 14 switches to the zero state (diagram 31), causing the code pattern 1000 to pass from the outputs of the first register 8 through multiplexer 27

to inputs B of block 10 of code comparison, at inputs A of which, during normal operation of the electric drive, the same code combination is formed, which, after removing the strobe, maintains a high level signal at the output of the device

At the end of the negative im- | pulse at the output of the first one-vibrator 11, t, e „by the transition of the pulse from

0v 1 and thus prohibiting the further recording of information in the registers, at the time T17, the second monaural 12 (chart 42) is started, forming at its output a negative impulse which, with a low level signal

on the bus 3 of the reverse and thus on the first input of the second element AND 20 passes through this element (diagram 43) and goes to the first input of the third element OR 18, from the output of which this pulse is fed to the input of the shift of the second register 9, causing differential from 0 to

1shift of the recorded original code combination 1100, respectively, to the reverse signal in the opposite direction and occurrence at the outputs of register 9 of code combination 1001, corresponding to the switching state of the stepper electric drive in the next clock cycle “At receipt of a clock pulse at time T18 (chart 38) after this the pulse at time T18, the synchronization block 7 is restarted and the negative pulse from its first output passes through the open elements AND 22 and 23 to the third input of the second element OR 17 and further to the input of the shift of the first register 8, which leads to the appearance of a code combination

0001 at its output at the end of the shift pulse. At the same time, the second trigger 14 switches to one state, causing the output to compare the contents of the second register, i.e. code combination 1001, corresponding to the combination of the 5 phase phases established by the clock pulse at its normal operation. When the strobe is removed at time T20, a high level signal is maintained at the output of the device.

When setting the symmetric switching mode by applying a low level signal to the mode select bus 4

- five

20 5

30, -Q

,, -

0

in the zero state of the second trigger 14, for example, at time T21 (diagram 30), the second trigger 14 is fixed in the zero state (diagram 31) and does not react further to the signals at the counting input, causing the shift pulses to pass only through the fifth element 23 and comparing the contents of only the first register 8 with the data at the input A of block 10 of the code comparison, since at the address input of the multiplexer 27, in this case, a low level signal is continuously maintained. When a clock pulse arrives at time T22 ( frame 38) at the end of it at time T23 on the first output of synchronization unit 7 (diagram 35), similarly described, a negative pulse is generated, arriving at the input of the shift of the first register 8 through the open elements AND 22 and 23 and the second element OR 17. The phase switch 5 forms when a low-level signal is applied to the bus 4, the selection of the switching mode and the arrival of clock pulses are a sequence of code combinations corresponding to the symmetric mode (for example, 0010, 0100, 1000, etc. in the above practical case).

In the general case, however, the transition from asymmetrical switching mode to symmetric one and back must be made by sending a low level signal to the engine wiring bus 2 and subsequent initial installation of the stepper electric drive and the device at the start signal.

When any deviation of the actual switching state of the stepping electric drive from the preset, information about which is recorded and stored in the first register 8, a signal of failure appears at the output of the device after removing the strobe.

During the initial recording of information into the first register 8 in the case of a symmetric switching mode and the coincidence of signal levels on the bus 3 of the reverse and direct output of the third trigger 15, the recording signal coming from the output of that element AND 23 to the third input of the second element OR 17 and further on the shift input of register 8 is added to the output signal of the first element I 19, opened by the parallel recording resolution signal generated by the first single vibrator 1 I,

Thus, this device has wider operational capabilities, providing control of switching states of a stepper electric drive both in symmetric and asymmetrical switching modes of stepper motor windings with the device. This device not only controls the basic switching parameters of a stepper electric drive, such as the number of phase windings of a stepper motor included in each cycle, their shift in each cycle, change in the number of the windings to be switched on when the modes are asymmetrical ommutatsii, but also monitors the direction of movement, you are a full if necessary correct the shift (including considering transients) someone avtomatiches- information mode using relatively simple means of hardware

Claims (1)

Invention Formula A device for detecting failures in a stepper electric drive equipped with a phase switch and connected to it tires of clock pulses, reverse and switching on the engine, containing a synchronization unit, first circular reversing shift register, code comparison unit, first single-oscillator, first trigger and first OR element, whose inputs combined with the corresponding inputs of the synchronization unit and connected to the clock bus and the engine start bus connected to the input of the first one-oscillator, the output of which is The input to the recording resolution input of the first ring reverse shift register, the output of the first OR element is connected to one of the setup inputs of the first trigger, the second installation input of which is connected to the second output of the synchronization unit, the output of the first trigger is connected to the code comparison gate input, the first Comparison inputs of which are connected to the outputs of the phase commutator and combined with the discharge inputs of the first circular reversing shift register, the input Q 5 0 5 0 5 five the reverse of which is connected to the reverse bus, characterized in that, in order to expand the operational capabilities by providing control of the states of a stepper electric drive during asymmetrical switching, a switching mode selection bus, a second one-vibrator, a second and a third trigger, a second and a third element OR, six elements are introduced And, the first and second elements are EXCLUSIVE OR, the second circular reversing shift register and multiplexer, whose outputs are connected to the second comparison inputs of the code comparison block, the address input one is connected to the direct output of the second trigger, the first and second inputs of the multiplexer are connected to the outputs of the first and second circular reversing shift registers, respectively, the shift inputs of which are connected to the outputs of the second and third elements respectively, the first inputs of which are connected to the outputs of the first and second elements , the second inputs are combined and connected with the output of the third element I, the third inputs are connected to the outputs of the fifth and sixth elements AND, respectively, the first inputs of which are connected respectively There are direct and inverse outputs of the second trigger, and the second inputs are connected to the output of the fourth element I and the first input of the first element I, the second input of which is connected to the output of the first one-oscillator and combined with the recording enable input of the second ring reversing shift register, bit the write inputs of which are connected with a shift of one bit to the outputs of the phase switch, and the reverse input is connected to the reverse bus and combined with the first input of the second And element, the information input of the third trigger and the first inputs The first and second elements EXCLUSIVE OR, the second inputs of which are connected respectively to the inverse and direct outputs of the third trigger, and the outputs are connected to the first inputs of the third and fourth elements And, the second inputs of which are connected to the first output of the synchronization unit and connected to the clock input of the third trigger and the counting input of the second trigger, the setup inputs of which are connected to the switching mode selection bus and the input of the first one-vibrator oscillator connected to the second input of the ra, the output of which through the second one of the element I.