SU1474822A1 - Pulse distributor for controlling four-phase stepping motor - Google Patents

Abstract

The invention relates to electrical engineering and can be used in switches of stepping drives based on four-stroke stepping motors. The purpose of the invention is to enhance operational capabilities. The distributor contains control buses, clock pulses, reverse, gating, switching mode selection, a reversible binary counter 1 and multiplexers 2-5, whose address inputs are connected to the discharge outputs of counter 1, and the outputs are used as outputs of the distributor. Expansion of the operational capabilities of the distributor is achieved by providing two typical four-stroke switching modes, correct reversal, and both fixed parking and parking with de-energized windings while maintaining information on the status of the distributor. 1 il.

Description

The national inputs are connected to the remote outputs of counter 1, and the outputs are used as the outputs of the distributor. Expansion of the operational capabilities of the distributor is achieved by ensuring

two typical modes of four-stroke commutation, correct reversal and modes of both fixed parking and parking with de-energized windings while maintaining information on the status of the distributor. 1 tab., 1 Il.

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The invention relates to the control of electric machines and can be used in a discrete electric drive.

The purpose of the invention is to expand the functionality.

The drawing shows a block diagram of a pulse distributor for controlling a four-phase stepper motor.

The distributor contains a reversive binary counter 1, connected to a clock input (C) with a clock bus, an input of counting resolution (V) - to a control bus, and an input to specify a counting direction (Ј1) - to a reverse bus. The output of the low order of counter 1 is connected to the first (lower) address inputs of the first 2, second 3, third 4, and fourth 5 multiplexers, the second (senior) address inputs of which are combined and connected to the input of the high bit of counter 1, the first information input of the first 2 the second information input of the second 3, the third information input of the third 4 and the fourth information input of the fourth 5 multiplexers are combined and connected to the power bus Eh, the second information input of the first 2, the third information input of the second 3, quarters An information input of the third 4 and the first information input of the fourth multiplexer 5 are coupled and connected to the bus mode selecting switch. (bus Mode), the third and fourth information inputs of the first 2, the first and fourth information inputs of the second 3, the first and second information inputs of the third 4, the second and third information inputs of the fourth 5 multiplexers are combined and connected to the common bus, the gate inputs of multiplexers 2 -5 are combined and connected to the Strobe gating bus, and the outputs of the multiplexers 2-5 are the outputs of the distributor.

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The device works as follows.

The clock pulses arrive at the clock input C of the reversible binary counter 1 and, if a potential counting resolution signal is applied to the control bus, the counter 1 counts them, and the binary number written to the counter increases or decreases by one with each clock pulse potential signal at the input to set the counting direction. In the forward count, for example, the binary code 00-01, -10-11 -00 is formed at the outputs of the counter 1 in the initial zero state, while in the reverse counting the binary code is formed in the following sequence: 00-11-10 -01-00. This binary code, arriving at the address inputs, multiplexers dyes 2-5, causes the corresponding potential signals to be overwritten from the information inputs of the multiplexers to their outputs if an enabling potential signal, for example, a low level, is fed to the gate bus. At the same time, at the outputs I-IV of multiplexers 2-5, code combinations are generated corresponding to the phase switching mode of the stepping motor. The dependence of the potentials at the outputs of the distributor from the potential signals on the switching mode selection bus and the reverse bus is given in the table.

The table shows that when a potential high level signal (logical unit) is applied to the switching mode selection bus, the proposed valve provides four-stroke paired switching of the phases of the stepper motor, while the potential low signal (logic zero) on the bus bus causes four-stroke switching with the alternate inclusion of the windings of the stepper motor. When the potential changes on the reverse bus, the distributor on the next clock pulse provides the formation of a reverse sequence of output signals, and the supply of the reverse signal does not cause skipping or working off extra steps.

When a potential signal to prohibit an account is sent to the control bus, i-counter 1 stops, preserving the previously recorded code on its outputs, thereby providing a fixed position of the stepper motor without loss of information.

If in this mode a prohibitive potential high level signal is sent to the distributor gating bus, then all outputs of multiplexers 2-5, regardless of signal levels at information and address inputs, appear to be of the same (zero) level, providing de-energization of stepper motor windings , moreover, information on the status of the distributor, incl. The driving direction and switching mode are also maintained when the motion is resumed, i.e. By supplying a low potential to the gate bus and a signal to enable the counting on the control bus, the stepping motor begins to work out steps from the same position in which it stopped. The standby mode with de-energized windings is especially effective when the stepping motor must make long stops without loss of information during operation. Under these conditions, this mode significantly increases the efficiency of the device as a whole while

facilitating the thermal conditions of other drive units (power supply unit, power amplifiers, the stepper motor itself).

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In comparison with the known technical solutions, the proposed pulse distributor for controlling a stepper motor has broader functionality, providing two typical four-stroke switching modes of the stepper motor windings, and the transition from one switching mode to another can occur both during parking and in the motion process, and is accomplished by changing the potential on the switching mode bus. The distributor provides, in addition, the correct reversal of the stepper motor without losing or working out extra steps in the reverse mode, as well as the mode of the fixed station with the windings turned on, and the station with the provided windings, while maintaining information about its last state.

Along with wide operational capabilities, the distributor is also characterized by ease of implementation. It can be implemented on a single IC1111 chip 564 (a reversible binary counter with a reset, a counting resolution input and an output for specifying the counting direction) and two KP1 chips 564, each of which contains two 4: 1 multiplexers with a common address input and in one package gating.

Claims (1)

Invention Formula A pulse distributor for controlling a four-phase stepper motor, containing a two-digit binary counter, with clock inputs and counting inputs, characterized in that, in order to expand operational capabilities, first, second, third and fourth multiplexers are added, the gating inputs of which are combined to connect to bus gate, the first information input of the first, the second information input of the second, the third information input of the third and fourth information input of the fourth. of multiplexers combined to connect to the power bus, the second information input of the first, the third information input of the second, the fourth the information input of the third and the first information input of the fourth multiplexer are combined to connect to the switching mode selection bus; the third and fourth information inputs of the first, first and fourth information inputs of the second, first and second information inputs of the third, second and third information inputs of the fourth multiplex1 (Four-stroke 1 on parna) O (Four shots alternately) The common address inputs of the multiplexers are combined and connected to the low bit output of a two-bit binary counter, the second multi-pixel address inputs are combined and connected to the high bit output of a two-bit double counter containing an input for setting the counting direction. . Oj ten eleven 00 01 00 eleven ten 01 00 eleven. ten 01 00 eleven 00 01 10 eleven 00 eleven 01 0o JО eleven 1O oo 01 eleven 1O oo oo 01 1O oo 1O 01 oo oo 1O 0 1 1 о о о 1 1 о о о 1 о о о о о 1 oh oh about o 1 1 o 1 1 o o 1 1 o o o 1 o o o 1 o