SU1758825A1 - Device for controlling two-phase step-breaking step motor - Google Patents

Abstract

The invention relates to the field of electrical engineering and can be used to control a two-phase stepper motor with an active rotor and with a saturated magnetic system. The goal is to simplify the circuit and increase reliability. The device contains two reversible power amplifiers, switching the corresponding phase windings of the engine, a divider, for example, two multiplexers, a reversible binary counter, a reversing pulse distributor and two groups of keys with four keys in each group. The device implements alternating power windings with any step splitting factor. 3 il. THX

Description

The invention relates to the field of electrical engineering and can be used to control two-phase stepper motors with an active rotor and with a saturated magnetic system in the electric crushing mode of a step.

The purpose of the invention is to simplify and increase reliability.

Figure 1 shows the functional diagram of the device; Fig. 2 shows timing diagrams of the control currents in the phases; FIG. 3 is the nomogram of the resultant moment for the step fragmentation factor.

The device contains (Fig. 1) a resistive voltage divider 1 connected to the Don reference voltage bus. the first 2 and second 3 multiplexers, the information inputs of which, depending on K, are connected to the corresponding outputs of divider 1, a reversible binary counter 4, the bit outputs of which are connected to the address inputs of multiplexers 2 and 3. and the control inputs to the corresponding clock buses T, of the reverse Roar and initialization setting Ust O. reversing pulse distributor 5, the control inputs of the forward (B - forward) and reverse (H - back) switching steps of which are connected to the transfer outputs P and the borrowing (3) of the reversing binary counter 4, and the inputs of the reverse and reset to the initial state - with the corresponding device buses, two groups of keys b and 7, the signal inputs of which are connected respectively to the outputs of multiplexers 2 and 3, and the control inputs VJ SP 03

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dy - with the outputs of the reversing pulse distributor 5, the first 8.1 and the second 8.2 reversing power amplifiers, the inputs of which are connected to the corresponding outputs of the keys 6 and 7, and the outputs with the corresponding phase windings 9.1 and 9.2 of the stepper motor.

The device works as follows.

Before starting work on the team of Const. About the counter 4 and the distributor 5, the initial logical states are established, in which the bit outputs of the counter 4 have zero potentials and the first output of the distributor 5 is selected. In accordance with this, the first informational inputs of multiplexers 2,3 and keys 6.1, 7.1 are selected.

If a unit logic potential is applied to the device's Rev bus, then, when clocking pulses arrive, bus T provides the summing up of counter 4, and at the outputs of distributor 5, the right switching order is 1-2-3-4-1 -...

If a zero logical potential is applied to the device's Rev bus, then the subtraction mode of counter 4 is provided, and at the outputs of the distributor 5, the reverse switching order is 1-4-3-2-1 -...

After each overflow of the counter, the transfer or borrowing terminals (depending on the summation or subtraction modes) form the corresponding signals switching the distributor 5.

Alternately sampling the information outputs of multiplexers 2,3 in accordance with the change in the output code of counter 4 leads to the corresponding switching of the output voltages of divider 1. Alternately, the selection of keys 6.7 leads to further distribution of these voltages across the inputs of amplifiers 8.1 and 8.2. As a result of this, in the phase windings 9.1 and 9.2 of the engine, corresponding periodic stepwise rising and falling currents are created (Fig. 2) and the engine works out the corresponding fractional steps in one or the other direction. In this case, the vector of the resulting engine torque describes a quasi-circular nomogram (Fig. 3).

The operation of the device with other factors of fragmentation step (3,4,5,6, ...) is the same way.

In general, the conversion factor of the counter 4 and the number of information inputs

multiplexers 2 and 3 are chosen equal to the fragmentation factor of step K.

As can be seen from the nomogram of the moment vector (fig.Z) thanks to this construction

the device can compensate to a certain extent for nonlinearities of the engine with a saturated magnetic system and thus significantly improve the accuracy of the fractional steps.

Thus, the proposed device favorably differs from the known similar devices in terms of the provided precision in the processing of fractional steps, the simplicity of the scheme and reliable operation.

Claims (1)

5 claims A device for controlling a two-phase stepper motor with a split pitch, comprising a logic unit, first and second reversible power amplifiers, 0 characterized in that, in order to simplify the circuit and increase reliability, the logic unit includes a reversible binary pulse counter, a resistive voltage divider, two 5 multiplexer K by 1. where K is the fragmentation factor of the pitch, the first and second groups; Key keys in each group have four keys, a reversing pulse distributor, and a voltage source, the information inputs of the first and second multiplexers, depending on K, are connected to the corresponding outputs of the voltage divider, and the address inputs - to the binary outputs of the binary counter, 5 the output of the first multiplexer is connected to the signal inputs of the first and third keys of the first group and with the signal inputs of the second and fourth keys of the second group; the output of the second multiplexer is connected to the signal inputs of the second and fourth keys of the first group and to the signal inputs of the first and third keys of the second groups, the first through fourth outputs of the pulse distributor are connected to the control inputs from the first to fourth keys of the first and second groups, respectively, and the forward and reverse order inputs are The values correspond to the transfer and borrow outputs of the dual counter, the synchronization input of the binary counter is connected to the device clock bus, and the reverse and reset inputs of the binary counter and pulse distributor are connected to the corresponding buses of the device, the first input of the first reversible power amplifier is connected with the outputs of the first and fourth keys of the first group, and the second input - with the outputs of the second and third keys of the same group, the first the input of the second reversible power amplifier is connected to the outputs of the first and second keys the second group, and the second input - with the outputs of the third and fourth keys of the same group. 17 wffJcm.aO 2. fig 1