SU1221746A1 - Pulse repetition frequency divider with automatic countdown change - Google Patents

Abstract

The invention relates to a pulse technique and can be used in machine tools with computer program control. The purpose of the invention is to expand the functionality of providing the functional dependence of the output frequency variation over time. The device contains a frequency divider 1, input 2 and output 3 tires, elements 4, 5 and 18 And, triggers 6, 7 and 17, reversive 8 and subtracting 12 pulse counters, decoder 9 maximum code, decoder 11 zero code, code bus 13, delay element 14, persistent storage device 15 and launch bus 16. As a decoder 9 and 11, code comparison elements can be used, which will allow changing the limits of variation of the output frequency, 1 slug. € to ee od

Description

V

The invention relates to a pulse technique and can be used in numerically controlled machine tools, in particular for acceleration and deceleration of executive stepping motors.

The purpose of the invention is to expand the functionality by providing a functional dependence of the output frequency variation over time, in particular, in the process of adjusting the position of the actuator.

The drawing shows the electrical structure of the device.

A pulse frequency divider with automatically varying division ratio contains a frequency divider 1, the clock input of which is connected to the input bus 2, the output to the output bus 3 and to the first inputs of the first and second elements 4 and 5 And, the second inputs of which are connected to the outputs respectively the first and second triggers 6 and 7, and the output with the inputs, respectively, of the summation and subtraction of the reversible counter of pulses 8, the output of which is connected to the input of the decoder 9 of the maximum code and to the first input of the code comparing unit 10 c, the second input of which is connected to the input of the decoder) 1 of the zero code and with the output of the subtracting counter 12 pulses, the information inputs of which are connected to the code bus 13, the first bit of which is connected to the information input of the first counter of the pulses8 pulse, element, 14 delay whose input is connected

with output bus 3, output - c 3X0, frequency recorder 1 recording house, the information inputs of which are connected to the output of the permanent storage device 15, whose address inputs are connected to the output of the reversible pulse counter 8, the recording input of which is connected to the record input of the subtracting pulse counter I2 of pulses , with the start bus 16, with a single input of the first O of the trigger 6 and with a single input of the third trigger 17, the output of which is connected to the first input of the third element 18 And, the second input of which is connected to the output bus 3, the output is countable subtracting input of the counter pulses I2, the output of the decoder 11 nule462

The first code is connected to the zero inputs of the second and third triggers 7 and 17 and to the first zero input of the first trigger 6, the second zero input of which is connected to the single input of the second trigger 7 and to the output of the code comparison unit 10, the third zero input to the decoder 9 output maximum code. As a decoder 9 and 11, both well-known decoders, for example, K-155IDZ type, and code comparison elements can be used, in the latter case, the limits of variation of the output frequency can be changed.

The pulse frequency divider operates as follows.

Pulses with frequency F are received from bus 2 to clock input of divider 1. Overflow pulses from divider I output, coming through element 14 to divider 1 recording input, write the code from device 15 output to divider 1. Frequency F. output

oblX

divider 1 will remain constant until the specified code value is entered into counter 12. The triggering pulse on bus I6 records the code received on bus 13 into counter 12 and the first discharge of counter 8, and also triggers 6 and 17 are set to one state. Allowing potential from single output of trigger 6 permits the passage of frequency F through element 4 And to the summing input of counter 8, and the resolving potential from the "single output of the trigger 17 allows the passage of the frequency Fg through the element 18" And to the counting input of the counter 12. From this moment the code at the output of the counter 8 starts to increase linearly and at the output of the counter 12 - linearly smart shats. Thou shalt increase every one. If the code in the counter 8 arriving at the address inputs of the device 15, corresponds to exactly the same code value at the output of the latter, then the increase in the frequency Fg will follow a linear law. If each code increment in counter 8 corresponds to the code value at the output of device 15 with a different law, then the frequency Fg will be

Been doing so in the same way.

If the code value in counter 1 is more than twice the code value determined by decoder 9, then the signal from the output of decoder 9 sets trigger 6 to zero and thereby removes the permissive potential from the input of element 4,

prohibiting the passage of the frequency R.

out

to the summing input of counter 8. From this point on, the maximum pulse frequency F ,, from the output of divider 1 is maintained until the code in counter 8 is comparable to the code in counter 12, while the signal from unit 10 sets the trigger 6 in the zero state, and the trigger 7 g - in the unit. The resolving potential from the single output of the trigger 7 permits the passage through the element 5 of the frequency to the subtracting input of the counter 8. From this moment begins the decrease in the code value in the counter 8 and the decrease in the frequency F, according to the law laid down in the device 15

When the code in the counter 12 becomes zero, the 1I decoder will generate a signal by which the triggers 6, 7 and 17 are set to the zero state, thus the device is reset.

To perform a new operation cycle of the device, a new code value is fed through bus 13 to counter 12 and simultaneously the value of the first bit of this code to the information input of the first bit of counter 8 (to create an even difference between the code values in counters 12 and B when comparing they are in the block u) - and a triggering pulse is fed through bus 16.

If the code value in counter 12 is less than twice the number determined by decoder 9, then the frequency F of the output from divider 1 increases to such a value until the increasing code value in counter 8 becomes equal to the decreasing code value in counter 12. As a result, the block 10 generates a signal, KOTOpbiM sets trigger 6 to the zero state, and trigger 7 sets to one. From this point on, the frequency of impulses output will begin to decrease for the law laid down in device 15. The cycle of operation

1221746

ends in the same way as described by Bbmie when the zero value of the code appears in the counter 12.

The frequency at the output of divider 1 is equal in all cases

would

where n is the number of bits of the divider I, P is the code value at the output of the permanent storage device, which is a function of the code value — at its input

15

P, f (i),

where i is the output code value

counter 8; , 2..Г is a positive integer.

If PJ i, then the frequency at the output of divider I will vary linearly.

If a

;

L and K - ... where

integers written in device 15, integer ratio i

TO

then the frequency at the output of the divider I will change step by step every K frequency pulses F by

Bh,

Claims (1)

a quantity proportional to the number L. Formula of the invention Pulse frequency divider with automatically varying the division factor containing a frequency divider, the clock input of which is connected to the input bus, the output to the output bus and to the first inputs of the first and second elements And, the second inputs of which are connected to the outputs of the first and second triggers, respectively, and the outputs to the inputs of the summation and subtraction of a reversible pulse counter, respectively, the output of which is connected to the input of the decoder of the maximum code and to the first input of the code comparison unit, the second input of which is connected to the input of the decoder zero code and with the output of the deductive pulse counter, the information inputs of which are connected to the code bus, the first bit of which is connected to the information input of the first bit reversibly of the counter. and shulsy, and the third element AND, which is related to the fact that, in order to expand the functionality by providing a functional dependence of the output frequency variation over time, a third trigger, a permanent storage device, a triggering element and a delay element are entered into it connected to the output bus, the output to the recording input of a frequency divider, the information inputs of which are connected to the output of a permanent storage device, the address inputs of which are connected to the output of a reversible pulse counter, course record which soeSostavitel Sokolov Editor Petrova Tehred V.Kadar Order 1620/59 Circulation 816 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Branch GShP Patent, Uzhgorod, st. Project, 4 dinene with the input of the record of the subtractive pulse counter, with the start-up bus, with the single input of the first one and with the single 1-INPUT of the third trigger, the output of which is connected to the first input of the third element And, the second input of which is connected to the output bus, output CO with the counting input of the subtractive pulse counter , the output of the zero-code decoder is connected to the zero inputs of the second and third triggers and to the first zero input of the first trigger, the second zero input of which is connected to the single input of the second trigger and output block comparing the codes, the third zero-input - with the output of the decoder maximum code. Proofreader L. Patay