SU1377852A1 - Device for sorting numbers - Google Patents

Abstract

This invention relates to automatics and computing. The purpose of the invention is to expand the scope of application by providing the ability to sort arrays of unlimited length. The device contains counters, triggers, a comparison unit, an extreme unit, an impulse generator, an adder-subtractor, AND, OR, OR-NOT, 2I-SHSh, differentiating elements. The first m numbers are written to the counters. the content of which starts decreasing by one, while simultaneously counting pulses in the output counter. When a zero is established in a counter, the contents of the output counter are output to an external storage device (OVC), and the next number from the array is entered into the released counter. If the newly entered number is greater than the number just displayed, it is reduced by the value of the number just output before being written to the counter, if less, then the record is recorded without a change to the counter, which is then masked by the zero state of the lock trigger. When all the counters are disguised, they are de-masked, and the process is repeated from the output to the memory of the new-range of sorted numbers. After the entire array has been sorted, the process is repeated, with the numbers taken sequentially from all the previously sorted segments. 1 il. (L with vi 00 SP y

Description

11377852

The invention relates to automation and computing.

The purpose of the invention is to expand the scope of application by providing the ability to sort arrays of unlimited length ..

The drawing shows a diagram of the device.

in counter 1, a single signal generated at the direct output of the element OR 12 will set trigger 4 to the zero state.

Then the pulses from the generator 7 are fed to the subtracting inputs of counters 1 and the summing input of the counter 2. After some time in the counter 2

The device contains a group of counts that will be recorded as the minimum of

1.1 j, where m is the number of odm numbers, and in some counter, 1 O, which is recognized by the OR element. In this case, the selected number, followed by a sync pulse on

newly sorted numbers, output counter 2, blocking triggers 3, -3 "groups, control trigger 4, adder-subtractor 5, extreme allocation unit 6 (BVKE), 7-pulse generator, comparison block 8, element groups I 9, - 9p ,, 10, 1b - group of elements ШШ 12, - 12 „, group of differentiating elements 13, - 13„, elements И 14-16, element

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OR 17, element 2И-OR 18, element ШШ-НЕ 19, group of information inputs 20, inputs 21 and 22 of start and stop, group of information codes 25 23, synchronization output 24 and output 25 of operation termination 25,

A single signal at the output of the comparison unit 8 is formed when there is a single signal at its control- ZO input and if FF, where F ,, are the numbers located respectively in counter 2 and input to input 20. Totalizer-subtractor 5 forms the difference FS F20-P, lR, where Fg is the signal at the output of comparison unit 8. BVKE 6 forms a single signal at the output with the minimum number of those inputs on which there are one. no signals. The counters 1, 2 are previously set to the zero state, the triggers 3, 4 are set to one.

The device works as follows.

After starting at the input 21 of the generator 7 pulses, the sorted numbers, preliminarily arriving at the input 20, pass through the adder-subtractor 5 without change and are recorded sequentially in counters 1-1 "(after writing the number into the counter where 1 1.2t-1, on the inverse output of the element OR 12, zero is present and a single signal will be generated at the (1 + 1) -th output of the PIDU 6) by a pulse from the generator of 7 pulses passing through the element. 2I-OR 18 to synchronization codes of all counters 1. After recording the number

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20

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five

five

About m numbers, and in some counter 1 - O, which is recognized by the OR element. In this case, the allocated number, accompanied by a sync pulse at the output of the course 24, enters the outputs 23 of the device and is recorded in an external storage device (OVC). In releasing the counter 1, /, the next number from the sorted array is entered. In this case, two options are possible. ,

If the newly entered number is not less than the number accumulated in the counter 2 ,. those.

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five

0

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F ,,,, F ,, as determined by comparison unit 8, the difference F is calculated, - F2 (which is entered into counter 1; /, and the device continues operation. If FIO P / g means that the number F , must be among the numbers already recorded in the EEP. In this case, the number is recorded without change in the counter, and the trigger 3 is set to the zero state, the reduction of the number recorded in the counter 1 is blocked.

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After some time, all the triggers 3, - 3 "will be set to the zero state, which is recognized by the element OR-NOT 19, the output signals of which are set to one state, all the triggers 3 - 3", the balance 2 in O, and the device starts to form the next segment of sorted numbers and output it to the OVC.

After viewing the entire array of numbers at the input 20, the devices begin to receive numbers in series from all the sorted segments, and the device functions in the same way. .

Further, the process is repeated until a natural segment, which is a sorted array, is recorded in the OVC.

Claims (1)

Invention Formula A device for sorting numbers containing a group of w counters, where m is the number of simultaneously sorted numbers, the output counter, the first group of m elements AND, the second group of n elements AND, where n is the size of the sorted numbers, group Q. m differentiated elements, an OR element, a group of m OR elements, and the first element AND, the output of which. it is connected to the first inputs of the elements of the first group and the summing j input of the output counter, the output of the jth bit of which, where j 1, 2, ..., n, is connected to the first input of the j-ro element of the second group, output which is the output of the j-ro of the 2Q row of the sorted number of the device, the output of the 1st element AND of the first group, where i 1, 2 ..., m, is connected to the subtractive input of the i-ro counter of the group, the output of j-ro the discharge of which is connected to the j-input of the i-element OR group, the direct output of which is connected to the second input of the i-ro element AND of the first group, the output of the i-ro differentiator element of the group is connected with the iM input of the OR element, the output of which is connected to the second inputs of the AND elements of the second group, which is based on the possibility of expanding the field of application by providing the possibility of sorting-35 of the array of unlimited length, a generator pulses, adder-subtractor, terminal unit, target unit, comparison unit, control trigger, group of m blocking triggers, third group of m AND elements, OR-NOT element, second and third And elements, and 2I-OR element, and inputs start and stop at The states are connected respectively to the start and stop inputs of the generator of pulses, the output of which is connected to the direct input of the first element AND and the first direct inputs of the first and second element AND element 2I-OR, 50 whose second direct inputs are connected respectively to the inverse and thirty Q Q 5 5 0 0 the direct outputs of the control trigger, the setup input in the zero state of which is connected to the output of the second element AND, the direct input of which is connected to the direct output of the second element OR group, the inverse output of the first element OR group is connected to the ith input the third AND element, the i-ro input of the differentiating element, the first input of the i-ro element AND the third group, and the iM input of the allocation unit of the extreme unit, the i-th output of which is connected to the write enable input of the i-ro group counter, the output of the OR element is the sync input devices and soybeans Inonii with inverted inputs of the first and second AND gates and first AND-OR element 2I whose output is connected to inputs of a synchronization counter and inverted vho- group. the house of the OR-NOT element whose output is connected to the installation inputs to the unit state of the group blocking triggers and the installation input to the zero state of the output counter, the bit outputs of which are connected to the first group of information inputs of the comparison unit and the group of inputs of the readable subtractor, group inputs of which are decremented are combined with the second group of information inputs of the comparison unit and is the group of information inputs of the device, the inverted output of the control trigger is connected to the output of the summing output of the output counter and the control input of the comparison unit, the output of which is connected to the second inputs of the elements of the third group and the control input of the adder-subtractor whose outputs are connected to the corresponding information inputs of the group counters , the output of the i-ro element of the AND-third group is connected to the input of setting to the zero state the i-ro trigger of blocking the group, the direct output of which is connected to the third input the home of the i-ro element of the first group and with the i-m direct input of the element OR NOT, the output of the third element AND is the output of the end of operation of the device. Im. IFIJ 21 / 25