SU1305772A1 - Storage - Google Patents

Abstract

The invention relates to computer technology, in particular, to storage devices, and can be used in computer systems for collecting information in case of priority service or in organizing a service queue for abo- hectares. The aim of the invention is (L oo o SP ND

Description

1305

increase the information capacity of the device. The device contains data sorting units 10, -10, (where k is an integer), memory block 11, signal distributors 12 and 13, triggers 14. signal shaper 15, group of ISj-IS drivers, signals, shaper 16, -16 | installation signals, a group of counters 17, -17. signals, reversible counter 18, selector 19, multiplexers 20 and 21, a group of elements And 22 / -22k, elements And 23-25, two groups of elements 1

The invention relates to computer technology, in particular, to storage devices, and can be used in computer systems for collecting information in the case of priority servicing of a large number of subscribers or in organizing a queue for servicing subscribers.

The aim of the invention is to increase the information capacity of the device.

Fig, 1 shows a structural diagram of the proposed device; in fig. 2 and 3, structural diagrams of, respectively, each of the local control units and the memory unit.

The device contains (Fig. 1) setup input 1, information 2 and address 3 inputs, reading input 4, recording input 5, access inputs 6, indicator outputs 7 and 8, information output device 9, blocks 10, -10 data sorting (where k is an integer), memory block 11, first 12 and second 13 signal distributors, triggers, driver 15 signals, group of drivers 15-15.

9

signals shapers set-. ADDITIONAL signals, a group of counters, (signals, a reversible counter 18, a selector 19, the first 20 and second 21 multiplexers, a group of And 22 elements., - 22, And 23-25 elements from the first to the third, the first 26 and the second groups of elements OR, elements OR 28-30 from first to third, element OR-II 31, group of elements 32

Commerce OR 26 and 27, elements t-SHI 28-30, element OR-NOT 31, group of delay elements 32, elements 33-36 of delay. When writing information words, they are sorted, so that they are placed in memory block 11 in order of increasing or decreasing their absolute value, or, without sorting, are recorded in order of arrival. The order of the location of the recorded information words is specified by the control word supplied to the device access inputs. 3 il.

delays, elements 33-36 delays from one to four.

Each data sorting unit 10 (FIG. 1) contains a local control unit 37, first 38 and second 39 word registers, single pulse shaper 40, trigger 41, selector 42, multiplexer 43, elements 44 and 45 ,. elements 46 -. 48, delay elements 49-52.

Each local control unit 37 (Fig. 2) contains a decoder 53, comparison blocks 54 and 55, elements AND 56-58, an OR element 59, and a single pulse generator 60.

The memory block 11 (FIG. 3) contains the first 61 and second 62 groups of word registers, decoders 63, the groups of elements AND 64 and 65, and the group of elements OR 66.

The proposed device works as follows.

The information entering the device is represented by a parallel binary code in the form of a sequence of information words containing each byte of information (with control bits — or without control bits). Before the information enters the device, an initial installation is made to the initial state by a signal arriving at input 1 (Fig. 1), after which output 7 has a logical unit level that permits the recording of a sequence of informational headers in the device (in sort mode

or without sorting), and at output 8 - the level of a logical unit, indicating that the device has not yet recorded information in the device.

Consider the operation of the device when recording information in the mode of sorting | KI.

Through the inputs 6, the control word comes in the form of a parallel binary code containing zeros in the control bits of the layout of the recorded information words in block 11 and one in the control bits of the selector 19, multiplexers 20 and 21, resulting in inputs 3- 5 are connected respectively to a, cracked input, to the read input and to the write inputs of block 11.

After that, through input 3 and selector 19, block 11 begins to receive address codes sequentially from zero to the address of the last memory cell of block 11, input 2 for each address receives a parallel binary code of initial information (zero or one code for all information bits of each information word), and through input 5 there are recording signals for which the initial information word is recorded in each cell of block 11.

After the initial information has been recorded, input a new control word to input 6, in the last discharge of which there is a zero, and in the remaining bits there is a code of the type of information word arrangement, which is fed to the inputs of blocks 37 and which simultaneously has the same location in block 11 information words from input 2.

The recording signal (for example, corresponding to the first informational party) from input 5 through multiplexer 21 and element 25 goes to the clock input of the distributor 12, in which the logical unit from its first left output and the level of the logical unit is set at its next (for example, second) output, i.e. if the next (for example, j second) block 10 is free, the level of the logical unit from output 7 is not removed. From the output of the corresponding, for example, trigger 142 to the input of the corresponding

24

element 22 enters a logical zero level. The same recording signal from the output of the AND 25 enters the clock input of the distributor 13, at the first output of which a similar signal appears at the input of the trigger 14, and on the falling edge of the recording signal the distributor 13 switches to the next output, for example, the second and next. This recording signal appears already at the second output of the distributor 13. The same first recording signal from the output of the AND element 25 also goes to the input of the summation of the counter 18, which adds one to the number contained in it. On the leading edge of the logical unit signal from the output of the trigger 14, the driver 15 is started, which begins to form a periodic sequence of rectangular pulses. The signal from the output of the trigger 14 removes the permitting level of the unit from the output 8, which prohibits the ability to read from the device at the time of writing the information word in the sort mode, as well as the driver 40 of the corresponding block 10, generates an enable signal at the control input of the register 38, an information input of which already has an information word for the arrival of a recording signal at its clock input, which is recorded in register 38.

On the falling edge of the signal from the output of shaper 40 of block 10, it is prohibited to write the next information word to register 38 until, after resetting the corresponding trigger 14, the leading edge of the logical unit level arrives again at the trigger input of shaper 40.

The forward pulse from the output of the imaging unit 15, through the corresponding input-reading of the block 11, reads the information word (in this case, the initial information) from the address received from the output of the corresponding counter 17 /, which is written to the register 39 of the corresponding block 10. By the same signal from the output of the imaging unit 15, arriving through the delay element 50, the multiplexer 43 and the OR element 47 to the clock input of the register 39. The information words present at the outputs of the registers 38 and 39 of the block 10j are compared in block 37 to you during which a signal is formed, by which the selector 42 connects the output of register 38 to the information input of block 11. On the leading edge of this signal from the output of block 37, set trigger one to 41, the leading edge of the signal of logical unit from the output of which closes) .ent I 44, opens the element I 45 and switches the multiplexer 43, which connects the output of the corresponding shaper 15 through the delay elements 50 and 52 to the clock input of the register 39 of the block 10 and to the corresponding input of the record of the block 11 Thus, One front of the first pulse from the output of the form11 38

The rotator 15 is written into the block information word from the register of block 10, |.

On the leading edge of the first pulse c: the output of the former 15, passing through the delay element 32 of the same name, in the counter 17, one is added to the number contained in it, and the resulting code of the address of the memory cell of the block 11 is received on e. The second address input and the first information input of the imager 16, which compares the code from the output of the counter 17 with the code at the output of the counter 18-. When these codes coincide, a signal appears at the output of the driver 16, which flushes trigger 14, (via OR 26) and counter 17, (through OR 27), and, in block 10, flushes trigger 41. This stops the operation of the imaging unit 15-) (which generates only one pulse), and the output signal 8 is set to the enabling signal log and-. i units. Thus, the process of recording the first info-, rational word in the sorting mode is lawful; When writing the next invisibility of the location of the information words in block 11, block 37 is performed with the help of a decoder 53 (phig.

frontal word (for example, the second entry of which receives the first

go; the next, for example, driver 15, is triggered by a signal from the expression of the control word, i.e. the code of the layout of the informational layers (at zero in all bits of this code, the decoder 53 does not exhibit a level

rewrite; expensively rewrites from pre; ptst ;; her cell block 11 previously

written information word as a logical unit on one

The next 39, for example, block, and from its outputs).

Block 54, when the absolute value of the codes of the information words from registers 38 and 39 coincides, sets

10 ,, where it is compared by block 37 with the word written in the device by the infrared word. Depending

from the meanings of these words and the algorithm of operation of block 37, the previously written information word is rewritten into the next memory cell of block 11, and the newly received word is written into the vacant memory cell. In this case, the device works in the same way as when writing the first word.

If, when comparing the information words in any block 10, no signal is formed at the output of block 37, the AND element 45 remains closed and the previously recorded word is not moved from the cell of block 11. In this case, when the next signal arrives from the output of the imaging unit 15, the recorded information word is compared with the initial information contained in block 11 and the recorded word is placed in the next cell of block 11. Thus, the recorded words are sorted and written into block -11 in accordance with given type of arrangement of informational words.

Blocks 10, -10c are included in the data sorting process sequentially one after the other, each according to the signal from the corresponding output of the distributor 13. After the data of the last (from left to right) block 10 is included in the sorting process, the first (left to right) block 10 is switched on again (if the number of memory cells of block 11 is greater than the number of blocks 10.,) by impulse with

TO.

first exit distributor 13.

If several blocks

,

functioning simultaneously and successively one after the other, then the readout-enabling signal of a logical unit can appear at output 8 only after the last block of operation of the last block 10, i.e.

by

45 the end of the whole data sorting process.

The selection of the location of the information words in block 11 is carried out by block 37 using a decoder 53 (function ig 2),

50 entrance which comes first

control word bits, i.e. the code of the layout of the information words (with zero in all bits of this code, the decoder 53 does not exhibit a level

At its output, the signal of the logical unit. If the loaded word in register 38 is greater than or equal to the previously written word in register 39.

Block 55, when the absolute value of the information words from registers 38 and 39 coincides, exposes at its output a signal of a logical unit, if the word in register 38 is less than or equal to the word found in register 39.

Thus, it is possible to place information words written into the device in increasing or decreasing order of their absolute value (the initial information in all cells of block 11 is equal to zero or one, respectively), and also sequentially in the order of accessibility (initial information in all cells of block 11 is equal to zero).

Reading information from the device is performed by a signal at input 4 Which, through multiplexer 20, is accessed to input the subtraction of counter 18 and through selector 19, to the first reading input of unit 11. All informational words are read out from block 11 sequentially, starting from the last memory cell of block 11, to exit 9.

In the sorting mode, the pulse counter 18 counts the number of recording signals received through input 5, i.e. the number of occupied memory cells of block 11, and if all the memory cells are occupied, then the unit from the output of counter 18 closes the Element I 24, As a result, a signal appears at output 7 that prohibits further writing to the device.

Claims (1)

Invention Formula A storage device containing a reversible counter, elements; 1 first to third, the conversion of signals, the driver, the delay elements, the OR elements, and the memory block, one of the information inputs and outputs of which are the information input and output of the device, - the house of which are the inputs of the installation of the reversible counter, signal distributors and the memory block, which is due to the fact that, for the purpose of increasing,; o 50 5 o Q five Q These devices are entered into the data sorting units, triggers, a group of signal conditioners, and drivers for installation data. The group of signal counters, mu.hiaxors, the group of elements AND, the group of elements OR, the element OR-NOT, the group of elements of the delay and the sector, the first input of which is the address input of the device, and the output connected to od1: From the address inputs of the memory unit, one output of the first multiplexer is connected to the first input of the first OR element, and the other to the subtraction input of a reversible counter and the input of the first delay element whose output is connected to the second input of the first OR element that is connected to one of the inputs sci The memory unit, one of the recording inputs of which is connected to the output of the second element OR, the first input of which is connected to the output of the first element AND, and the second input to the first output of the second multiplexer, the second output of which is connected to the first input of the third element And, the second input which is connected to the output of the second delay element, the input of which is connected to the output of the second element AND whose inputs are connected respectively to the first output of the reversible counter and to the output of the third OR element whose inputs are connected with the outputs of elements AND groups, the direct inputs of which are connected to the outputs of the first signal distributor, the input of the third element AND is connected to the inputs of the third and fourth / delay elements, the first input of the first element AND, the clock inputs of the first and second signal distributors, the control inputs of which are connected with the second input of the first element And, the outputs of the second signal distributor are connected to the inputs of the trigger setup, the output of each of which is connected to the corresponding input of the RSHI-KE element, the first control the input of the corresponding data sorting unit, the inverse input of the corresponding element And group and the start input of the corresponding signal conditioner, the output of which is connected to the clock input of the corresponding setting signal generator, the first clock input of the corresponding data sorting unit corresponding to the input of the readings ;;: n of the memory block and the input of the corresponding group delay element: - .. whose output is connected to the summation input of the corresponding group signal counter, the output of each setter signal generator is connected to the first input of the settings corresponding to the data sorting unit, the first inputs of the corresponding ORS of the first and second groups, BiKiOAbi elements OR of the first group are connected to the reset inputs of the trigger, and the outputs of the OR elements of the second group - to the inputs of the installation of the signal counters of the group, all,: one to each of which is connected to with :; geetvuyushlk address address block input la. - TP and the first informational., ОS, OM of the corresponding driver are installed:: the signals, the second information inputs of the installation drivers are: the signals and the second input of the selector are connected to the second top of the reversing counter, the summation input of which is connected to the output of the third delay element the third input of the selector is connected to the first input; and the multiplexers, the output of the fourth delay element is connected to the second 577210 clock inputs of sorting units data, one of the information inputs of which are connected to one of the information inputs of the memory block, the information output and other information input of each data sorting unit are connected to the corresponding other information input and information output of the memory block, and f (; clock output: Airborne 6: ioica data sorting is connected to the corresponding other input of the storage unit, the second inputs of the elements of OR groups, the installation inputs of the drivers of the installation of new signal sorts and the second inputs of the installation of the data sorting units , the first inputs of the multiplexers, the second input of the first element AND, and the second control inputs of the data sorting units are the inputs of the operation mode of the device, whose indicator codes are respectively the output of the second element a5 Derzhko and an output of a NOR second inputs of the first and second z-gulti- plexor are respectively input read and write input ycTpoiicTBa. Hmfi from 3S On C 2. FIG.