SU1310803A1 - Device for storing numbers - Google Patents

Abstract

The invention relates to automation and computing and can be used in devices for sorting numbers. The purpose of the invention is to increase the speed of the device. The device contains a group of registers 6 - 6, comparison circuits 7 triggers 1 - 1p, groups 4 - 41 elements AND, two counters 8, 9, result register 5, pulse distributor, made in the form of a selection unit 2 starlos units, address generator, performed on the scheme of the permanent storage device 12, a group of additional registers Yu - 10. At each clock cycle, all the numbers of the array that have the same values are sorted at once, which allows to increase the speed of the device, the formation of a sorted array in addition These registers allow you to save the original array after sorting. I zp f-crystals, 1 tab., 2 ill. / J (O (L G4 00 o CX5 o co (rig 1

Description

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The invention relates to automation and computing, and more specifically to devices for sorting numbers, and is intended to order arbitrary arrays of numbers in data processing systems.

The purpose of the invention is to increase speed.

The invention consists in the use of additional registers, a persistent storage device and a high-speed allocation node of the higher unit, each sort being sorted. Immediately all array numbers having the same values, resulting in the sorting duration equal to k cycles, where k is the number of different values of numbers in sorted array and the process of forming signals at the output of a permanent storage device, allowing the recording of the analyzed number in the corresponding The information registers intended for storing the sorted array, and the process of issuing, under the control of the allocation node, the highest unit of the next number to be analyzed, to the information inputs of the result register are aligned in time, which improves the speed of the device. In addition, the formation of a sorted array in additional registers eliminates the need to swap the numbers of the original array during the sorting process and, after sorting, saves the original array, providing the ability to control the sorted array, which improves the reliability of the device, as well as: from it a large number of delay elements.

1 shows a block diagram of a device for sorting numbers; Fig. 2 is a schematic of the allocation node of the higher unit.

The device contains (see Fig. 1) triggers, C p node 2, selection of the highest unit, element OR 3, groups 4 4 elements AND, result register 5, registers 6 b ,,, schemes 7 - 7 comparisons, counters 8 and 9, additional registers 10 - 10, element 11, fixed memory 12, input 13 clock pulses of the device and output End sorting 14 of the device.

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The node 2 of the selection of the senior unit contains (see Fig.2) the elements OR-NOT 15, -15jj, the elements AND 16 i -, the inputs 17-17, the subgroups 18-18

inputs 17 and outputs 9 - 19 ,.

Each of the n flip-flops 1 is a T, -Trigger (i.e., a synchronous T-flip-flop with an internal delay) triggered by a negative voltage drop at the synchronization input: the unit at the information input T in this case causes a flip-flop to the opposite state When zero at input T, the state of the trigger does not change. Triggers 1 are meant to inform those. the numbers of the array that have not yet participated in the sorting process, and before the start of sorting, are set to one by supplying a signal to input S (not proven).,

The U.S. 2 highlight unit is used to quickly select a single signal present at the output of trigger 1 with the smallest number and block single signals from the outputs of all other triggers 1. At maximum speed (the node's response time is the sum of the element response times OR-NOT and the element AND) such an organization of the structure of communications between the inputs 17 of the node, the elements OR-NOT 15 and the elements AND 16 of the node provides minimal equipment costs when implementing the node. The Element TI-NO element 15 with the number R; + Wg, where S 1,2, ..., R, and Wg 0,1 ,, .., ms-l, has Ws +1 inputs, And 16 with the number Kg + Wg has S + 1 inputs. The element OR 3 has n inputs and is intended to generate a zero signal. The sorting end at the device output 14 after analyzing all the array numbers, as a result of which the AND 1 element is locked, which terminates the effect of the clock pulses on the device.

Each of the n groups of 4 elements And contains m two-input elements And, where m is the size of the sorted numbers, and is intended to connect the output of the same name register 6 to the information input of the result register 5 if there is a single signal on the control; their inputs are I.

The outputs of the elements of the same name AND of all groups 4 are combined according to the installation OR scheme, therefore the elements AND must be implemented according to the scheme with an open collector, and even better according to the scheme with three states.

The result register 5 consists of m synchronous D-flip-flops triggered by a single signal level at the synchronization input, and is designed to receive the next analyzed number with the arrival of a clock pulse at the clock input, to store this number during the clock pulse period and to issue it to the inputs all the comparison circuits 7 and all the additional registers 10.

Each of the n registers 6 consists of m synchronous D-flip-flops triggered by the signal level at the synchronization input, and sl5; a sweep for receiving the corresponding number to be sorted (the receiving circuit is not shown) to store this number and output it to the inputs of the same-name circuit 7 Comparison and informational inputs of elements of the same group 4.

Each of the n comparison schemes 7 is implemented in the standard way and is intended for comparing two t-times of the real numbers and forming at its two outputs the signals Smaller and Equal.

Counter 8 is used to count the number of comparison circuits 7 that have single signals at the outputs Less and is implemented in the standard way.

The counter 9 is designed to count the number of comparison circuits 7 having single signals at the outputs of Equals, and is implemented in the standard way.

Additional registers 10 are used to receive and store the numbers of the sorted array. Each of the n registers 10 consists of m synchronous D-triggers, triggered by the level of the signal at the synchronization input.

Element And I1 has 2 inputs and is designed to block clock them

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15

20

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pulses arriving at the input 13 of the device when forming the zero signal End of sorting at the output of the element OR 3.

Permanent memory 12 is a standard ROM having +2 address inputs, where square brackets are

the operation of extracting the integer part of the number, the inverse control input, and the n outputs. The output of the number from the ROM cell with the address set on the address inputs occurs at a zero signal at the control input, i.e. after the expiration of the next, clock pulse.

The programming logic of the ROM is simple. Let the outputs of the counter 9 are connected respectively with the lower address inputs of the ROM, and the outputs of the counter 8 with the higher address inputs of the ROM, i.e. the full address A, arriving at the ROM, in the older half of the section, series of AI carries information p the number of numbers in the array that are less than the analyzed number, and in the younger half of the digits A - information about the number of numbers in the array equal in value to the analyzed number. Then it can be seen (the array is sorted in order of increasing values of numbers) that the analyzed number should occupy an in-sorted array (A, +1) -th place, and the subsequent Ag-1 places should be occupied by numbers equal in value to the analyzed one (to AJ includes the unit that the analyzed number gives), i.e. The number to be analyzed should be written in all additional registers 10 that have numbers from (A + 1) to (A +

- TETU rrtrtTTTTrri l g

35

40

45

+ inclusive, and consequently, in the ROM cell with the address A equal to, it is necessary to record the units in all digits from (A + 1) -th to (A + A2) -th, inclusive. So, for example, for the case when n is equal to three

and addresses A

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two-digit,

accordingly, we have the following ROM programming table:

1st bit 01 1 1000000000000 2nd bit 0011011000000000 3rd bit d 0001001001000000

Of the 16 addressable ROMs, the information is entered only in 6, which speeds up and facilitates the programming of the ROM. This is explained by the fact that many address combinations are not working, i.e. during operation of the device, these combinations of counters 8 and 9 are not formed. Non-working addresses are those that correspond to A2., Equal to zero (since there is at least one number in the array always equal to the one being analyzed), as well as those addresses that give the sum А + А2, greater than n.

The device works as follows.

Before the start of operation, the triggers I are set to one state, and the registers 6 are added to the sortable numbers, after which the device is ready to sort the numbers in ascending order.

When the first clock pulse is applied to the input 13 of the device, it goes through the element 11, open a single signal from the output of the element OR 3, passes to the control input of the result register -5, allowing the register in register 5 of the number received from the output of the upper register 6 And elements opened with a single signal from the top (first) output of node 2, while all other outputs of node 2 will have zero signals generated by the corresponding OR-NOT 15 and AND 16 elements of node 2 under the influence of the highest unit on the top (first) inlet node . The analyzed number recorded in register 5 is compared with all the sorted numbers in comparison circuits 7. Score0

five

0

five

0

five

0

five

Chick 8 counts the number of comparison circuits that have single signals at the outputs Smaller, indicating that the numbers in the corresponding registers 6 are less than the number being analyzed, and counter 9 calculates the number of comparison circuits that produce single signals at the outputs Equals. Binary codes from the outputs of counters 8 and 9 are received respectively at the senior and junior address inputs of the permanent storage device (ROM) 12. Each cell of the ROM that has the working address contains units for all digits from (r +) - th to ( r + 1) is inclusive, where r is equal to the value of the binary number corresponding to the upper half of the address, and 1 is equal to the value of the binary number corresponding to the younger half of the address, and the address width is 2 (ο§2п} +2, where the square brackets denote the operation of extracting the target part of the number. For example, for l, equal to 15, the size of the ROM address is 8, and the ROM cell with address 00110100 records units in all bits from the fourth to the seventh inclusive (,). Most of the ROM addresses are idle, i.e. during device operation at the address inputs ROMs cannot be formed, which speeds up and facilitates the recording of information in ROM.

On the trailing edge of the clock pulse, two processes proceeding in parallel begin: the process of forming at the output of a ROM of single signals that allow writing the analyzed number to the corresponding additional registers 10, and the process of resetting the corresponding triggers 1

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and issuing, under the control of node 2, the next number to be analyzed to the information inputs of register 5. The first process starts under the influence of the zero enable signal at the control input of the ROM and ends with fixation in the corresponding registers 10 of the analyzed number coming from the outputs of the register 5.

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Further operation of the device anat is logical considered.

After the device has completed k cycles, where k is the number of different values of the numbers in the sorting array, in registers 10, starting with the first, the array of numbers sorted in order of increasing will be formed, and after the reset in the kth

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The second process starts at the zero stroke of the last triggers 1 on the output (by the negative difference on the course of the element OR 3, the control inputs are formed) of those triggers 1, on the information (counting) inputs of which there are single signals from the outputs 7 comparisons, as a result of which the triggers 1 corresponding to the numbers sorted in a given clock cycle are reset to the zero state. Then -.

node 2 selects the highest unit, at-20 devices, which are present at the output of flip-flop 1 with the smallest number, block the unit at the outputs of all other flip-flops 1 by generating zero signals by the corresponding elements OR NOT 15 of the node 2. Highlighted by node 2 the highest unit connects the outputs of the corresponding register 6 through the corresponding group of 4 elements And to in30

25

the left potential arriving at the output 14 of the device as a sign End sorting and blocking the supply of clock pulses from the input 13 of the device by locking the element 11.

Next, by the external query, the numbers of the sorted array are output.

To sort the numbers in order of decreasing their values, it is necessary to write the return codes of numbers in registers 6, and read the numbers of the sorted array from the inverse outputs of registers 10.

Claims (2)

1. A device for sorting numbers, containing n registers (n is the number of numbers in the sorting array), n comparison circuits, n groups of 35 AND elements, n triggers, two counters, a result register, AND element, OR element, pulse distributor and address builder, whereby the output of each i-ro register, where, 2, ..., p, is connected to the first group of inputs of the i-th comparison circuit and to the first inputs of the corresponding elements AND the i-th group, outputs of the same name And all groups combined and connected to the informational inputs of the register of the same name the one whose outputs are connected to the inputs of the second group of each comparison circuit, the i-th output of the pulse limiter is connected to the second inputs of the elements of the I-th group, characterized in that, in order to increase the speed of the device, the pulse distributor is the form of the highlight unit of the higher unit, the address maker is made in the form of a permanent storage device, n additional registers are entered into the device, with 50 55 eight Further operation of the device anat is logical considered. After the device has completed k cycles, where k is the number of different values of numbers in the sorting array, in registers 10, starting with the first, an array of numbers sorted in order of increasing will be formed, and after resetting to the kth the tact of the last triggers 1 at the output of the element OR 3 is formed the clock cycle of the last triggers 1 at the output of the OR element 3 is formed by the left-potential device, which arrives at the device output 14 as a sign of the Sorting end and blocks the clock pulses from the device input 13 by locking the AND 11 element. Next, by the external query, the numbers of the sorted array are output.  devices To sort the numbers in order of decreasing their values, it is necessary to write the return codes of numbers in registers 6, and read the numbers of the sorted array from the inverse outputs of registers 10. Invention Formula 1. A device for sorting numbers containing n registers (n is the number of numbers in the sorting array), n comparison circuits, n groups of elements AND, n triggers, two counters, result register, element AND, element OR, pulse distributor and driver addresses, and the output of each i-ro register, where, 2, ..., p, is connected to the first group of inputs of the i-th comparison circuit and with the first inputs of the corresponding elements of the i-th group, the outputs of the elements of the same name of all groups are combined and connected to the same information inputs of the register result The outputs of which are connected to the inputs of the second group of each comparison circuit, the i-th output of the pulse distributor is connected to the second inputs of elements AND of the i-th group, characterized in that, in order to increase the speed of the device, the pulse distributor is executed as a selection node the upper unit, the address driver is made in the form of a permanent storage device, n additional registers are entered into the device, with 9 1310803 Outputs Smaller than all circuits compared to 2n are connected respectively to the input of the first counter, and the output Equal to the comparison circuit is connected to the input input of the corresponding 5th meter and the corresponding input of the counter, the outputs of the sensors are connected to the first and second Ssn, S in (5 (SP по S SP вый в в ни ка ка ад ад ад элем ад ад со со со со со со элем элем элем элем элем элем элем элем элем элем элем элем элем элем г г г г вл вл вл вл вл вл вл вл вл вл вл вл вл вл вл вл вл вл) ) g AND node swarms by groups of address inputs of a persistent storage device, each i-th output of which is connected to the control input of the i-ro additional register, the output of each trigger is connected to the corresponding input of the OR element and to the i-th input of the high-order allocation node pulses of the device are connected to the first input of the element I, the output of which is connected to the control input of the fixed memory device by the control inputs of all the triggers and the result register, the outputs of which are connected to the information inputs each additional register, the output of the element OR is the output of the device's sorting end and is connected to the second input of the element I. 2. The device according to claim 1, characterized in that the node selection of the senior unit contains n-1 elements OR-NOT and p-1 elements AND, and the elements OR-NOT are divided into R subgroups, where R is a whole part of the number ;about  2n - , 75 - 0.5, so that S is a subgroup, 2, .. ,, R includes t, S inputs, where t, I equals R-S + H (57), where P is 0.5-R (R + 3) -n + l, (SP) is a single function, is equal to 1 poi SP is greater than zero and equal to O when SP is less than zero or equal to zero, the first input of the allocation node the highest unit is connected to its first output, ka / adm q-th input of the node, where, 3, ..., p, is connected to the first input (ql) -ro of the AND element of the node, the output of each element OR of the high-order allocation node connected to the second input of the same element AND of the highlight unit of the highest unit, the output of each gth element AND, where, 2 ,, .., n-1, is Cr + 1) -th output of the highlight unit of the high unit, each input in each subgroup u of an OR-NOT node node containing inputs with numbers from Kj-ro to (Kg +) -ro inclusive, where Kg is (R + 1.5-0.5S) S-R + + (S-iP) - (2- (SlP), is connected to the corresponding inputs of the same name and subsequent elements of the OR-NOT node of the division of the higher unit to (K + + Sd 1) -th inclusive, and the output (Kg + Di 5 -1) of the element of the RSHI-HE node of the elder units is connected to the corresponding inputs (Kg +) of th and all subsequent elements AND the allocation node of the senior unit.