SU1325564A1 - Memory - Google Patents

Abstract

The invention relates to computing, in particular, to storing devices for accumulating the 15 NIN results. The purpose of the invention is to increase the speed of the storage device. This goal is achieved by providing a multichannel accumulating adder combining the summation, recording and reading of current and previous decisive statistics in the same RAM cells for the same resolution elements for h observation periods in real time. The device contains registers 1-4, element 5, synchronizer 6, adder 7, counters 8, 9, memory blocks 10, 11, trigger 12, element OR 13, delay element 14. 3 il. 17

Description

The invention relates to computing, in particular, to storage devices for accumulating results.

The invention is an increase in the speed of a memory device,

Fig. 1 shows a functional diagram of a storage device; FIG. 2 is a functional diagram of a synchronizer; FIGS. 3 are diagrams depicting memory operation.

The memory device (FIG. 1) contains registers 1-4, AND 5, synchronizer 6, adder 7, counters 8 and 9, blocks 10 and P memory 5 trigger 12, OR 13 and delay element 14. The input of register 1 is the first input 15 of the device, the input of the synchronizer 6 by the second input 6, and the output of the element 13 by the output I7 of the device.

The synchronizer 6 contains a generator 18 clock pulses, counters 19 and 20 and the element And 21,

In the proposed storage device, the outputs of the synchronizer 6 are connected to the inputs of registers 3 and 4,

ten

/,

thirty

40

counters 8 and 9, -5locks 10 and 11 of memory, trigger 12, element 5 and delay element 14. The output of the delay element 14 is connected to the inputs of registers 1 and .2, counters 8 and 9s of blocks 10 and 1} of memory. Register 1, adder 7 and register 2 are connected in series, the outputs of trigger 12 are connected to the inputs of registers 3 and 4, blocks 10 and 11. memory meters and counters 8 and 9. The output of the register 2 is connected to the information. the inputs of blocks 10 and 11 of memory. Counter 8, memory block 10, and register 3 are connected in series. Also, a counter 9, a memory unit P and a register 4, Element OR 13 are connected in series with AND 5 and registers 3 and 4, AND 5 output is connected to the input of adder 7, Input 15 of register 1 is the first memory input, second the input 16 of which is the input of the synchronizer 50 ntsator 6, and the output 17 is the output code of the IPI 13,

In the synchronizer 6, the generator 18 clock pulses, the counter 19 and

The second inputs are counters 19 and 2.0, the first 23, second 24, and third 25 outputs of synchronizer 6, respectively, are output of element 21, counter output, 20, and first counter output 19, Figures 3 denote pulses 25-30,

The storage device (memory) works as follows.

The current value of statistics in the form of a K-bit digital parallel binary code in series for each j-ro element of N elements g-j is fed to the input 15 (memory). neither (for example, in range, in time and m, n,), where ,, “,, ,, N.

The signal arriving at the input 16 of the charger permits the formation of pulses 27, 29 and 30 (Fig. 3) at the output of synchronizer 6, Calculation of the decision statistics, 2D. -P

., (,: - (.

sticks b 2-5 reduced to synchronous -1;

accumulation of statistics x: for n observation periods (, .o ,, n),

"(. In the i-M observation period in the memory on. I,

Copied statistics Si 2 x for all.

of i resolution elements. Trigger 12

 is in one of two of its stable states, such as zero. In this case, at its direct output

tin

there is a logic level O and at the inverse level a logical level I. At the end of the i-th observation period, the counting input of the trigger 12 alternates 35 and the i + 1th pulse 29 (FIG. 3) -c synchronizer 6, indicating the beginning 1 + 1 th observation period. Counters 8 and 9 are switched to the initial state code setting mode, and trigger 12 changes its steady state and a logic level l appears at its direct output.

45

and on the inverse - the level of the logical o,

The signal, logical 1 from the immediate output of trigger 12, enters the information input of the 1st least significant bit of counter 9 and the information inputs 1-1 of the most significant bits of the counter 8, switches the memory block 10 into the information recording mode, enters the input of the register 3, prohibits recording and issuing information from it,

The logical signal with the inverter counter 20 are connected in series, the output of the trigger 12 is fed to

The inputs of the element And 21 are connected to the you-information input of the 1st junior

generator clock 18 clock pulse-discharge counter 8 and information

owls and counter 19. The input 22 sync inputs 1-1 old bits of the counter

low 6 are the combined w-9, puts the memory block 11 in the mode

The second inputs are counters 19 and 2.0, the first 23, second 24, and third 25 outputs of synchronizer 6, respectively, are output of element 21, counter output, 20, and first counter output 19, Figures 3 denote pulses 25-30,

The storage device (memory) works as follows.

The current value of statistics in the form of a K-bit digital parallel binary code in series for each j-ro element of N resolution elements (for example, in range, in time and m, n,) where ,, “,, n.

The signal received at the input 16 of the memory, allows the formation of pulses 27, 29 and 30 (Fig. 3) at the output of the synchronizer 6, Calculation of the decisive statistics -. -P

., (,: - (.

sticks b 2-5 reduced to synchronous -1;

accumulation of statistics x: for n observation periods (, .o ,, n),

In the i-M period of observation in the memory on. I,

Copied statistics Si 2 x for all.

of i resolution elements. The trigger 12 is in one of its two stable states, for example, in zero. In this case, at its direct output

40

50

tin

there is a logic level O and at the inverse level a logical level I. At the end of the i-th observation period, the counting input of the trigger 12 alternates 35 and the i + 1th pulse 29 (FIG. 3) -c synchronizer 6, indicating the beginning 1 + 1 th observation period. Counters 8 and 9 are switched to the initial state code setting mode, and trigger 12 changes its steady state and a logic level l appears at its direct output.

and on the inverse - the level of the logical o,

The signal, logical 1 from the immediate output of trigger 12, enters the information input of the 1st least significant bit of counter 9 and the information inputs 1-1 of the most significant bits of the counter 8, switches the memory block 10 into the information recording mode, enters the input of the register 3, prohibits recording and issuing information from it,

The logical signal O with inverse information, arrives at the input of register 4 and allows recording and issuing information from it.

In the presence of i + 1-gs pulse 29 (Fig. 3) synchronization, the counter 8 g is set to its (2-1) initial state, and the counter 9 to its first initial state. The binary 1-bit code of the rutchers 8 and 9 defines the addresses of the memory cells in the memory blocks 10 and 11, respectively. At the end of the pulse 29, the counters 8 and 9 are switched to the summation mode of the pulses 28 coming from the delay element 14 (FIG. 3) to their counting inputs. By the delay element 14, the leading and trailing edges of the pulses 27 (FIG. 3) produced by the synchronizer 6 are delayed by the amount needed to transfer information from memory block 10 or 11 to register 3 or 4.

In the i + 1 st period of observation, the computation of statistics S S + x | for each of the j elements of the time resolution, it follows the principle of the stream method of information processing, in which the various nodes of the circuit perform operations corresponding to different (adjacent) time resolution intervals. The time resolution interval is determined by the pulse period T at time 27 (Fig. 3). Since the same pulses 28 arrive at the counting inputs of counters 8 and 9 (Fig. 3), the V-e state of the counter 8 and the Zj-e state of the counter 9 connect the ratio, - 2.

Before the occurrence of j-x pulses 27 and 28 at the outputs of synchronizer 6 and delay element 14 (Fig. 3), the information input of register 1 receives statistics x 1 j-ro of the time resolution element. In adder 7, the X + statistics coming from the register 1 output is accumulated with the previously accumulated value of the statistics from the register 4 output through the OR 13 and AND 5 elements. In memory block 10, the sample U.-2 is resolved -th cell of memory and record of statistics S, coming to its information input from the output of register 2, to this cell of memory. In block 11 of the memory, the sampling of the Z ,, -th cell of the memory and the issuance of statistics on its output from this memory cell are allowed.

 ,

325564.

When the j-ro pulse 27 (Fig. 3) arrives at the clock input of the register 4, the value S written to its information input from the output of the memory block 11 is written to it. Register 3 does not write information.

When the j-ro pulse 28 (Fig. 3) arrives at the clock inputs of registers I and 2, memory block 10 and counting inputs of counters 8 and 9, the following occurs. Memory blocks 10 and 11 prohibit the sampling of memory cells. The register value is written to the register.

tiki X. coming to his infor

SM make input. Value statistics

Sl from the output of the adder 7 writes off to the register 2, Counter 8 enters the state and determines the address at the memory cell of the memory block 10. Counter 9 goes to the Z.-e state and determines the address Z J of the + lth memory cell of the memory block 11.

When the j-ro pulse 28 (Fig. 3) disappears, the information input of the register 1 receives the statistics x j + 1-th element of the time resolution. In adder 7, the statistics xt, coming from the output of register 1, is summed with the previously accumulated 1 value of statistics S, coming from the output of register 4 through the elements OR 13 and 5. In memory block 10, the sample Y is allowed. 1st. Cells, memory and recording statistics S,

S. Arriving at its information input from the output of register 2. In block 11 of memory, sampling 2, - + the 1st memory cell is allowed and issuing statistics S from this memory cell.

- When j + 1-th pulse 27 (Fig. 3) arrives at the clock input of register 4, the value S written to its information input from the output of memory block 11 is written to it.

Register 3 does not write information.

When j + 1-th pulse 28 (Fig. 3) is received at the clock inputs of registers 1 and 2, memory blocks IO and 11, and counting inputs of counters 8 and 9, the following occurs. Register 1 records the value of the statistics x. Coming in on its information input. The statistics value S |, S, + x, from the output of the adder 7 is written to the register 2. Counter 8 goes to V), the e and the state determines the address of the W of the memory cell of the memory 10. Counter 9 enters the state and determines the address L. j + 2-ft of the memory cell of the memory 11, When j + 1-th pulse 28 disappears (Fig. 3), the statistics input x is fed to the information input of the register I. j of the 4.2 element of time resolution. In adder 7, the statistics x., Coming from the output of register 1, is summed up with the previously obtained statistics of the statistics coming from the output of register 4 through the elements OR 13 and AND 5. In memory block 10, a sample of the SAR cell is resolved and record statistics

S ,, S + X-, incoming on his infor

the memory input from the output of register 2. In block 11 of memory, the sampling of Z j + the 2nd memory cell and the issuance of

}

:) 2

statistics s. on his way out of this cell of memory.

Thus, the statistics s extracted from the j-th memory cell of the memory block J is summed with the statistics xj + n is written into the j-th cell of the memory block 10. The capacity of the counters is 8 and 9 and the number of pulses is 27 and 28 is greater than N + 1.

Upon receipt of the i + 2 nd pulse 2.9 (Fig. 3), the memory block 10 is transferred to the information reading mode from it, the memory block 1 is transferred to the information recording mode in it, the counter 8 is set to the initial

9 setting

 state 5 the counter is reset to the initial 7 2-1-6 state, recording and issuing information from register 3 is permitted and recording and transmitting information from register 4 is prohibited,

When i + 2 nd pulse disappears 29 40 (FIG. 3), the statistics s | 51ch1 5 l for all of the N elements of time resolution, similar to the accumulation of statistics S

)

1 + 1

A storage device containing the first register, the output of which is connected to the first input of the summator, the output of the adder is connected to the informational input of the second register

For n observation periods, a 45 memory block occurs, the third register.

accumulation of decisive stats S.

  X with alternate switching i i

write and read channels. The capacity of the J-X memory cells of the memory blocks 10 and 11 is larger than 2 n, and the total capacity of the memory blocks 10 and P memory is larger,

than

p.

the synchronizer, the clock input of the first memory block is connected to the clock inputs of the first and second register, which differs in that

50 in order to increase the speed of the remembering device, in it, the first and second counters are inserted, the second memory block, the output of which is connected to the information input four

At the end of the cycle, out of n observation periods, the next cycle starts out of n observation periods. Its beginning is determined by the appearance of the 1st pulse 29 (Fig. 3). During the 1st observation period, the synchronizer 6 generates

the impulse 30 (fig. 3) of the logical o level, which enters the input of element AND 5 and prohibits the passage of the decisive statistics SJ accumulated in the previous observation cycle, from the output of element a OR 13 through element 5 to the input of adder 7. Therefore, in 1- The observation period in the memory cells of block 10 or AND memory (depending on the state of trigger 12) is recorded statistics, where x is the current value of the statistics in the first period of observations.

Synchronizer 6 (Fig. 2) works

in the following way.

The clock pulse generator 18 produces pulses 26 (FIG. 3) with a repetition period T. In the absence of a signal at its input 22 counters 19 and. 20 are in the zero state. At the direct output 25 of the zero state of the counter 19 is present

The logical level is 1, and at its inverse output is the logic level O, which prohibits the passage of pulses 26 through element 21 to output 23. At the inverse output 24 of the zero state of counter 20, there is a logical level 1.

When a signal arrives at the input 22, the synchronizer 6 begins to generate pulses 27, 29 and 30 at its outputs 23, 25 and 24, respectively (Fig. 3). The capacity of the counter 19 is greater than N + 1, and the capacity of the counter 20 is equal to p.

Claims (1)

Invention Formula A memory device containing the first register, the output of which is connected to the first input of the adder, the output of the adder is connected to the information input of the second register, the synchronizer, the clock input of the first memory block is connected to the clock inputs of the first and second registers, which in order to increase the speed of the memory device, the first and second counters are entered into it, the second memory block whose output is connected to the information input of the fourth register whose output is connected to the first input of the OR element, the output of the OR element is connected to the first input of the element And, the output of which is connected to the delay element, the input of which is connected to the first output cHHxpoHHsatopa and the clock inputs of the third and fourth registers, and the output is connected to the clock inputs of the first and second counters and inputs of the first and second counters, the second output of the synchronizer is connected to the second input of the element I, the output of which is connected to the second input of the adder, the third output of the synchronizer is connected to the control inputs of the first and second counters and the counting input of the trigger, the direct output of which is connected to the serial information the input of the second counter and the parallel information inputs of the first counter, and the inverse output with a serial information input of the first. th counter and parallel information input of the second counter, etc. 18 H 22 ten 2556A My TpHrrejia output is connected to the third-register reset input and control input of the first memory block, and the inverse trigger output to the fourth register reset input and control input of the second memory block, the first and second memory address connectors are connected to the first and second outputs The second counter, respectively, the first input of the second memory block is connected to the output of the second register, the output of the third register is connected to the second input of the OR element, the output of which is the information output of the memory device Discount input of the first register is a data input of the memory, and input synchronizer rtrobiruyuschy - strobiruyupschm input of the memory device. 15 20 21 23 25, FIG 2 --four 24 " 1325564 G, "JMJllltUlJllUlIUlMJULMMM .rJlMMllJLlJlJL" JUlJimJUUUJLJlJlJlJL  n-1 n 1 Z {, JL LYALYAL G fpu3.3