SU1267436A1 - Device for determining complement of set - Google Patents

Description

The invention relates to computing and can be used in data bank management systems.

The aim of the invention is to enhance the functionality by providing a comparison operation for the elements of a plurality.

The drawing shows a diagram of the device.

The device contains a block of 1 memory, a counter 2, the elements OF 1, 4, the element OR 5, groups 6, 7 of the elements AND. registers 8, 9, counter 10, circuits 11, 12, comparisons, triggers 13, 14, clock generator 15, pulse distributor 16, address input 17, information input 18, start input 19, information output 20, termination 21 output 21 and 12 outputs a signal when the matching codes match. A group of 6 elements AND opens with the presence of signals simultaneously on its three inputs. When an address is fed to the address input of block 1, this block outputs the contents of the corresponding memory cell to its output and maintains it until a new a, a cres

Let P be a universal set, and A a set that is a subset of P. Then the complement of set A is the set of elements from set P that do not belong to set A. The sets that are subsets of set P are stored in memory block 1, and the elements of these sets are represented by Isel codes. Elements of each set, with in successive memory cells. The last element of each set is marked with a unit in the last category. All other elements are marked with a zero. The elements of the universal set are encoded with integers from 1 to N, where N is the number of elements in the universal set. In all sets, the same element is represented by the same code.

The device works as follows.

When the power is turned on, the distributor 16 pulses are reset (with no signal on any of its outputs), the generator 15 sets up 67A362

c in a locked state, and the memory information register and counter 10 are zeroed (not shown). At the entrance. DU 18 to register 9 zagsssyaetsya code

5 numbers N + I, and at input 7 into register 8, hell is entered, res of the first element of the set A. The device is ready for operation.

The device is put into operation by a pulse from input 19,

10 According to this pulse, the trigger 13 is set to one state, as a result of which the elements 3 and 4 are opened and the generator 15 is started. The distributor 16 starts

t5 distribute the pulses to the control points of the device. By the pulse from the first output of the distributor 16, the trigger 14 is set to one, and the contents of the counter 10 are increased by one, i.e. it forms the code of the first (hereinafter the next) element of the set. At the output of memory block 1, there is a zero code (including 25 and at the output of the last bit). Therefore, the circuit 11 does not produce a signal. By the pulse from the second output of the distributor 16, the trigger 13 is zeroed, and the counter 2 of register 8 receives the address of the first element of set A. By the pulse from the third output of the distributor 16, the address of the first (hereinafter next) element of set A from counter 2 is fed to memory block 1, as a result of which at its outputs appears the code of the first element of set A,

Suppose that the set A contains not one but several elements. Therefore, the signal at the output of the last bit of block 1 is absent. If the code of the first (hereinafter successive) element of the set A is equal to the code of the first (further next) element of the set P, then the circuit 11 outputs a signal on which the trigger 14 is zeroed. The pulse from the fourth output of the distributor 16, the contents of the counter 2 is increased by one {i.e. the address of the next element of set A) is generated. And the 6 elements of And does not open, since there is no signal from the output of the last bit of block I due to the fact that all elements of set A have not yet been read and have not been compared with the first (hereinafter) element of set P.

3

After this, a pulse appears again at the first outlet of the distributor 16, but since the element I 3 is closed, no action is taken on it. The impulse from the second output of the distributor 16 also does not pass through the closed element 4 And the impulse from the third output of the distributor 16 from block I reads the code of the next element of set A, after which it is compared with the code of the first (hereinafter next) element of set P by circuit 11 From the fourth output of the distributor 16, the counter 2 forms the address of the next element of set A. Thus, all the elements of set A are read sequentially from block I and compared with the first (hereinafter next) element of m R.

Let from block 1 the last element of set A. is read. At the same time, a signal appears at the output of the last bit of block 1, which contributes to the discovery of group 6 of elements I. With the same signal, elements OF and 4. If the first (hereinafter) element of the set P coincided with one of the elements of the set A, then the trigger 14 is reset. Therefore, according to the impulse from the fourth outlet of the distributor 16, the group of 6 elements I does not open. If trigger 14 remains in a single state, i.e. the first (hereinafter, the next) element of the set P does not belong to the set A, then by this impulse the group 6 of the elements I opens and the code of the first (hereinafter the next) element of the set P of the counter 10 enters the output 20 of the device as the code of the first (later the next ) an element of the set P.

Then an impulse reappears. at the first output of the distributor 16, according to which the code of the next element of the set P is generated in the counter 10, and the trigger 14 is set to the initial (single) state. The pulse from the second output of the distributor 16 confirms the zero state of the flip-flop 13 and the address 2 of the first element of set A. is received in the counter. In the following, the device works as described above until the next pulse from the first output of the distributor 16 counts the contents of the counter 10

674364

matches the contents of register 9. If a match occurs, circuit 12 outputs a signal by which the device is reset (i.e.

- the distributor 16 is reset, the generator 15 is in the locked state, and the counter 10 and the information register of the block I are zeroed out). In addition, it passes to the output 21 of the device FQ of the property, signaling the end of the formation of the set B.

After writing to the register 8 of the address of the new set A, the device starts up again with a pulse

., at input 19 to determine the set in A.

Claims (1)

Invention Formula A device for determining the complement of a set containing a first register, a memory block, a first counter, two AND elements, an OR element, and two groups of AND elements, the outputs of the AND elements of the first group being 25 nztc information output of the device, characterized in that expanding the functionality by providing a comparison operation of the elements of the sets, a second register, a second counter, two comparison circuits, two triggers, a clock generator and a pulse distributor, an information input to Expensively connected to the output of the clock generator, the address input of the device is connected to the input of the first register, the output of which is connected to the information input of the first counter, the outputs of the bits of which are connected respectively to the first inputs of elements AND of the second group, the outputs of which are connected to the address input of the memory block, the outputs of the bits of which, except the last bit, are connected to the first input of the first comparison circuit, the second input of which, the first input of the second comparison circuit and the first inputs of the AND elements of the first group connected to the outputs of bits of the second 50 counter, the second input of the second comparison circuit is connected to the output of the second register, the input of which is the information input of the device, the start input of which is connected to 55 with a single input of the first trigger and an input of the start of the clock pulse generator, whose stop input, the installation inputs of the memory unit. the pulse distributor, the second counter and the output of the device termination feature are connected to the output of the second comparison circuit, the counting input of the second counter and the single input of the second trigger are connected to the output of the first element AND, the first input of which is the first input of the second element AND connected to the output of the element OR, the first input which is connected to the output of the first trigger, the zero input of which is connected to the output of the second element I and to the recording input of the first counter, the first and second outputs of the distributor 67436ft owls are connected respectively with the first inputs of the first and second element And, the third output is connected to the second inputs of the elements And the second J group, the fourth output of the pulse distributor is connected to the counting input of the second counter and the second inputs of the elements AND of the first group, the third inputs of which are connected to the output of the second trigger, the zero input of which is connected to the output of the first circuit; comparison, the output of the last bit of the memory block is connected to the fourth inputs of the elements of the first group 15 by the second input of the OR element.