SU1249529A1 - Device for simulating network topology - Google Patents

Abstract

The invention relates to computing and can be used in the construction of specialized computing devices for parallel modeling of various systems having a network structure with regard to the control of the Correctness of the topology of the network under study. The purpose of the invention is to increase the reliability of work. For this, the eighth, ninth, tenth elements of OR and the control unit are additionally introduced into the network topology modeling device, the latter containing an address counter, the first and second counters, the overflow decoder, the first and second decoders, the comparison element, the starting node address register nets, first and second triggers, first through fifth. elements AND, element OR. the element is NOT, the element of delay and the element of indication. i SL C sd hO

Description

The invention relates to computing.

The purpose of the invention is to increase the reliability of work.

FIG. 1 shows a block diagram of the device; in fig. 2 - block diagram of the control unit; in fig. 3 is an example of a fragment; networks; in fig. 4 shows an example of the presentation of network topology information in the form of lists.

The device contains a block of 1 memory of addresses of the initial nodes of network branches, a block of 2 memory of addresses of end nodes of network branches, a block of 3 memory of addresses of output branches of network nodes, a block of 4 memory of addresses of incoming branches of network nodes, block 5 of memory of addresses of the first the outgoing branch of the network nodes, block 6 of the memory of the addresses of the first incoming branch of the network nodes, the register 7 of the address of the outgoing branch, the register 8 of the address of the incoming branch, the register 9 of the address of the end-iHoro branch node, the register 10 of the final network node, triggers 11 and 12, decoders 13 and 14, decoder 15 code comparison, lines 16 and 17 back rzhki, OR elements 18 - 27, AND gates 28 - 33, NOT element 34, a control unit 35.

I.

The inputs of the device are poles 36 and 37, connected respectively to the address inputs of blocks 1 and 2 of the memory of the start node and the end node of the network branch.

The input poles 38 and 39 are supplied respectively to a series of pulses GI1 and GI2, shifted one relative to the other. Pole 40 is designed to receive a Start signal, which starts the simulation of a given network topology. The outputs of the device are poles 41 and 42, connected respectively to the outputs of registers 7 and 8 of the outgoing and incoming branches. Pole 43 is designed to provide a signal to end the simulation of a given network topology. Poles 44-4 are intended to communicate with branch models.

Blocks 1–6 based on lists contain information about the topology of the simulated network. As a result, the cell number of the first outgoing branch is stored in the cells of the memory block 5 at the node number address. If the node has no output branches, then at

The control unit (Fig. 2) contains the triggers 47 and 48, the counter 49 of the address, the counters 50 and 51, the decoder 52 overflow, the decoders 53 and 54 consisted of 55 node numbers. In eiky is stored information jC, the element 55 comparison, the element es.

you AND 56 - 60, element OR 61, ele-. Similarly, in the cells of block 6, the memory NOT 62, the delay element 63, at the node number address, is stored

five

0

five

0

five

0

five

50

register 64 addresses the initial network node, the element 65 display.

Input pole 66 is designed to receive the Start Control signal. Input pole 67 is a clock pulse input. Input pole 68 is connected to the output of memory block 5 of the first input branch. The input pole 69 is connected to the output of the memory block 6 of the first input branch. Pole 70 is the output of the address counter and is connected to the inputs of the elements OR 19, OR-25, OR 27. The output pole 71 is designed to transmit a read signal to memory blocks 5 and 6, connected to the inputs of the elements OR 18, OR 26. The output pole 72 is connected to the input of the register 10 and serves to output a write signal to the register 10 of the end node of the network. The address counter 49 is a binary counter whose capacity corresponds to the number of cells in blocks 5 and 6 of the memory. The address counter is designed to sequentially miscalculate the addresses of memory blocks. Overflow decoder 52 serves to highlight the overflow signal of an address counter indicating the end of network topology monitoring. Counters 50 and 51 are identical and have a capacity equal to one. The second counter bits, which are the overflow bits, are the outputs of the counters.

The decoders 53 and 54 states are designed to compare the codes arriving at them with the code combination of the state of the OS specified in the scheme permanently.

Comparison element 55 is a one-bit comparison circuit for performing EXCLUSIVE OR. Register 64 is a register with parallel reception of information.

Consider the operation of the device when monitoring information. On the topology of the simulated network.

Blocks 1–6 based on lists contain information about the topology of the simulated network. As a result, the cell number of the first outgoing branch is stored in the cells of the memory block 5 at the node number address. If the node has no output branches, then at

55 node numbers. In her storehouse of information es.

3

code of the first incoming branch. If

Since this node has no incoming branches, informationalIl is stored in the corresponding cell.

Previously, the counters 49-51 of the resistor are reset to the initial state; triggers 47 and 48 are returned to the zero state. The start control signal from the input pole 66 is fed to the input of the trigger 47. The trigger 47 is set to one and allows the clock pulses from the pole 67 to pass through the element 56.

The first clock pulse passing through the element AND 56 is fed to the input of the delay element 63, as well as to the input of the address counter 49 and the inputs of the OR 18 and OR 26. After the first clock pulse arrives, the address counter 49 contains the address code of the first network node which enters through the elements OR 19 and OR 25 to the address inputs of memory blocks 5 and 6. The result of the submission of the address code of the first node from counter 49 to memory blocks 5 and 6 is the information in the lists of the first incoming and outgoing branches.

At the same time, at the outputs of the elements OR 18 and IL 26, sampling resolution signals are outputted, which are fed to the read inputs of memory blocks 5 and 6. The read information from memory blocks 5 and 6 is fed to the inputs of the decoder 53 and 54, respectively. The depifiers 53 and 54 compare the read information with the code state x.

In that, if the read information is not equal to the state of the ES, the outputs of the decoders 53 and 54 produce resolution signals, which determine the presence of output and input branches for the node in question, respectively. .

The signals from the outputs of the decoders 53 and 54 are received respectively at the inputs of the elements And 59, 60 and together at the inputs of the element 55 of the comparison.

Comparison element 55 works hardly.

If two permitting or prohibiting signals arrive at its input at the same time, a ban is generated at the output of the comparison element. This case corresponds to two options: when the node in question has input and output branches,

0

five

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and he

five

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five

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five

is an intermediate network node; when at a given node address, blocks 5 and 6 of the memory contain information that determines the absence of a node in the network with this number. In both cases of this case, the comparison element 55 prohibits the operation of the elements 59 and 60.

If one permitting signal and one inhibitory signal are passed to the input of the comparison element 55, then at such combinations, the element 55 at the output allows the signal

This case also has two options.

When the enabling signal comes from the decoder 53, and the inhibiting signal comes from the decoder 54. This corresponds to the fact that the node under consideration has outgoing branches and no incoming, i.e. it is the starting node of the network. The permissive signal from the output of the comparison element 55 is fed to the inputs of the And 59 and 60 elements, on the second inputs of which there is a resolution from the decoder 53 and; the prohibition from the decoder 54, respectively; Since the counter 49 of the address is not overflowed and the output of the decoder 52 connected to the inputs of the element 57 and the element NOT 62 is missing. There is a ban on the input of the element 57 and the input of the element 58 passes the element 62 signal. As a result, the delayed clock pulse passes through the elements And 58, And 59 and is fed to the input of the counter 50 and to the input of the register record 64 of the initial network node. When a recording signal arrives in the register 64, the number of the initial network node is recorded, which is fed to the information input of the register from the output of the counter 49 of the address. The counter 50 calculates the delayed clock pulse, which corresponds to one found initial network node.

In the second variant, when there is a permitting signal from the output of the decoder of torus 54 and a inhibitory signal from the decoder 53. This corresponds to the fact that the node in question has input branches and there are no output, i.e. he is the end node

55 networks. In this variant, the delay pulse passes through the element 60, where there is a resolution from the output of the decoder 54. From the output of the element 60 the pulse arrives at the input of the counter 51 and through the pole 72 to the input of the register 10 of the end node of the network. When a recording signal arrives in the register 10, the number of the end node of the network is recorded, through the OR element 27 it enters the information input of the register from the output of the counter 49 of the address. Accordingly, the counter 31 calculates a delayed clock pulse, which is determined by one found end node of the network.

At the next clock, the next (second) clock pulse passes to pole 67, which is fed to the counting input of the address counter 49. The address counter increases its content by one. This corresponds to the formation of the address of the next node for which the presence of incoming and outgoing branches is examined. In the case of determining the second initial or second end node of the network, an overflow signal is output at the output of the counters 50 or 51, respectively. The overflow signal passes through the OR element 61 and sets the trigger 48 to one state, which corresponds to the incorrectness of the network. The display element 65, which is connected to the output of the trigger 48, in this case displays information about the incorrectness of the network. Thus, the polling of the addresses of the network node numbers is carried out, until all cells of blocks 5 and 6 of memory have been reviewed. This corresponds to the fact that the counter 49 of the address will contain the overflow code ..-

The decoder 52 decrypts the overflow state of the address counter and generates a resolution signal that is fed to the input of the element 57. The signal from the output of the decoder 52 also enters through the element 62 to the element 58 and prohibits the passage of the delayed clock pulse from the output of the element 63 delay . In this case, the delayed clock pulse passes through AND 58 and sets trigger 47 to the zero state. As a result, the zero state of the trigger 47 prohibits the passage of the clock pulses through the element 56 and the operation of the monitoring device ends there. If the network is correct, then codes 64 and 10 store the codes of the starting and ending nodes of the network, respectively. If the network is incorrect, the trigger 48 is in the single state and the display element indicates the alarm state of the device. /

The device provides the arrival of the necessary preset signals, which in FIG. 1, 2 are not shown.

The solution to the monitoring task is to verify the correctness of the specified network topology, which is stored in six memory blocks of the device. In this case, opscs in the topology can be allowed both when writing information in the memory blocks, or if the operator has incorrectly specified the network topology.

Monitoring information about the topology makes it possible to eliminate the incorrect switching of the decisive elements in the process of modeling the network under study.

Claims (1)

Invention Formula A device for modeling the network topology - containing the memory block of addresses of the first outgoing branch of network nodes, the block of addresses of the first incoming branch of the network nodes, the address register of the outgoing branch, the address register of the incoming branch, outputs of the outgoing address registers and input the main branches are connected to the address inputs of the memory block of addresses of the outgoing branches of network nodes and the memory block of addresses of the incoming branches of network nodes, the memory blocks of addresses of the start and end nodes of the network branches, the address registers of the end node of the branch and the network node, the first and second triggers, the first and second decoders, code comparison decoder, the first and second delay lines, seven OR elements, six AND elements and the NOT element, the address input of the block of addresses of the initial nodes of the network legs being the task input addresses of the initial branch of the device, the read input of the memory block of addresses of the initial nodes of the network branches is the starting input of the device and connected to the input of the first delay line and the first input of the first OR element, the address input of the memory of the addresses of the end nodes is network twist is the endpoint address input the device branch, the interrupt input of the memory of the addresses of the end nodes of the network branches is the interrupt input of the device and connected to the input of the second delay line and the single input of the first trigger; the first input of the first element I is connected to the input of the element. It is NOT and is the input of receiving the signals of the end of the operation of the models of the device branches, un-. The standard input of the address register of the end node of the branch is connected to the output of the memory block of the addresses of the end nodes of the network branches, the input of the resolution of the record of the register of the address of the end node of the branch is connected to the output of the second delay lia, the output register of the address of the end network node is connected Compared to none of the codes, the second input of which is connected to the output of the register of the address of the final branch and the first input of the second element SH, the second input of the second element OR is connected to the output of the memory block of the addresses of the initial nodes of the network branches, and the output - with the address input of the memory block of addresses of the first output branch of network nodes, the read input of which is connected to the output of the third OR element, the first input of which is connected to the output of the first delay line, the outputs of the memory of addresses of output branches and the first output branch network nodes are connected to the inputs of the fourth OR element, the output of which is connected to the information input of the address register of the output branch, the output of which is the output of the address of the input branch of the device and connected to the input of the first decoder, the output of which connected to zero, the second trigger input and the first input of the fifth element OR, the second input of which is connected to the output of the element NOT and the first input of the sixth element OR, the output of the fifth element OR is the output of the turn on patterns of the device branches - the video is the output of the address of the input branch of the device and is connected to the input of the second decoder, the output of which is connected to the second input of the third OR element, the second inputs of the first and sixth SH and the first input of the second And, which is connected to the output of the code comparison decoder, the output of the first element I is the output of the device end signal, the output of the first element OR is connected to the single input of the second tripper, the output of which is connected to the first inputs of the third and fourth elements and the output of the first trigger is connected to the first the inputs of the fifth and sixth elements And, the second inputs of the third and fifth elements And are connected with the first. The second clock inputs of the fourth and sixth elements I are connected to the second clock input of the device, the outputs of the third and fourth elements I are connected respectively to the read input of the block, the address memory of the output branches of the network nodes and the input; branch, the output of the sixth element And is connected to the second input of the first element And, the output of which is connected to the read input of the memory block of addresses of the incoming branches of network nodes, the output of which is connected to the first input of the seventh OR element, the second input of which is connected to the output of the memory block of addresses of the first incoming branch of network nodes, the output of the seventh element OR is connected to the information input of the address register of the incoming branch whose recording input resolution is connected to the output of the fifth element AND, output The sixth OR element is connected to the zero input of the first trigger, characterized in that, G of the confidence increasing circuit, the eighth, ninth, tenth OR elements and the control unit i containing the address counter, the first and second counters, overflow decoder, first and second decoders, comparison match, address register of the initial network node, first and second triggers, first to fifth AND elements, OR element, NOT element, delay element and display element, single input of the first block trigger the control is the control start input of the device, the unit output of the first trigger of the control unit is connected to the first input of the first element I of the control unit, the second input of which is connected to the second input of the device clock, the output of the first the control unit I is connected to the inputs of the address counter and the delay element of the control unit with the third input of the third OR element and the first input of the eighth OR element, the output of which is connected to the read input of the memory of the addresses of the incoming branches of network nodes. connected to the information input of the register of the initial network node of the control unit, with the input of the overflow decoder of the control unit, with the third input of the second OR element, with the first input of the ninth OR element, with the first input of the ILI element whose output is connected to the information input of the address register of the network end node, the overflow decoder output of the control unit is connected to the first input of the second AND element and connected to the first input of the third AND element, the output of the delay element is connected to the second inputs The second and third elements of the control unit And, the output of the second element and the control unit is connected to the zero input of the first trigger of the control unit, the output of the third element and the control unit is connected to the first inputs fourth and fifth elements and a control unit, the second inputs of which are combined and connected to ryhodom comparing elements, the outputs of the first and second DEPP € fratorov control unit connected to respective inputs -ele-; The control unit is connected to the third inputs of the fourth and fifth control units AND, respectively, the output of the memory block of addresses of the first output branch of network nodes is connected to the input of the first decoder of the control block, the output of the memory block of addresses of the first incoming branch of network nodes is connected to the input the second decoder of the control unit, the output of the first element And the control unit is connected to the input of the first counter of the control unit and the input of the resolution of writing the address register of the end node of the network, and the output of the fourth element And the control unit connected to the input and output permit register register of the initial network node and the input of the second counter of the counter control unit, the output of which is connected to the first input of the OR control unit, the second input of which is connected to the output of the first counter of the control unit, the output of the OR control unit is connected to the unit input of the second flip-flop of this block, the unit output of which is connected to the input of the indication element, the output of the ninth element OR is connected to the address input of the memory block of addresses the input of the network node branches, the output of the second line the delay is connected to the second input of the eighth OR element, the output of the memory block of addresses of the network node end nodes is connected to the second input of the ninth OR element, the second to the tenth input | The OR element is the input for specifying the address of the end node of the device network. 67 iaA bA cB dB fC 4.aX bX cb df fX Fig4