SU559395A1 - Counter with a constant number of units in the code - Google Patents

Description

one

The invention relates to the field of electrical discrete devices of automation systems, remote control and computing.

There are counters with a constant number of units in the region that contain shift registers, triggers and logic elements Ш.

The disadvantage of this device is a large amount of equipment.

The closest technical solution to the present invention is a device comprising a control unit, a shift register, AND elements, an OR element and a NOT element, the device input being connected to the control inputs (to + 1) -th shift register bits, the outputs from (to +1) -th of (71-1) -th bit of which is connected to the corresponding inputs of the control unit, the output of which is connected to the first input of the first and second elements Nick of the input of the element NO, the output of which is connected to the first input of the third element And, the second input which is connected to the output of the h-th sp and the shift register, the output of the third element

And it is connected to the first input of the element OR whose second input is connected to the output of the second element AND, the second input of which is connected to the output of the k-th bit of the shift register.

The disadvantage of such a device is the presence of the log states of the device and the redundancy of its equipment.

The aim of the invention is to increase the reliability of the device.

This is achieved by the fact that the device input is connected to the second input of the first element AND, the output of which is connected to the control Inputs from the 1st to k-th digit of the shift register, the output of the -th digit of which is connected to the input 1-gx) shift register bit, element OR output is connected to the input (to + 1) of the shift register bit.

The drawing is a schematic diagram of the proposed device.

It consists of a shift register 1, a 2-control block, AND 3, 4, and 5 elements, an OR 6 element, a NOT 7 element. The AND 4 and 5 elements and an 11/111 element are combined into a block 8.

The device works as follows.

Before starting work, register 1 is written to any binary sequence having the desired weight R. (We denote this sequence A).

The transfer of the counter from the jth state to the th (i.e., from the sequence Af to j + 1) is carried out on the arrival of the ith input pulse as follows. If the contents of the cells before the arrival of the ith pulse is such that the output of control unit 2 is equal to the signal, then elements 3 and 5 are open and element 4 is closed (the signal from the output of element 7 is not). The complete shift circuit is closed, -j, and the input pulse arrives at the clock inputs of all the cells in register 1 and the shift is complete, i.e. cyclic shift in cells from 1st to 1st. If the contents of the cells before the arrival of the nth pulse is such that at the output of control block 2, the signal is equal to P, then elements 3, 5 are closed and element 4 is open. Nep partial shift is closed, the i-th input pulse is received only on the clock inputs. cells with (k + l) -4i are fi-th and partial shift is performed, i.e. cyclic shift in cells from (k + l) -4i to.

The total shift does not change the inter-unit distances in the sequence produced by W

Noah counter. A partial shift of these distances may change. This allows, with an appropriate selection of the value of k and an appropriate choice of the logical structure of the control unit 2, to ensure that the counter works in such a way that it will have. From various states. |

Each shift cell works as follows; If there is no pulse at the clock input, the cell content does not change independently of the signal at the information input. If there is a pulse at the clock input to the cell, the value of the signal at its information input is recorded. However, at the output of the cell, a new signal appears only after the end of the pulse. sa on the clock input (i.e., the recording of new information in the cell occurs on the front

the edge of the clock pulse, and the signal at the output of the cell varies along the trailing edge of this pulse). The use of just such cells allows avoiding races to - construct the control unit 2 using circuits without memory.

Thus, the proposed device is simpler known, i.e. There are no delay elements and an OR element. This increases the reliability and speed of the proposed device.

Claims (2)

1. US patent number 3242480, class. 340351,1969. 2. USSR author's certificate No. 254201, M.C.Q 06 F 5 / OO, 1969. OR, the second input of which is connected to