SU824208A1 - Device for determining the difference of two n-digit numbers - Google Patents

Description

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The invention relates to automation and computer technology and can be used in automatic control systems and electronic computer machines.

A device is known for determining the difference of two numbers, which contains an emulsion generator, the output of which is connected to one input of the first and second elements AND, the outputs of which are connected to the inputs of the first and second binary counters, respectively, the outputs of which are connected to the comparison inputs of the comparison unit. The first and second outputs of which are connected to other inputs of the first and BTOpcSro elements AND respectively, triggers, elements OR, AND, NOT, difference counter 1.

The drawback of the device is low speed, since the number of comparison cycles is equal to the number of pulses added to the counter of a smaller number.

Closest to the proposed. is a device for determining the difference of two numbers, which contains a pulse generator, the output of which is connected to the inputs of the first / and

The second And elements, the output of each of which is connected to the inputs of the addition and subtraction of the first and second reverse meters and the first and second inputs of the first OR element, are connected to the inputs of the comparison unit, the first and second outputs of which are connected to the other inputs of the first and second elements

0 AND, the first and second inputs of the second element OR, respectively, the third output of the comparison unit is connected to the inputs of the first trigger of the third element OR, the fourth output of the unit

5 is connected to the inputs of the second trigger and the third element I, the output of which is connected to the input of the third element I, the output of which is connected to the input of the first digit of the difference counter, the input of the second digit which is connected to the output of the first element OR, zero inputs of the first and second the trigger is connected and connected to the bus setting them in the initial state, and their direct outputs are connected respectively to other inputs of the first and second elements AND, the output of the second element OR is NOT connected to another input third about element and 210

The disadvantage of the device is its speed.

The purpose of the invention is to increase speed.

The goal is achieved by the fact that a device for determining the difference of two n-bit numbers containing two AND elements, the OR element, the first element NOT, a trigger, a reversible counter, a clock generator, the output of which is connected to the first input of the first element AND, contains a switch, a second element NOT, a memory unit, a delay element, two registers, two pulse drivers and a comparison circuit, each i-th bit of which (i 1,2, ..., n) contains three elements , the element OR, the element "t NOT, va the pulse shaper and the element of equivalence , the first and second inputs of which are connected to inverse outputs ix of bits, 20, respectively, of the second and first register, as well as with the first inputs of the first and second elements, respectively, and the i-th bits of the comparison circuit, the second inputs of which are connected to the output of element 25 NOT i- ro of the comparison circuit, the input of which is connected to the output of the element of equivalence and to the first input of the third element AND of the i -th bit, from the comparison circuit / third inputs of the first and 0 SECOND elements AND i-ro bit of the comparison circuit are connected to the output of the clock generator and pulses, and the outputs are connected to the setting inputs of the bits of the first and second registers, respectively, the direct outputs of the iX bits are connected to the inputs of the first and second pulse shaper ix of the comparison circuit, respectively, the outputs of which are connected respectively to the first and second inputs the OR elements in each i-th discharge of the comparison circuit, the outputs of which are connected to the inputs of, respectively, iX bits of the reversible counter or pulses, the second 45 input of the third element AND the J-ro bit of the comparison circuit (jl, 2 ,. . ., n-1; connected to the output of the third element of the (j + 1) -th bit of the comparison circuit, the second input of the third element 50 of the n-th bit of the comparison circuit is connected to the control bus of the device, and the output of the third element of the first bit of the comparison circuit is connected to the first input of the second element yy AND, the outputs of the first element AND the i-th bits of the comparison circuit are connected to the inputs of the OR element, the output of which is connected to the single trigger input and to the input of the first HE element, the output of which is connected by the first 60 input & the second entry of the first element This And, the third input is connected with the output of the delay element and with the output of the second element NOT, the input of which is connected to the second

The inputs of the second element of the storage unit, the output of the first element I, are connected to the zero input of the trigger, the inverse and direct outputs of which are connected respectively to the inputs of the addition and subtraction of a reversible pulse counter, the inputs of which Installation O and Installation 1 are connected to the outputs respectively

(The first and second pulse formers, the a-forward and inverse outputs of each i-th digit of the reversible counter are connected respectively to the direct and inverse information inputs of each i-ro bit of the switch, the first centr of the second control inputs of the switch are connected respectively to the inputs of the first and the second pulse formers and to the first and second outputs of the memory block, the input of the installation of which is connected to the device installation bus and the first control input of the clock pulse generator, the second input of which o connected to the output of the second element And / and the output with the input of the delay element.

FIG. 1 shows a functional diagram of the device; in fig. 2 diagrams of his work.

The device contains () elements AND 1 ... 1, 2 ... 2 j, 3 ... ZU,, 4 and 5, n elements of equivalence, 6j ... 6, n + l elements OR 7. . . 7 and 8, () shapers 9 ... 9 (,,

10 10m / I and 12.2 registers 13 and

14, trigger 15 / delay element 16 (n + 2) elements tiE 11. . L1, 18 and 19, generator 20 clock pulses (GTI), reversible counter 21 (impulse, installation bus 22 / switch 23, memory block 24, control bus 25.

Consider an example of determining the difference of two five-digit numbers (01110 recorded in register 13 and 10101, recorded in register 14). After writing the numbers to the registers at the outputs of the equivalence elements b,., Bd / 6 and 6, a negative potential is formed, and at the output of the element 6j - positive. Elements And 1, 2, 2 and 1 are open at the first and second inputs, elements And Ij and 2j are closed at the second entrances, elements And 34, 3 and 3 are closed at the first and second entrances / And elements 3 and 3 are closed at one of the entrances .

Claims (2)

1. USSR author's certificate No. 341031, class, 2 G About F 7/02, 1970. 2. USSR author's certificate number 599264. cl. 2 G 06 F 7/04, 1978.