SU970366A1 - Microprogram control device - Google Patents

Description

. (54) FIRMWARE CONTROL DEVICE

The invention relates to computing.

A firmware control device is known that contains memory blocks, address registers, switches, triggers / AND elements, OR elements 1.

A firmware control device is known comprising a trigger, address registers, AND elements, memory blocks, control inputs, first and second memory block outputs f 2.

A disadvantage of the known devices is an excess of equipment.

The purpose of the invention is to reduce equipment.

The goal is achieved by the fact that in the firmware control device containing the first and second address registers, the outputs of which are connected to the address inputs of the first and second memory blocks, respectively, controls the outputs of which are connected respectively to the single and zero setup inputs of the trigger, direct output which is connected to the first input of the first element And, the second input of which is connected to the first input of the clock pulse; c6 in the device, the inverse output to the first input of the second element And, the second od which is connected to the second input clock device outputs the first and second AND gates connected to the control inputs of the first and second memory blocks, respectively, whose outputs are connected to respective inputs

10 elements of the OR group, the outputs of the elements of the OR group are connected to the information inputs of the first and second address registers.

The drawing shows the functional15 on the device diagram.

The proposed device contains the first and second registers 1 and 2 addresses, blocks 3 and 4 of memory, trigger 5, elements 6 and 7, the first and second

20 inputs 8 and 9 clock pulses of the device, a group of elements OR 10.

The device works as follows.

Let trigger 5 be in a single, state. Then a single level at the forward output of the trigger allows access to the first memory block 3. When a clock signal arrives at input 8 of the device, information is read out from block 3. Through a group of elements OR10, information from the second outputs of block 3 enters the inputs of registers 1 and 2 of the address. The signal from the first output of the first block 3 sets the trigger 5 to O. The unit level detected at the inverse output of the trigger 5 permits the access to the second block 4, and when the clock signal arrives at the second input 9 of the device, information is read from the second block 4. Through a group of elements OR 10 information from the second inputs of block 4 is fed to the input of the registers 1 and 2 addresses. The signal from the first output of the second block 4 sets the trigger 5 to one state, allowing the same access to block 3, etc.

Thus, the proposed device allows to simplify the control

part of the firmware control device by eliminating switches.

To calculate the technical and economic effect, the volume of the equipment of the com- mutator is assumed equal to the volume of the equipment of the address register, the total volume of the equipment of the AND elements and the trigger is equal to 10% of the volume of the equipment of the group of elements OR — 50 % of the switchboard equipment, then the amount of equipment in the control part of the known device is 35

T, 2Rg + 2Ko „+

2I + Tr. 4.1Rg,

and the amount of equipment of the control part of the proposed device is equal to dO

T, 2Rg + 12I + T.f + OR 2.6Rg

n 1 ± 4

.100% .lQO%

 f -L

 36.65%

Thus, the proposed device can reduce the amount of equipment by 36.65%.

Claims (2)

1. USSR author's certificate number 646333, cl. G 06 F 9/22, 1976. 2. Authors certificate of the USSR 679980, cl. G 06 F 9/22, 1977  (prototype).