SU932487A1 - Number ordering device - Google Patents

Description

The invention relates to automation and computing, can be used in digital information processing devices and discrete automation.

A device for comparing numbers is known, which contains a set of comparison nodes, OR elements, the AND element, the AND blocking signs, Less and More, the first output of each comparison node is connected to the corresponding input of the AND element, the inputs of the comparison nodes are connected to the input buses, and the control inputs to The control bus, the first output of each comparison node is connected to the corresponding inputs of the elements. D1 blocking of signs. The disadvantage of this device is the ability to solve the problem of ordering arbitrary numbers.

The closest technical solution to the proposed is

a device for arranging numbers, a memory for storing codes of numbers to be sorted, several buffer registers, each of which provides the storage of one code, several c. comparison schemes, each of which is used to compare the code read from the buffer register with the code read from memory, and for each 10, in each comparison circuit, the output signals are greater than, less than. The device has several addressing nodes for storing code addresses in an address sequence, in which code addresses correspond to codes stored in buffer registers. To connect the buffer registers to the comparison circuits, several selectors are provided, each of which is controlled by a code address stored in the corresponding addressing node. The transmission node consists of several 39 transmission schemes, each of which is connected between the corresponding one addressing node to selectively transmit code addresses between the addressing nodes when the corresponding output comparison circuit is generated. More than. The transmission node contains a block for transmitting the address of each code from the memory in any of the addressing nodes to which the output signal corresponds. On more than one arm, the comparison circuit connected to it and the Signal Less than on the other arm. The specified transmission node arranges the address sequence of code addresses. The output node serves to read the information codes from the buffer registers selected by the selectors in the prescribed order of the C2 J code addresses. A disadvantage of the known device is the low performance caused by the irrational time spent on sequential comparison of the codes of the information being ordered and the time spent on performing operations address codes. The purpose of the invention is to increase speed. The goal is achieved by the fact that the device for ordering numbers containing AND groups of input elements AND, n input registers, n groups of elements And rewriting, (nl) K group in each group of comparison circuits, (n-1) group k in each group of triggers, a synchronization block, a group of elements OR, information inputs of the device are connected to information inputs of input elements of groups, outputs of elements AND of each i-th group, where 1 1,2 ,, .., п, are connected to information inputs - th input register, the outputs of each i-ro input register dinene with information inputs of elements AND rewrites of the 1st group, outputs of elements AND rewrites of each (i + 1) -th group are connected to the first information inputs of the comparison circuits of the i-th group, outputs More and Equal, less than each J-th comparison circuit -th group, where, 2,.,., (nl). are connected to the inputs of the installation in the unit and the left state, respectively, of the j-ro j-th scheme of the comparison group, where j 1,2,.,., (n -i), are connected to the installation inputs to the single and zero states, respectively, of the j-ro trigger of the i-th group, the second information inputs of each j-th second Comparisons of the k-th group, where k 1,2,.,., (p-1). are connected to the outputs of the AND rewriting elements of the (1-1) -th group, reversible counters, delay elements, memory block are introduced, and the direct output of each j-ro trigger of the first group is connected to the first input of the j-element OR, the inverse output of the first trigger of the first group is connected to the first input of the n-th element OR, the inverse outputs of the second, third, ..., (nl) -ro Triggers of the first group are connected through the first, second, ..., (p-2) -th delay elements of the first group with the second, third, ..., (p-1) -th inputs of the corresponding p-g about the OR element, the direct output of each j-ro trigger of each} -th group, except the first, through the j-th delay element of the i-th group is connected to the j-My input of the i-ro element OR, the inverse output of each j-ro trigger each i-th group. connected through (ni j) -th delay element with (ni + j) -biM input (il) -ro of the element OR, the output of each f-ro element OR is connected to the information input of the i-ro reversible counter, the outputs of each i-ro reversible the counter is connected to the inputs of the 1st element NAND, the outputs of each 1st input register are connected to the information inputs of the output elements AND the 1st group, the output of each i-ro element AND NOT connected to the first control input of the output elements AND (1 + 1) -th group, and the output of the n-element AND-NOT connected to the first control input output elements And p your group, the outputs of the output elements And groups are connected to the inputs of the elements OR the groups whose outputs are connected to the inputs of the memory block, the control input of the device is connected to the input of the synchronization block, the first output of which is connected to the control inputs of the input elements And groups, the second output of the block synchronization is connected to the control inputs of the elements And rewriting groups, the third, fourth and fifth outputs of the synchronization unit are connected to the control inputs of the output elements And groups, reversible counters and input registers co accordingly. five

The synchronization block contains pulse shapers, delay elements, triggers, OR, AND, AND-NOT elements, a counter, a clock pulse generator, the sync synchronization block input being connected to the setup input of the first trigger unit and through the first delay element and driver pulses with the input of the installation in the zero state - 5 of the first trigger and the input of the installation in the single state of the second trigger, and through the second delay element and the driver of the pulses with the input of the installation in the zero state - 20 of the second trigger and through the third delay element and the third pulse generator, to the first input of the OR element and to the input of the fourth delay element, the output of which 25 is connected through the fourth pulse shaper to the installation input of the third trigger to the zero state and to the input of the start of the clock pulse generator, the output of which is 30 connected to the first input of the AND element, to the counter input and to the second input of the OR element, the output of which is connected to the installation input in the unit state of the third trigger, jj the reverse output of which is connected to the second And, the outputs of the tap are connected to the inputs of the NAND element, the output of which is connected by the input of the stopping of the clock 4o pulse generator, the direct outputs of the first, second and third triggers, the output of the element I are connected to the first, second, third and fourth outputs of the block, block through the fifth driver is connected to the fifth output of the block.

Fig, 1 shows the block diagram of the device; figure 2 - block diagram of the synchronization node.

The device contains groups of input elements And 1., l .... t IH input registers 2, 2, ..., 2ts,

groups of elements And 3

rewriting.groups schemes C, C ,,,. 4y, compare, group of triggers 5. 5a.f ...,, elements C, .. ,, 6vvi delays, groups of elements OR 7 / | i7i I ... 7n, reversible counters g

8,8, ..., 8 ,, elements AND-NOT 9, 9, groups of elements AND 10., 10, ... 10, group of elements OR 11, block 12 of memory, block 13 of synchronization.

The synchronization unit 13 contains delay elements, drivers 18-22, triggers, generator 2b of clock pulses, counter 27, AND 28, and OR 29 element AND-NOT 30.

The device works as follows. in the way

Operation starts on the Start signal, received via the control code bus to the input of the synchronization unit 13. Therefore, the signal by the amplifier-shaper 19 generates a signal OSTO which arrives at the zero inputs of the registers 2.1-2.4 and zeroes them. Upon termination of the CCO signal in the synchronization unit 13, a synchro impulse CI1 is generated, which arrives at the first inputs of the AND elements of the first group 1.1-1.4, allows writing the information codes to the input registers 2.1-2.4.

Upon completion of writing the codes of the numbers of the ordered array from the synchronization unit 13, the sync pulse SI2 is sent to the first inputs of the nodes of the elements of the second group 3.1-3.4, allowing simultaneous output of the codes of the numbers of the ordered array to the inputs of the corresponding 4,1-4.6 comparison circuits. Comparison circuits are the comparison nodes for the highest bit of the sequential type, therefore the duration of the sync pulse CI must ensure the passage of the signal through the And element, to the middle of the field. and trigger sign. Triggers 5.15 .6 of the sign provide storing and storage of the sign of the comparison result and, through the elements OR 7.1-7.4, give impulses from the single and zero outputs to the inputs of the reversible counters 8.1-8.4. To ensure the triggering of the reversible counter triggers to the inputs of the OR 7.4 elements, elements 6h1-6 are connected to the inputs of the second.

Claims (2)

The number of pulses recorded in the reversible counter is a priority code K; numbers / array A. Thus, after comparing the codes of the ordering numbers of the array, in the reversible counters 8.1–8.4, priority codes of the ordered order are written, and the priority code of the largest number is zero. In this connection, the unit outputs of the triggers of the reversing estimator storing the priority code of the highest number will have zero potentials, and the output of the corresponding AND-NOT element is the unit potential that resolves to the second input of the AND node of the third group 10.1-10. issuing the highest number code. To ensure the sustained sequential operation of reversible counter triggers and the formation of priority codes between the end of the CI2 sync pulse and the beginning of the first SIZ sync pulse, a delay is needed, the duration of which can be determined using the following formula:, SL - tr. where tX is the response time of the reversible counter trigger; the propagation time of the signal in the OR element; the number of ordered array codes. . The issuance of codes of the largest number is carried out from the output of the short input register through the AND node of the third group, at the second input of which there is a resolving potential and on. the first input of which from the synchronization unit 13 is the sync pulse of the PPE. The highest number code through the node of elements OR 11 is written to the first register 12 of the stack memory. At the end of the PPE sync pulse. in the synchronization unit 13, a synchro impulse SI is formed, which is fed from the fifth output of the synchronization unit to the reverse inputs of counters B-I-B, reducing the contents of the counters by one. Thus, for the number following the highest, the priority code becomes zero and the resolving potential is fed from the output of the corresponding AND-NOT element to the AND element of the third group. When the PPE sync pulse arrives, the following number code is written into the first register of memory block 12, the hold of which is rewritten into the second register, and so on. The number of issue cycles is counted in synchronization block 13 by the counter 27. At the end of the reading of the codes, the contents of the counter 27 become equal to zero, allowing the formation of a signal on which the clock generator stops. If there are two equal numbers in the information array at the output of the corresponding comparison scheme, the S is not present, therefore the trigger of the sign is in the state in which it was after the end of the transient processes. In this case, the sequence of issuing codes of numbers is determined by the current state of the given sign trigger. Evaluation of the technical and economic efficiency of the invention was carried out by the method of mathematical modeling with the subsequent software implementation of the model at the ZUM BESM-6. The analysis shows that the efficiency of the proposed ordering device depends on the volume of the array being ordered and can be from 5 to 3. 10. The application of the present invention is most effective for 100. Claims of the invention 1. A device for arranging numbers, containing groups of input elements AND, AND input registers, groups of elements AND rewriting, (and -1) group of K in each group of sirennye schemes, See About a group of K and each trigger group, a synchronization unit, a group of elements OR, information inputs of the device are connected to information inputs of the input elements of the groups, outputs of the AND elements of each group, where 1.2 b, are connected to the information I-th input register, The outputs of each 4th input register are connected to the formation inputs of the elements AND group overwrites, the outputs of the elements AND overwrites each (1-1) -th group podklychen to the first information inputs of comparison circuits of the i-th group, outputs Bolbshe and Equal less than each j -Th comparison schemes of the t-th group, where j 1,2 ,, .., (and -i), are connected to the installation inputs in the single and zero state, respectively, of the j-ro trigger -i-th group, the second information inputs of each j th comparison scheme, the K-th group. where K 1,2, ..., (I-1, are connected to the outputs of the elements AND rewriting of the (1 + 1) -th group, characterized by the fact that, in order to improve speed, reversible counters are introduced into it, the elements I- NOT, delay elements, memory block, and the direct output of each U-th trigger of the first group is connected to the first input of the j-th element OR, the inverse output of the first trigger of the first group is connected to the first input of the I-th element OR, inverse outputs the second, third, ..., (and -1) th triggers of the first group are connected through the first, second, ..., (and-2jth delay elements of the first groups with the second, third, ..., (AND -1) -th inputs, respectively, AND-th element OR, direct output of each J-ro trigger of each 1st group, except the first, through the j-th delay element 1- th group is connected to the j-th input of the -i-rc element OR, the inverse output of each j-ro trigger of each H th group is connected via (and - 1 + J) -th delay element with (and - i + f -th input The Ci-O-ro element OR, the output of each 4th element OR is connected to the information input of the i -th reverse counter, the outputs of each horizontal reversing counter are connected to the inputs of the -V-ro element NAND, the outputs of each 1- About the input register is connected to the information inputs of the output elements of the I} -th group, the output of each -i -th element of the I-IE is connected to the first control input of the output elements of the And., (i -f 1) -th group, and the output of the This element is NOT connected to the first control input of the output elements AND of the first group, the outputs of the output elements of AND groups are connected to the inputs of the elements OR the groups whose outputs are connected to the inputs of the memory block, the control input of the device is connected to the input of the synchronization unit, the first output of which is connected to the control input s input and element9v groups yield blo second synchronization ka connected with the control inputs of the AND rewriting groups, third, fourth and first outputs the block synchronization key to the control inputs of the AND output groups; reversible counters and input registers, respectively. 2. The device according to claim 1, of which is that the synchronization unit contains pulse shapers, delay elements, trigers, OR, AND, NAND units, a counter, a clock generator, and the input of the synchronization unit is connected to the installation input into the unit state of the first trigger and through the first element and the pulse shaper - with the installation input into the zero state of the first trigger and the installation input into the single state of the second trigger, and through the second delay element and the pulse shaper - with the installation input a zero The second state of the second trigger and through the third delay element and the third pulse generator - with the first input of the OR element and with the input of the fourth delay element, whose output through the fourth pulse shaper is connected to the installation input of the third state of the third trigger and with the trigger start input of the clock generator pulses, the output of which is connected to the first input of the AND element, to the input of the counter and to the second input of the OR element, output / :; which is connected to the input of the unit in a single state of the third trigger, the inverse output of which is connected to the second input of the element AND, 9 COURSES of the counter are connected to the inputs of the element NAND, the output of which is connected to the input of the stop of the clock generator, the direct outputs of the first, second and third the triggers, the output of the element I are connected to the first, second, third and fourth outputs of the block, the input of the block through the fifth coefficient driver with the fifth output of the block. Sources of information taken into account in the examination 1. The author's certificate of the USSR f 6918A7. cl. G About F 7/02, 1977, 2. Patent ClilA K 3931612, cl. G About F 7/02, published. 1976 (prototype). Mu