SU1679492A1 - Computer-to-data communication equipment interface unit - Google Patents

Abstract

The invention relates to automation and computing and can be used in the construction of data transmission systems. The aim of the invention is to increase the reliability of the device. The device contains six And elements, three comparison blocks, two groups of And elements, a issuing register, a mode register, a receive register, two delay elements, a memory block, two counters, a parallel-serial converter, three impulse drivers, a readiness node, serial-parallel converter, four switches and a display unit. The invention allows control of the output information circuits by returning this information to the device and comparing with the transmitted signals. In addition, the device can be connected in parallel with a similar device and control its operation by comparing the signals generated by the monitored and the monitoring devices. 6 sludge. L | "-tg, -, | C

Description

The invention relates to automation and computing and can be used in the construction of data transmission systems.

The aim of the invention is to increase the reliability of the device.

FIG. 1 shows a functional diagram of the proposed device (a is a device entry input; b is an input for setting a device register number; c is an input for setting a device mode; d is a group of information inputs / outputs for a device; d is a group of input-outputs for setting a device bit number; е - address input; g — device read input; h — device read permission input; and — first sync-go; k-information output of the device; l — second sync-input; m — output information input groups; n — output cycle inputs; cycle input group n - a group of inputs for receiving information); in fig. 2 is a circuit of a series-parallel converter (a is a group of inputs-outputs of setting the bit number; b is the first synchronous input; c is the information output of the device); in fig. 3 is a diagram of a series-parallel converter (a is a group of inputs-outputs of setting the bit number; b is the first synchronous input); in fig. 4 shows the layout of the formation of the readiness (a is the readout input of the device; b is the second synchronous input); in fig. 5 is a diagram of a pulse shaper 23 (24) (a is the first synchronous input; b is the second synchronizing input); in fig. 6 is a diagram of the integration of devices into a complex: I — device 1; II - device 2; III - device N; IV is a decoder (a is a device write input; b is an input for setting a device register number; c is a device enable input; g is an information group xj

ABOUT

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tions of the device; d - device readout input; e - address input; W - device mode setting input; h - the first synchronous input; and - second synchronous input; k - device mode setting input 2; l - group of input-output number of bits; m - input for setting the device mode N; n - information output device 1; o - input of issuance cycles 1; p is the input of reception cycles 1; p is the input of the reception information 1; C - information output device 2; t - input cycles issuance 2; y- input receive cycles 2; f - input of the reception information 2; x - information output device N; C - input cycles issuing N; h - input of receive cycles N; w - input information receiving N).

The device (Fig. 1) contains the first element And 1, the third element And 2, the third unit 3 comparison, the second element And 4, the fourth element And 5, the second and first groups of elements And 6 and 7, the issue registers 8, mode 9, reception 10, second delay element 11, memory block 12, second 13 and first 14 counters, first comparison block 15, parallel-to-serial converter 16, third pulse generator 17, readiness forming unit 18, sixth And 19 element, serial-parallel converter 20 , the first delay element 21, the second comparison block 22, the first pulse generator 23, second pulse generator 24, fifth element AND 25, fourth switch 26, first 27, second 28 and third 29 switches, display unit 30.

The parallel-serial converter 16 (Fig. 2) contains a delay element 31, an AND 32 element. A comparison circuit 33, a shift register 34, an AND 35 element, an OR 36 element, a decoder 37 and a counter 38.

The serial-parallel converter 20 (FIG. 3) contains a delay element 39, an AND 40 element, a comparison circuit 41, a shift register 42, an AND 43 element, a counter 44, and a delay element 45.

The readiness formation node 18 (FIG. 4) contains the triggers 46-48, the AND-NE element 49, the triggers 50, 51, and the AND-NE elements 52, 53.

Shapers 23 and 24 (Fig. 5) contain elements NOT (inverters) 54 and 55, triggers 56-59, elements And 60-62.

The parallel-to-serial converter 16 is designed to convert the information recorded in the issue register 8 in the parallel code into a serial code for output to the information output.

The serial-parallel converter 20 is designed to convert the information coming from the switch 29 in the serial code into

parallel code followed by recording in the register 10 of the reception.

The readiness building node 18 is designed to form readiness for issuance and reception. Readiness is formed on the first and second information inputs.

The formers 23, 24 are designed to differentiate the leading and trailing edges of the clock frequencies arriving from the switches 27, 28. The former

23 differentiates the leading and trailing edges of the clock frequency, the driver

24 - only the back front.

The device works as follows.

Before starting work, a code is entered into mode register 9, which determines the further order of operation of the device.

High bit of register 9 defines

5 device operation mode - main mode or control mode. In the control mode, the device only receives clock and data signals from the data transmission equipment (FDA), but does not transmit anything

0 according to the group of information inputs / outputs of the device, which is achieved by applying a zero signal to the input of the element I 4 from the output of the high bit of the register 9 mode.

To write the control code to the register 9, the necessary code is fed to a group of information I / O devices —

0 a single signal to the inputs of the recording and setting the device mode and a zero signal to the input of the register number of the device. In this case, a single signal is generated at the output of the element 2, which

5 enters the clock input of register 9 and records information from the group of information inputs and outputs of the device.

In the main mode, in register 9 there are two units: in the high order and in

0 bit, denoting in the position code the number of this device.

In block 12, the memory by addresses, the highest bits of which, defined by the bit outputs of register 9, have only

5 one unit, contains the binary code corresponding to the binary representation. device number. The information output of the memory unit 12 is connected to the control inputs of the switches 26-29, allowing information and clocks from the ADF set served by this device to flow into the device.

Information intended to be transferred to the ADF (one or several bytes) is fed into a group of information inputs-outputs of the device and is written to the output register 8 by the signal from the output of the And 1 element. To do this, the inputs of the And 1 element receive single signals from the inputs recording and setting the register number of the device. To enable the recording, a single signal is required from the output of block 3, where a comparison is made of the number of the device to which the information arriving at the address input of the device is designed, with its own device number generated at the output of block 12 of the memory. In order not to spoil the previous information, which may not yet be transferred to the ADF, the And 1 element is controlled by a signal from one of the outputs of the readiness generating unit 18, corresponding to reading the information from the register 8 received at the information input of the parallel-serial converter 16. information from the converter 16 controls the output clock signal of the corresponding ADF, which passes through the switch 27, is differentiated by the pulse shaper 23 and is fed to the clock input of the converter 16. onnogo output transducer 16 signals go to an information output apparatus and then input to the ADF.

After the output of the next piece of information is completed, the converter 16 generates a signal at the output of the conversion end, which is fed to the input of the readiness formation node 18, and receives the next piece of information from the issue register 8.

Reception information from the corresponding set of ADF through the switch 29 is fed to the information input of the serial-parallel converter 20; the operation of the latter is controlled by the receive cycles of the same set of ADF, coming through the switch 28 to the input of the pulse shaper 24, from which the signal goes to the clock input of the converter 20.

After the accumulation of the group of information is completed, converter 20 generates a signal at the output of the conversion end, which is fed to the input of node 18 and, moreover, is written to the code receiving register 10 from the information output of converter 20. After that, converter 20 starts accumulating another piece of information.

Reading from the device the accumulated information (from register 10)} and the readiness signals of node 18 is carried out with the help of elements AND 6. This happens on a signal arriving at the input of the reading device, which interrogates AND 6 through element AND 4. 4 polls and elements 7 for transmitting to the group of input-output the setting of the device number of the device codes from the outputs of the number of the processed bit of the converters 16, 20.

The synchronization of the converters 16, 20, pulse formers 23, 24, and node 18 is performed by two series of clock pulses shifted one relative to the other by half the follow-up period.

In the main mode, the input and output circuits of the device are monitored.

The signal from the information output of the device outside the device is transmitted

to the corresponding information input of the switch 26. From the output of the switch 26, this signal is sent to one of the information inputs of block 22, where it is compared with the information output signal of converter 16. The signal from the output of comparison block 22 is gated on the AND 25 element by the signal from the output of the pulse former 23, and in the case of non-comparison, the device number 30 is output from the output of memory block 12 to the display unit 30.

Comparison unit 15 compares the code from the output of receive register 10 with the code from the information input-output group of the device. At the moment when the signal from the read permission input of the device passes through the element 5, the information read out from the device’s own input / output group is a code read from its own receive register 10. Therefore, in the absence of faults in the elements And 7 at the output of the unit 15 comparison will be a zero signal. The output of the comparison unit 15 is gated by the signal from the output of the element AND 5 and the first clock pulse. If there is an incomparison, the signal from the output of the element And 19 writes into the display unit 30 a device number from the output of the memory block 12.

When several devices are combined into a complex, as shown in FIG. 6, it is possible to control the operation of neighboring similar devices with the help of one of the devices. For this, the information and clock outputs and information inputs of the ADF kits are connected to all devices of the complex.

clock and information signals from all sets of ADF.

The device, on which the functions of checking other devices are assigned, is transferred to the monitoring mode. For this, the high-order bit of register 9 is set to the zero state, the single state of the other bits of register 9 indicates the device numbers of the complex that should be monitored by this device. (The register bit 9 corresponding to the number of the control device must necessarily be in the zero state).

One device can control multiple devices. The number of the monitored device is determined by the contents of register 9 and counter 13. Code i at the output of counter 13 (0 i N-1), where N is the total number of devices in the complex) corresponds to the output of memory block 12 of the code for the j-th unit contained in Register 9 (1 jk), where k is the number of ones in register 9). An expression for J is selected from the condition j (i) mod k. This means that with a small value of k, one device can be controlled at different values of 1, which are separated from each other by the value of k.

The monitoring of the operation of any device is carried out by parallel processing of information and comparing the results of the monitoring and monitoring devices.

The monitoring time is determined by the counter 14. In the initial state, both the counters 13 and 14 are set to the zero state (the initial setting signal is not shown in Fig. 1). The control time is calculated by differentiated clock pulses of the monitored device, coming through the switch 27 and shaper 23 pulses. When the zero code at the output of the counter 13 at the output of the memory block 12, the code corresponding to the first monitored device is selected, the control for which is contained in the register 9 (counting starts from lower order bits).

The device now seems to have the number (address) of the monitored device, and the access (writing and reading) occurs immediately to two devices. The difference is that the most significant bit of register 9 prohibits the passage of signals through elements 6 and 7 in the monitoring device, so that codes read from register 10 of the device being monitored appear on the group of information inputs / outputs of the device.

Thus, in the monitoring mode, the comparison unit 22 compares the signal at the information output of the converter 16 and the output information,

coming through the switch 26 from the output of the controlled device. When these signals are not compared, the number of the monitored device is recorded on the display unit 30.

0 Transmitter 20 receives the information and reception cycles are the same as on the monitored device. Thus, the device duplicates the transformation of the monitored device, and 5 compares the contents of the register 10 of the controlling device with the contents of the register 10 of the monitored device, arriving at the group of information inputs / outputs of the device.

0 In case of incomparability, the number of the monitored device is entered into the display unit 30. The duration of the monitoring is determined by the counter 14. At the end of the monitoring time, the impulse of repartition

5 of the counter 14 through the delay element 11 adds one to the contents of the counter 13. At the output of the memory block 12, a code appears corresponding to the device number specified by the second unit of the register 9 of the mode 9. At the same time, the overflow signal of the counter 14 starts the pulse shaper 17, which locks the AND 19, 25 elements. In the converters 16, 20 of the control device

5, subphasing occurs in order to coordinate the time of the signals of the conversion end at the outputs of the monitored and control devices. The pulse duration at the exit of the former 17 is selected based on the duration of the phaseization of the transducers 16 and 20.

At the end of the pulse at the exit of the former 17, the operation control begins.

5 next device.

Thus, with further change of the code on the counter 13, new devices are connected to the control.

Claims (1)

Invention Formula 0 Device for interface of computer with data transmission equipment, containing six elements AND, output register, receive register, mode register, first counter, first block compared, four switches, two delay elements, two pulse drivers, serial-parallel converter, a parallel-serial converter and a readiness formation unit, the first input of the first element I being the recording input of the device for connecting to the control bus of the computer, the output of the first element I Dinen with a clock input of the output register, information inputs of the output register and the mode register are connected to the group of information inputs of the device for connecting to the computer data bus, the first input of the second element I is the read input of the device for connecting to the control computer bus, the output of the receive register connected to the first information input of the first comparison unit, the first output of the first and the output of the second pulse shaper are connected respectively to the clock inputs of the parallel-to-serial sequence the parallel and parallel converters, the outputs of the first and second switches, respectively, are connected to the enable inputs of the first and second pulse formers, the output of the third switch is connected to the information input of the serial-parallel converter, the outputs of the conversion end parallel-serial and serial-parallel converters are connected respectively to the first and the second information inputs of the formation of the readiness node, that is, so that, in order to increase access the second operation unit, the third pulse generator, the second counter, the display unit, the memory block and two groups of elements AND, the second input of the first element AND connected to the inverse input of the third element AND are input to the device. the device register numbers of the first and second direct inputs of the third element I are connected respectively to the recording input and the mode setting input of the device for connection to the control computer bus, the output of the fourth element I is connected to the change inputs the numbers of the parallel-serial and series-parallel converters, the synchronous inputs of which are connected to the first synchronized input of the device for connecting to the first synchronous output of the computer, the inputs of specifying the number of bits are connected to the input-output group of specifying the number of bits of the device for connecting to the control computer bus and outputs the first group, the outputs of the fifth and sixth elements And are connected respectively to the inputs of the recording and clock cycles of the display unit, the information input connected to the output of the memory block and the pack The four inputs of the four switches, the groups of information inputs of the first, second and third switches are respectively groups of inputs of output cycles, receive cycles and a group of information inputs of the device for connecting to the data transmission equipment, the group of information inputs of the fourth switch is a group of control information of the device inputs , the first input of the fifth element I is connected to the output of the second comparison unit, the first and second information inputs of which are connected respectively to the information to the output outputs of the parallel-serial converter and the output of the fourth switch, the output of the first counter is connected via the third pulse shaper to the second input of the fifth element I, the third input connected to the second output of the first pulse shaper, the first and second synchronous inputs of which are connected respectively to the first and second the synchronous inputs of the device for connecting to the synchronous drives of the computer and the first and second synchronizing inputs of the second pulse driver, the synchronous input and the input of the read resolution of the node and the readiness generator is connected respectively to the second synchronized input of the device and the reader input of the device for connection to the control bus of the computer, the output of the reception register, the first and second outputs of the node of the formation of gaotic conductivity connected to the first inputs of the corresponding elements And the second group, information output of the parallel-serial converter is the information output of the device for connection to the data transmission equipment; the outputs of the elements of the second group are connected to a group of information the device outputs for connecting to the computer data bus and the second information input of the first comparison unit, the output of the sixth element I connected to the first input, the second, third and fourth inputs of which are connected respectively to the outputs of the third pulse generator, the fourth element And and the first delay element, whose input connected to the first synchronous input of the device, the output of the third element I is connected to the clock input of the mode register, a group of outputs. Which and a group of outputs of the second counter are connected to the group the address inputs of the memory unit, the output connected to the first information input of the third comparison unit, the second information input of which is the address input of the device for connection to the address bus of the computer. and the output is connected to the third input the first element of And, the fourth input of which is connected to the second output of the site for the formation of readiness, the first inputs of the corresponding elements of the first group are connected to the outputs of the number of the processed bit of the parallel-serial and series-parallel converters, the second inputs of the elements of the first and second groups are connected to the output The second element And, the second and third inputs of which are connected respectively with the output of the third unit of comparison and the output of the senior bit of the mode register, the first and second inputs of Werth AND gate connected respectively with the output of the third comparator and the input of block razre0 five A readout device for connecting to a computer control bus, the clock and information inputs of the receive register are connected respectively to the output of the conversion end and the information output of the serial-parallel converter, the output of the first And element is connected to the input of the read inhibit of the readiness node, the first output of the first pulse shaper connected to the counting input of the first counter, the output of which is connected through the second delay element to the counting input of the second counter, the register output in The output is connected to the information input of a parallel-to-serial converter. FIG. 2 a 6