RU2159952C1 - Device for information input - Google Patents

Abstract

FIELD: automation and computer engineering. SUBSTANCE: device may be used for reading information from pulse and static signal detectors in control systems, in particular, in design of function-oriented microprocessor information processing and control systems. Goal of invention is achieved by memory units, counters, signal state commutator for input channel detectors, synchronization unit, NAND gates. This results in possibility of detection of maximal possible threshold value for detection of alteration of signal state of detector for each input channel and in automatic correction of errors upon storage of current results of device operations. EFFECT: increased field of application, increased stability to noise. 5 dwg, 2 tbl

Description

 The invention relates to automation and computer technology, is intended for inputting information from sensors of pulsed and static signals in control systems and can be used to build controllers for inputting bit information in functionally oriented microprocessor-based information processing and control systems designed taking into account the following basic principles [1] : software (microprogram) control; modular construction; trunk information exchange; increasing computing power.

 Typically, such a system contains a system core module formed by a synchronization and initial installation circuit, a microprocessor (or single-chip computer) and combined memory (RAM + ROM + ROM), functionally oriented controller and modem modules for inputting and outputting information during the system’s interaction with external objects (by the operator panel, event sensors in the control object, actuators, adjacent systems, etc.), a power supply unit and a system bus for exchanging information between modules (construct clearly and functionally finished component parts of the system) - see, e.g., [2] and [3]..

 When the equipment is turned on, its components are brought into working condition (reset to the initial state, tested, initialized, etc.) independently or under the control of the system core using the bit information input controller, through which information about the readiness (health) of internal and external devices and bit information in the form of pulsed and static signals, and all or part of the bit information through this controller can be directly entered into adjacent systems.

 Pulse signals include those for which, at least, their minimum and maximum (final) durations are determined, and static signals include signals that, after being established, can retain their state indefinitely. For example, after setting the signals of readiness of serviceable devices remain unchanged until the equipment is turned off, and pressing the button on the remote control by the operator causes a signal to appear, the duration of which is on average 40 ms [4].

 Pulse signals of different input channels (hereinafter referred to as communication channels formed by the outputs of the signal sensors, wired communication lines and the outputs of the channels that are inputs of the device for inputting information) can differ significantly from each other in terms of interference and time parameters. In this regard, the threshold for detecting signal changes for each type of sensor is usually selected experimentally and lies, for example, for contact sensors ranging from 5 to 50 [5]. This detection is usually done by converting the time interval into a code using the classical method of sequential counting [6].

 Since the communication channels of the input channels have a considerable length (up to tens and hundreds of meters), and the signals of different channels can vary significantly in parameters, the creation of a simple highly reliable controller for noise-tolerant input of bit information into adjacent systems and the core is an urgent technical task, so how the quality of operation of the equipment as a whole depends on the quality of input of this information.

 The solution to this problem is possible by creating a controller based on a device for entering information with a structure invariant to the type of system trunk. In this regard, a pulse generator, a system-invariant device for inputting information into adjacent systems and the core, and an information exchange control device with adjacent systems and the core, which generally contains codes and signals transceivers, a chopper, an address addressing decoder, can be distinguished as a controller from the trunk, a memory unit for interpreting input channel information (for transmitting it to external systems and / or to the core by interrupts corresponding to changes in sensor status signals anal input), a buffer register or FIFO type stack several input words into the nucleus (see., e.g., [7]). and a control unit for ensuring interconnected operation of all controller components. In such a controller, the structure of the exchange control device is highly variable and is determined by the connections with adjacent systems and the type of system bus (UNIBUS, Q-BUS, IEEE796, ISA, VME, etc.), and the structure of the device for inputting information is practically independent of type of system bus and is designed to provide the ability to enter from each channel the required amount of information into adjacent systems and a core with high noise immunity.

 At least three types of devices for inputting information are known, the first [8–11] and second [12–14] types being highly specialized and designed to provide noise-resistant input of information from the keyboard (mechanical or touch) and binary sensors of the measured value ( angle, displacement, temperature, etc.), respectively, and devices of the third type, designed to enter information from sensors of pulsed and potential signals, for example [15 - 17], have limited functionality because they do not provide noise-resistant simultaneous input of information into adjacent systems and into the core.

 A device [17] is known that contains a switch of state signals of input channel sensors, formed by the switch itself and controlled by a level converter, to ensure operation from signals with four types of levels (case - gap, TTL, 27V - gap, CMOS - determined according to GOST 18977-79 ), a pulse generator, a counter, two memory blocks, an encoder, a matching switch, a register and an element I.

 In the process of functioning, the device [17] analyzes the signal of each channel in three time samples with a programmable frequency for each channel. In this regard, when interruption is enabled, the device for each channel in the current window of three samples can send a message to the system kernel either about the reception of interference or about the detection of a signal change with a threshold equal to "two".

 Since the detection threshold in the device [17] is the same for all input channels (equal to two), and the channels, as a rule, have different characteristics (see, for example, [5]), the device [17] in the general case will not be able to provide noise-immunity entering information into the system core from all channels.

 Of the known technical solutions, the closest to the proposed one is a device for inputting information [15], containing a pulse generator with two outputs (ie, a synchronization unit), a counter, a switch of signal states of input channel sensors, memory blocks, address decoders controlling memory blocks ( each of them is formed by two decoders, a trigger, two groups of AND elements and a counter), and the outputs of the input channels connected through the switch to the information inputs of the memory blocks, the input of the write pulse and the address input of each about which it is connected through its control address decoder, respectively, to one of the outputs of the synchronization block and to the code address input of the switch connected to the code output of the counter, the counting input of which is connected to the other output of the synchronization block.

 During the operation of the device [15], the synchronization unit generates at its outputs two sequences of pulses that do not coincide in time. According to the first sequence of pulses, the contents of the counter are changed and transmitted through the switch to the information inputs of all memory blocks of the bit signal of the selected input channel, and using the second sequence of pulses, bit information is recorded in certain cells of the memory blocks according to the selected operation algorithms of the control address decoders.

 Thus, in the device [15], bit information is transferred cyclically in time from all input channels to the corresponding bit cells of the memory blocks.

 If later on in the equipment the use of information of memory blocks is tolerant to short-term malfunctions (for example, this information is used for indication and control), then the use of a simple device [15] is quite advisable. However, when this information is used to control a dynamic technological process, failures in transferring channel information to memory blocks can lead to undesirable (unpredictable) consequences, i.e. in such situations, the use of the device [15] is practically unacceptable.

 Therefore, the device [15] has a limited area of use, which is due to its low noise immunity, since the processes of changing information in the input channels are asynchronous to the processes of its transfer to memory blocks.

 The present invention solves the problem of expanding the field of use of the device and ensuring its noise immunity comprehensively both by setting the maximum threshold for detecting a change in the sensor status signal for each input channel, and by automatically eliminating failures while storing the current results of the device’s functioning.

 To achieve this technical result, an information input device comprising a memory unit, a counter, a signal switch of the state of input channel sensors, a synchronization unit and input channel outputs, which are information inputs of the switch, the address code input of which is connected to the code output of the counter, the input of which is connected with the first output of the synchronization unit, an additional memory unit, an additional counter, four NAND elements, a comparator, a control unit, a clock input connected to a clock are introduced the input of the synchronization block, the reset input connected to the reset inputs of the counter and synchronization and control blocks, the address code output of the input channel number, the first pulse and information outputs of the write pulse and the filtered state bit of the channel sensor for input into adjacent systems, the second pulse and information the outputs, respectively, of the pulse of the detection of the state change and the status bit of the channel sensor for input into the core, and the output of the ready signal, and the counter code output is connected But with the address code output of the input channel number of the device, with the address code input of the memory block and with the inputs of the least significant bits of the address of the additional memory block, the inputs of the highest bits of the address are connected to the additional code output of the counter, which is its highest code output, the code output of the additional memory block is connected with the first information input of the comparator, the second information input of the comparator is connected to the information input of the additional counter and to the code information output of the unit memory, the code input of which is connected to the code output of the additional counter, the output of the switch is connected to the first input of the first NAND element, the output of which is connected to the first inputs of the second and third NAND elements, the first output of the synchronization unit is additionally connected to the gate input of the memory block selection and with the second inputs of the first and second AND-NOT elements, the first information input of the control unit is connected to the output of the third AND-NOT element and with the first input of the fourth AND-NOT element, the second input of which is connected to the the ode of the second AND-NOT element, and the output is connected to the second input of the third AND-NOT element, the bit information output of the memory unit is connected to the second information input of the control unit, the third information input of which is connected to the output of the comparator, the bit output of the additional memory unit is connected to the control input control unit, the first pulse input of which is connected to the counter overflow output, the counting input of the additional counter is connected to the second output of the synchronization unit, the third and fourth outputs of which are connected respectively to the inputs of the read and transmit data gates for recording the memory unit, the fifth and sixth outputs of the synchronization unit are connected respectively to the second and third pulse inputs of the control unit, the first and second pulse outputs of which are connected respectively to the reset and installation inputs of an additional counter, pulse input the recording unit of the memory is connected to the first pulse output of the device and to the third pulse output of the control unit, the fourth pulse output of which is the second pulse output device, the bit information input of the memory unit is connected to the first information outputs of the control unit and the device, the second information output of the device is the second information output of the control unit, the third information output of which is the output of the device ready signal.

 The authors are not aware of technical solutions containing features equivalent to distinctive features (introduction of an additional memory unit, additional counter, four NAND elements, a comparator, control unit equipped with eight inputs (reset, three information, one control and three pulse) and seven outputs (four pulse and three information), clock input, reset input, address code output of the input channel number, first pulse and information outputs of the write pulse and filter bit the current state of the sensor for input into adjacent systems, which are, respectively, the third pulse and first information outputs of the control unit, the second pulse and information outputs of a pulse for detecting a state change and bits of this state of the channel sensor for input to the system core, which are the fourth pulse and second information outputs of the block, respectively control and output signal readiness of the device, which is the third information output of the control unit) of the proposed device, allowing x him comprehensively provide noise-tolerant input of information into adjacent systems and / or into the core of the system.

 In FIG. Figures 1 to 4 show a functional diagram of a device for inputting information when it is implemented, in particular, for 64 input channels on an element base of integrated circuits (ICs) of the 1533 series, programmable memory ICs, for example, 541 PT1, 541 PT2 (or 556РТ4, 556РТ7 ) and a memory IC, for example, 537RU9A: Fig. 5 is a timing chart explaining the operation of the device during operation over time.

 The device for inputting information (Fig. 1) contains a memory unit 1, an additional memory unit 2, a counter 3, a switch 4 of signal states of input channel sensors, a synchronization unit 5, an additional counter 6, the first 7, the second 8, the third 9 and the fourth 10 elements AND-NOT, comparator 11, control unit 12, clock input 13 connected to the clock input of block 5, reset input 14 connected to reset inputs of counter 3 and blocks 5 and 12, address code output of input channel number connected to code input 15 counter 3, with address code inputs of memory unit 1 and switch 4 and with the inputs of the lower bits of the address of the memory block 2, the inputs of the high bits of the address of which are connected to the additional code output 16 of the counter 3, which is its highest code output, the outputs of the input channels, which are information inputs of the switch 4, the output of which is connected to the first input of the first element AND-NOT 7, the output of which is connected to the first inputs of the second 8 and third 9 AND-NOT elements, the first output 17 of block 5 is connected to the gating input of the selection of memory unit 1, with a counting input of the counter 3 and with the second inputs of the first of the 7th and second 8th elements NAND, the code output 18 of the memory unit 2 is connected to the first information input of the comparator 11, the second information input of which is connected to the information input of the additional counter 6 and to the information code output 19 of the memory unit 1, the information code input of which is connected with the information output 20 of the additional counter 6, the first information input of block 12 is connected to the output 21 of the third AND-NOT 9 element and to the first input of the fourth AND-NOT 10 element, the second input of which is connected to the output of the second ment AND-NOT 8, and the output with the second input of the third element AND-NOT 9, the information bit output 22 of the memory unit 1 is connected to the second information input of the control unit 12, the third information input of which is connected to the output 23 of the comparator 11, the bit output 24 of the block 2, the memory is connected to the control input of block 12, the first pulse input of which is connected to the output 25 of the counter overflow 3, the counting input of the additional counter 6 is connected to the second output 26 of block 5, the third 27 and fourth 28 of which outputs are connected respectively to the strobe inputs current and data transfer for recording block 1 of the memory, the fifth 29 and sixth 30 outputs of block 5 are connected respectively to the second and third pulse inputs of block 12, the first 31 and second 32 pulse outputs of which are connected respectively to the reset and installation inputs of an additional counter 6, input the write pulse of the memory unit 1 is connected to the third pulse output 33 of the block 12, which is the first pulse output of the device, the second pulse output of which is the fourth pulse output 34 of the block 12, the information bit input of the memory block 1 and connected to the first data output 35 the block 12, which is the first data output device, a second information output of which is the second information output unit 12, 36, a third information output 37 which is the output ready signal device.

 To automatically eliminate malfunctions during storage of the current results of the device’s operation, the memory unit 1 (Fig. 2) is designed as random access memory with majority redundancy, usually used / 18 / in highly reliable computing control systems, and contains the first, second and third random access memory elements 38, 39 and 40 (each of them is based on IS 537RU9A), the first, second, third and fourth controllable buffer transmitters 41, 42, 43 and 44 (each of them is made in the form of IS 1533AP5), group 45 of eight major tare elements (implemented on three IS 1533AP3), an address code input 15 connected to the address inputs of the elements 38 - 40, a gating input 17 of the selection connected to the inputs of the selection of the elements 38 - 40, an input 27 of the reading gate connected to the inputs of the resolution of the outputs of the elements 38 -40 and the transmitter 44, the input 28 of the data transmission strobe for recording, connected to the inputs of the resolution of the outputs of the transmitters 41-43, the input 33 of the write pulse connected to the control inputs for recording information in the elements 38-40, the information byte input formed by the code and bit input 20 and 35, respectively, and connected through transmitters 41, 42 and 43, respectively, with information inputs and outputs of elements 38, 39 and 40 connected respectively to the first, second and third information code inputs of group 45 of majority elements, the information output of which is connected through transmitter 44 with the information byte output of the memory unit 1 formed by the code and bit outputs 19 and 22, respectively.

 The memory unit 2 can be implemented, for example, on a single IC 541 PT2 (or 556PT7). Counters 3 and 6 can be performed on three and two IS 1533 IE7, respectively. Switch 4, when operating from signals of one TTL level, can be made on the basis of nine IS 1533 KP15, and to ensure the operation of the device according to signals of several types of levels, defined, for example, according to GOST 18977-79, its technical implementation applied should be used as a switch in / 17 / and supplemented with a memory unit (one IC 541РТ1 or 556РТ4) for generating the address code of a 3-digit level converter control code using the address code.

 The comparator 11 can be performed on the basis of two IS 1533SP1.

 Block 5 synchronization (figure 3) is implemented on the IS series 1533 to work on pulses of a clock frequency of 8192 kHz at input 13 and contains a counter 46, five elements AND-NOT 47-51, element NOT 52, three elements OR NOT 53-55 , two OR elements 56 and 57 and three software contacts 58-60, the clock input 13 and the reset input 14 of block 5 being connected to the counting and reset inputs of the counter 46, respectively, the first output 17 is connected to the output of the first AND-NOT 47 element, with the first the inputs of the elements OR NOT 53-55 and with the first input of the first element OR 56, the second output 26 is connected to the output of the second element a AND-NOT 48 and with the first input of the third AND-NOT 49 element, the third output 27 is connected to the output of the first OR 56 element, the fourth output 28 is connected to the output of the third AND-49 element and with the first input of the second OR 57 element, the output is zero (least) discharge of the counter 46 is connected to the second input of the first element OR-NOT 53 and to the first input of the fourth element AND-NOT 50, the second input of which is connected to the output of the first discharge of counter 46 and to the third input of the first element OR-NOT 53, the output of which connected to the first input of the second element AND-NOT 48, the output of the second bit the counter poison 46 is connected to the second inputs of the elements 48, 54, 56, with the first input of the fifth AND-NOT 51 element and with the input of the HE 52 element, the output of which is connected to the second input of the third OR-NOT 55 element, the outputs of the third and fourth bits of the counter 46 connected to the first and second inputs of the first AND-NOT element 47, the third input of which is connected to terminal 58, which is connected by soldering or with terminal 59 connected to the output of the fifth discharge of counter 46 or with terminal 60 connected to logic 1 bus (for example , power supply bus + 5V), fourth element output and AND-NOT 50 is connected to the third input of the second OR-NOT 54 element and to the second input of the fifth AND-NOT 51 element, the output of which is connected to the second input of the second OR 57 element, the second input of the third AND-NOT 49 element is connected to the output of the third element OR NOT 55, the outputs of the second elements OR NOT 54 and OR 57 are respectively the fifth 29 and sixth 30 outputs of block 5.

 A possible implementation of the control unit 12 (Fig. 4) comprises a logic function generator 61, executed, for example, on one IC 541 PT1 (or 556PT4), an OR element 62, triggers 63 and 64, elements NOT 65 and 66, elements OR_ NOT 67 and 68, an AND-NOT element 69 and an AND 70 element, the reset input 14 through the element NOT 65 connected to the reset input of the trigger 63, the information and installation inputs of which are connected to the installation input of the trigger 64 and to the logical bus "1", the first 21, the second 22 and third 23 information inputs of block 12 are connected to the inputs of the first three arguments the driver 61, the input of the fourth argument of which is connected to the first input of the element 67 and to the control input 24 of the block 12, the first output of the shaper 61 is connected to the first inputs of the elements 68 and 69, the outputs of which are the first and second pulse outputs 31 and 32 of the block 12, the first pulse the input 25 of which is connected to the clock input of the trigger 63, the inverse output of the trigger 63 is connected to the second input of the element 67, the second output of the driver 61 is connected to the first input of the element 70, the second pulse input 29 of the block 12 is connected to the input of the element 66 and to the second inputs elements 69 and 70, the output of element 66 is connected to the second input of the element 68 and to the clock input of the trigger 64, the output of element 67 is connected to the first input of the element 62, the second input of which is connected to the third pulse input 30 of block 12, the third and fourth pulse outputs 33 and 34 of which the outputs of the elements 62 and 70 are respectively, the direct output of the trigger 64 is the first information output 35 of the block 12, the second information output 36 of which is connected to the third output of the driver 61 and to the information input of the trigger 64, the reset input of which is single with the input of the fifth argument of the driver 61 and with the direct output of the trigger 63, which is the third information output 37 of the block 12.

 A description of the operation of the device is carried out using the system of positions and notation formulated in the following paragraphs.

 1. We use a modified description language of Boolean (logical) functions - ABEL, in which the operators "Conjunctions", "Disjunctions", "Inversions" and "EXCLUSIVE OR" are denoted by "&", "#". "!" and "$" respectively. For example, y =! X1 $! X2 means an EXCLUSIVE OR operation on two inverse variables.

 2. The address codes at outputs 15 and 16 of counter 3 are denoted by K15A = A0A1A2A3A4A5 and K16A = A6A7A8A9A10, respectively, where A0 is the lowest and A10 is the most significant bits of the 11-bit counter 3.

 3. At the outputs 18, 19 and 20 of the corresponding component parts of the device, the generated seven-digit data codes are denoted by K18D, K19D and K20D, respectively.

 4. The bit signals generated at the outputs of the corresponding component parts of the device will be denoted by the letters "x" and "y" (for example, the X21-bit of the sample state of the sensor of the input channel being processed, generated at the output of element 21 AND-NOT; y3 = x36 is a function generated at the third output of the shaper 61, which is the second information output 36 of block 12), and pulsed using the entries "C ... or! C ...", for example, direct C29 and inverse! C26 clock signals are generated respectively at the outputs 29 and 26 of block 5 according to FIG. 5.

 5. By the edge or fall of any signal (direct or inverse) is meant a change in the logical level of this signal from "0" to "1" or from "1" to "0", respectively - see Fig. 5.

 6. The signal (direct or inverse) means the appearance on the time axis of a "single" value of this signal. For example, the appearance and removal of the signal! C17 means that in the corresponding sections of the time axis t! C17 = 0 and! C17 = 1, respectively - see Fig. 5.

 Given the adopted system of positions and notation, we first describe the purpose and operation of the individual components of the device, and then its operation as a whole using time diagrams of FIG. 5.

 The memory block 1 with a usable capacity of 64 bytes is designed to store bit-filtered filtered state signals of X22 sensors of all channels and current codes K19D of multi-channel conversion of time intervals of the state signals of sensors of all channels into a code using the sequential counting method. The operation of block 1 (Fig. 2) is organized according to the signals! C17 selection,! C27 read strobe,! C28 data transmission strobe for recording and pulse! C33 recording so that during its operation three modes can be distinguished: storage at! C17 = 1: reading the information “K19D and X22” at address K15A with! C17 =! C27 = 0; write to the address K15A the information "K20D and X35" with! C17 =! C28 = 0 per pulse! C33 records.

где T_f - период частоты следования импульсов !C17;
T_n - длительность прохода адресов всех каналов ввода.Eleven-digit counter 3 is designed to generate pulses! C25 overflow, code K15A = A0A1A2A3A4A5 (where A0 is the least significant bit of the code) of the input channel address (number) and current code K18A = A5A7A8A9A10 input channel processing numbers during the cycle T _c :

where T _f is the period of the pulse repetition rate! C17;
T _n - the duration of the passage of addresses of all input channels.

 During operation, the counter 3 by the signal C14 is fixed in the state "0. ..0", in the absence of the signal C14, the contents of the counter 3 are increased by a unit of the least significant digit on each edge of the signal! C17. When overflowing, counter 3 generates a signal! C25, coinciding on the time axis with one of the pulses! C17.

В этой связи с помощью управляющего бита X24 каждый канал ввода в течение T_ц может быть опрошен от одного до 32 раз так, что для соответствующих каналов ввода при Z=32 бит X24=1 независимо от значения кода K16A, а при Z= 1. ..,31 бит X24=1 только при определенных значениях кода K1SA. Это основано на том, что при работе счетчика 3 по фронтам сигнала !C17 в течение T_ц биты A6, A7, A8, A9 и A10 переходят из "0" в "1" в разное время 16, 8, 4, 2 и 1 раз соответственно. Поэтому при Z < 32 блок 2 формирует для каждого канала ввода бит X24=1 в течение цикла равномерно (32 делится на Z без остатка) или квазиравномерно (32 делится на Z с остатком) Z раз как сумму состояний переходов из "0" в "1" соответствующих битов кода K1SA. Например, для конкретного канала ввода при Z=31 бит X24=1 при всех значениях кода K16A, кроме значения K16A = 11111, а при Z=17 сигнал X24=1 при K16A= 0XXXX (т.е. IS раз, где X - означает "0" или "1" в соответствующих битах кода K1SA) и при K16A= 11110 (т.е. всего один раз).The memory block 2, with a capacity of 2048 bytes, is designed to generate, according to the K15A and K1SA codes, for each K1SD code input channel a numerical threshold "P" for detecting a change in the status signal of the input channel sensor and the control bit signal X24, with the help of which the state signal will be converted into a code input channel sensor according to the method of sequential counting with a maximum error E _c and a time quantum T _c estimated according to the expressions

In this regard, using the control bit X24, each input channel during T _c can be interrogated from one to 32 times so that for the corresponding input channels with Z = 32 bits X24 = 1 regardless of the value of the code K16A, and with Z = 1. .., 31 bits X24 = 1 only for certain values of the K1SA code. This is based on the fact that when the counter 3 at the fronts of the signal! C17 for T _p bits A6, A7, A8, A9 and A10 change from "0" to "1" at different times of 16, 8, 4, 2 and 1 times respectively. Therefore, for Z <32, block 2 generates for each input channel the bit X24 = 1 during the cycle uniformly (32 is divided by Z without remainder) or quasi-uniformly (32 is divided by Z with remainder) Z times as the sum of transition states from “0” to “ 1 "corresponding bits of K1SA code. For example, for a particular input channel with Z = 31 bits X24 = 1 for all values of the K16A code, except for the value K16A = 11111, and for Z = 17 the signal X24 = 1 with K16A = 0XXXX (i.e., IS times, where X - means "0" or "1" in the corresponding bits of the K1SA code) and with K16A = 11110 (i.e., only once).

 Switch 4 is designed to select, during! C17 = 1, the input channel sensor status signal using the K15A code of the input channel address (number).

 The NAND 7-10 elements function as a trigger latch, from which, during! C17 = 0, bit X21 of the sample of the analyzed signal state of the sensor selected by switch 4 during! C17 = 1 is removed.

 An additional seven-digit counter 6 is designed to generate for! C17 = 0 by pulses C31 (or! C32) and! C26 the current result of converting the duration of the signal state of the input channel sensor into code K20D using code K190. This is done when! C17 = 0 so that first a reset pulse C31 (or! C32) is formed in the "0 ... 0" (or setting to the state K20D = K19D) counter 6. After that, a counter pulse arrives at counter 6! C26, along the edge of which the contents of counter 6 are increased by a unit of the least significant bit and then, with X24 = 1, it is written to the memory unit 1 by pulse! C33

Блок 5 синхронизации по сигналу C14 сбрасывается, а при C14=0 по тактовым импульсам ! C13 частоты 8192 КГц формирует шесть регулярных последовательностей импульсов !C17, !C26, !C27, !C28, !C29 и !C30 с частотой следования f= 256 КГц (или f=128 КГц) при замкнутых контактах 58 и 60 (или 58 и 59), т. е. при X58=1 (или X58=C5}. На основании фиг. 3 и 5 функционирование блока 5 при C14=0 можно описать полностью сводкой формул

где C0,...,C5 - формируемые счетчиком 46 сигналы разрядных цифр.Comparator 11 constantly compares codes K18D and K19D and generates bit X23 according to the expressions

Block 5 synchronization on the signal C14 is reset, and when C14 = 0 on clock pulses! A frequency C13 of 8192 KHz generates six regular pulse sequences! C17,! C26,! C27,! C28,! C29 and! C30 with a repetition rate of f = 256 KHz (or f = 128 KHz) with closed contacts 58 and 60 (or 58 and 59), that is, with X58 = 1 (or X58 = C5}. Based on Figs. 3 and 5, the functioning of block 5 with C14 = 0 can be completely described by a summary of formulas

where C0, ..., C5 are the digit signals generated by the counter 46.

 The control unit 12 (Fig. 4) is designed to generate four pulse signals C31,! C32,! C33 and C34 and three information signals X35 (filtered memorized sensor status signal). X36 = Y3 (filtered current sensor status signal) and signal X37, device ready.

 The operation of block 12 is carried out by a reset signal C14, three information signals X21, X22 and X23, a control signal X24 and three pulse signals! C25, C29 and! C30.

С учетом (5) формирование блоком 12 импульсных сигналов описывается формулами

Кроме того, по спаду каждого импульса C29 триггер 64 устанавливается в состояние X35=X36, определяемое в этот момент времени сигналом Y3=X36.In the process of operating on pulse C14, trigger 63 is reset and generates a signal X37 = 0, and then with C14 = 0 along the signal edge! C25 trigger 63 is set and sets signal X37 = 1 for the device to be ready. In General, the functioning of the block 12 is determined by the operation of the shaper 61, functioning according to the table. 1 truth. This shaper 61 can be performed, for example, on one IC 541 PT1 (or 556PT4), or on ordinary logic elements that generate functions Y1, Y2 and Y3 according to the formulas

In view of (5), the formation by the block 12 of pulse signals is described by the formulas

In addition, by the decline of each pulse C29, the trigger 64 is set to the state X35 = X36, determined at this point in time by the signal Y3 = X36.

 From (5) and (6) it follows that at (X24 #! X37) = 0, the device performs a dummy operation cycle, since in this case the pulses! C33 and C34 are not generated and the contents of the memory unit 1 are saved (see Section 2 table 1).

 In view of the foregoing, when X24 #! X37 = 1 (see Table 1, clause 1, clause 3-clause 10), during the operation of the device as a whole with! C17 = 0, three modes of its operation P1, P2 can be distinguished and P3 (Fig. 5), and in each of the modes, first, by the decay of the pulse C29, the trigger 64 is set to the state X35 = Y3 (where Y3 = X36 is defined in Table 1), and then formed using pulses C31 (or! C32) and! C26 the information "K20D and X35" is written by the pulse! C33 to the memory of block 1 at the address K15A of the input channel being processed.

 In this regard, the execution of the modes P1, P2 and P3 differs only in the formation by the counter 6 of the code K20D and the formation in P3 of the pulse C34.

 P1 mode in Table 1 corresponds to item 1, item 3, item 6, item 7 and item 10. In this mode, the code K20D = 1000000 is generated so that first, by pulse C31, counter 6 is reset, and then by the edge of the pulse! C26 its content is increased by a unit of the least significant bit.

P2 mode in the table. 1 correspond to clauses 4 and 5. In this mode, when reading from the memory of block 1 of the K19D code with! C27 = 0, a code is generated
K20D = K19D + 1,000,000 (7)
so that first, by pulse! C32, code K19D is written to counter 6. and then along the edge of the pulse! C26 the contents of counter 6 are increased by a unit of the least significant bit.

 P3 mode in Table 1 corresponds to p. 8 and p. 9. It is in the P3 mode that a pulse C34 of a change in the sensor status signal of the input channel processed at K15A is generated, and the K20D code is generated in P3 in the same way as in P1 mode.

 Thus, the mechanism for detecting a change in the sensor state of each input channel consists in counting in P2 mode up to a given number (P-1) of matching samples X21 (where P is the threshold defined by K18D code), otherwise, in P1 mode, initialization is performed and it all starts over. Therefore, the detection of a change in the signal state of the sensor of a certain input channel, marked by the formation of a pulse C34, will occur only if mode P2 is sequentially performed (P-1) for this channel, and then mode P3 is executed only once.

 During operation of the device, the current address code K15A and pulses! C33 records to adjacent systems can be transmitted filtered information (bit X35) of the status of each input channel, and by pulses C34 information about a change in the sensor status of any input channel addressed by K15A code can be transmitted to the system core. In addition, the X37 signal can be connected to one of the inputs of the switch 4 in order to inform the kernel of the system that the device is ready for the X37 bit to go from “0” to “1”.

где T_c и E_c - определены в (2);
P - числовой порог обнаружения, определяемый кодом K18D.To ensure the noise immunity of the device for each detected signal with a minimum duration T _x should be set the detection time threshold T _o defined by the expressions

where T _c and E _c are defined in (2);
P is the numerical detection threshold defined by the K18D code.

 In the table. 2 shows the time parameters of the functioning of the device, determined using (8).

It follows from (2), (8) and Table 2 that, in the general case, for a given T _{x, the} integers Z and P must be determined in the process of solving the following integer linear programming problem.

В процессе решения задачи ((9), (10)) для каждого конкретного T_x требуется определить целые числа Z и P, минимизирующие целевую функцию E_x при максимальном значении P из числа допустимых в (8).The linear equation is given
T _x - (P + 2) • T _c / Z = E _x , (9)
defining simultaneously the objective function E _x under constraints

In the process of solving problem ((9), (10)), for each specific T _x, it is required to determine the integers Z and P that minimize the objective function E _x at the maximum value of P from the number allowed in (8).

в противном случае переходят ко второму шагу:
- на втором шаге ищется максимальное число
P2=entP1/Z_i≤129, (13)
где варьируемой переменной является Z_i= 1...,31.The problem ((9), (10)) is solved by the directed search method in no more than two steps as follows:
- at the first step, an integer is determined
P1 = entT _x / T _n , (11)
where ent is the operator of selecting the integer part of a number;
for P1 ≤ 129, the desired solutions are

otherwise go to the second step:
- in the second step, the maximum number is searched
P2 = entP1 / Z _i ≤129, (13)
where the variable being varied is Z _i = 1 ..., 31.

 Based on (10), (11) and (13) from the set (1, ..., 31) we find the number Z and the threshold P = P2-2.

 Thus, this device allows providing noise-tolerant input of bit information both in adjacent systems and in the core in a complex manner, i.e. using both the detection of a change in the status signal of each input channel at the maximum threshold among the admissible ones and the automatic elimination of failures during storage in the memory unit 1 of the current results of the operation of the device.

Literature
1. Ushkar M.N. Microprocessor devices in electronic equipment / Ed. B. F, Vysotsky - M .: Radio and communications, 1988. - 128 p.: "Principles of building microprocessor means", p. (5-12).

 2. Kagan B. M., Stashin V. V. Fundamentals of designing microprocessor-based automation devices - M .: Energoatomizdat, 1987. - 304 p.: "Typical structure of a microprocessor-based device (system)" - p. (11-14).

 3. Microelectronic devices of automation / A.A. Sazonov, A.Yu. Lukichev, V.T. Nikolaev and others. Ed. A.A. Sazonova. - M.: Energoatomizdat, 1991. -384 p.: "Programmable controller" - p. (253 - 259).

 4. Kraus M., Kuchbach E., Voshni O.-G. Data collection in control computing systems. Per. with him. - M .: World. 1987. - 294 p.: "Data input devices", p. (83-87).

 5. Design of digital devices on single-chip microcontrollers / V.V. Stashin, A.V. Urusov, O.F. Mologontseva. - M .: Energoatomizdat, 1990. -224 s.: "Entering information from sensors", p. (128-139).

 6. Gitis E.I., Piskulov E.A. Analog-to-digital converters. - M .: Energoatomizdat. 1981. -360 p. : "Methods for constructing time interval to code converters", p. (140-158).

 7. Rafikuzaman M. Microprocessors and machine design of microprocessor systems: in 2 books. Prince 2. Trans. from English - M .: Mir, 1988. - 288 p.: "8279 / 8279-5-programmable keyboard and display interface" - p. (288 - 245).

 8. Auth. St. 1049891, G 06 F 3/02, USSR. Device for entering information / P.I. Borodin, D.N. Dudin and V.P. Sedinkin - Publ. 1983. Bull. N 39.

 9. A.S. 1080131, G 06 F 3/02, USSR. A device for entering information / "A. N. Murashko. - Published. 1984. Bull. N 10.

 10. A. p. 10895167, G 06 F 3/02, Device for entering information / V.V. Topilin. Publ. 1984, Bull. N16.

 11. A. p. 1105883, G 06 F 3/02, USSR. Device for entering information / Yu.V. Morozov and V.A. Zadorin. -Publish. 1984. Bull. N28.

12. A. p. 614434, M. Cl ² G 06 F 3/04, USSR. A device for collecting information from discrete sensors / M.M.Sukhomlinov, P.A. Voloshin and others. - Publ. 1978, Bull. N25.

13. A.S. 746439. M. Cl ² G 05 B 23/02, G 06 F 15/46, USSR. Device for collecting data from on-off sensors / B.A. Kalinichev. Publ. 1980. Bull. N25.

 14. A.S. 1109731, G 06 F 3/04, USSR. A device for collecting information from discrete sensors / V.M.Bykov and V.I. Gonoskov. Publ. 1984. Bull. N31.

 15. PROTOTYPE, A.S. 1086420, G 06 F 3/00, USSR. Device for entering information / V.A. Sechkin and V.I. Yuldashev. Publ. 1984. Bull. N 14.

 16. A. p. 1087979, G 06 F 3/04. THE USSR. Device for entering information / M.N. Golovanov, V.R. Duma, G.L. Levin, Yu.N. Rodin. Publ. 1984. Bull. N15.

 17. A. p. 1540544, G 06 F 13/00, USSR. A device for interfacing an electronic computer with discrete sensors / Yu.V. Kryukov and A.V. Kuznetsov. Publ. 1988.

 18. Ognev I.V., Sarychev K.F. Reliability of storage devices. - M .: Radio and communications. 1988. - 224 p.: "Majority backup of storage devices" - p. 155.156.

Claims (1)

 An information input device comprising a memory unit, a counter, a switch of state signals of input channel sensors, a synchronization unit and input channel outputs, which are information inputs of a switch, the address code input of which is connected to a code output of a counter, the input of which is connected to the first output of the synchronization unit, characterized in that an additional memory unit, an additional counter, four NAND elements, a comparator, a control unit, a clock input connected to the clock input of the C block are introduced into it synchronization, a reset input connected to the reset inputs of the counter and synchronization and control units, the address code output of the input channel number, the first pulse and information outputs of the write pulse and the filtered state bit of the channel sensor for input into adjacent systems, the second pulse and information outputs, respectively, of the pulse detecting the state change and the status bit of the channel sensor for input into the system core, and the output of the ready signal, and the counter code output is additionally connected to the address with the code output of the input channel number of the device, with the address code input of the memory block and with the inputs of the least significant bits of the address of the additional memory block, the inputs of the highest bits of the address of which are connected to the additional code output of the counter, which is its highest code output, the code output of the additional memory block is connected to the first information input of the comparator, the second information input of the comparator is connected to the information input of the additional counter and to the code information output of the memory block, codes the information input of which is connected to the code output of the additional counter, the output of the switch is connected to the first input of the first AND-NOT element, the output of which is connected to the first inputs of the second and third AND-NOT elements, the first output of the synchronization unit is additionally connected to the gating input of the memory block selection and with the second inputs of the first and second AND-NOT elements, the first information input of the control unit is connected to the output of the third AND-NOT element and with the first input of the fourth AND-NOT element, the second input of which is connected to the output of the second AND-NOT element, and the output is connected to the second input of the third AND-NOT element, the bit information output of the memory unit is connected to the second information input of the control unit, the third information input of which is connected to the output of the comparator, the bit output of the additional memory unit is connected to the control input control unit, the first pulse input of which is connected to the output of the counter overflow, the counting input of the additional counter is connected to the second output of the synchronization unit, the third and fourth outputs of which connected to the inputs of the read and transmit data gates for recording the memory unit, the fifth and sixth outputs of the synchronization unit are connected respectively to the second and third pulse inputs of the control unit, the first and second pulse outputs of which are connected respectively to the reset and installation inputs of an additional counter, input the write pulse of the memory unit is connected to the first pulse output of the device and to the third pulse output of the control unit, the fourth pulse output of which is the second pulse the output of the device, the bit information input of the memory unit is connected to the first information outputs of the control unit and the device, the second information output of the device is the second information output of the control unit, the third information output of which is the output of the device ready signal, and the memory block is a random access memory block and contains the first, second and third random access memory elements, the first, second, third and fourth controllable buffer lanes sensors, a group of majority elements, an address code input connected to address inputs of random access memory elements, a gating input connected to input inputs of random access memory elements, an input data transmission gate for recording, connected to output resolution inputs of the first, second and third buffer transmitters, an input a read gate connected to the input resolution inputs of the operational memory elements and the fourth buffer transmitter, a write pulse input connected to the operational recording inputs explicit memory elements, code and bit inputs connected through the first, second and third buffer transmitters respectively to information inputs / outputs of the first, second and third operational memory elements connected respectively to the first, second and third information code inputs of the group of major elements, information output which is connected through the fourth buffer transmitter with the code and bit outputs of the memory block.

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