RU2220502C2 - Serial-binary-to-parallel-serial code converter - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device provides for conversion of input serial code in range of code lengths including output of operation results in the form of fragments of parallelserial code, detection of information error and failure of bit synchronization, and generation of result availability signal by detecting programmable-threshold interval. EFFECT: simplified design and enlarged functional capabilities of converter. 1 cl, 2 dwg

Description

 The invention relates to the field of computer engineering and is intended to perform the operation of converting a serial binary code (word) belonging to a number of lengths into a parallel-serial code with the output of fragments (syllables) accompanied by a code of the fragment number and signals of readiness and synchronization of the fragment and the formation of control signals (an information error with an even number of units in the received code and a bit synchronization failure when the bit depth of the received code deviates from the selected row d yn) and the readiness of the operation result (the operation) by detecting a pause with a programmable threshold.

 The invention can be used to build devices for inputting information of the type [1] and local area network (CLS) controllers, for example, CLS based on GOST 18977-79 and RTM 1495-75, according to the protocols, which are the rules for the exchange of information [2, p. 57 -64] between stations of a local area network (SLS) via multiplex and / or separate communication lines with messages (sequential binary codes in a number of lengths {16, 24, 32} in bits with the least significant bits (bits) forward and the highest bit of parity control of the number of units in the lower discharges) separated by pauses 4-40 periods of duration T pulse repetition bit transmission timing of the message.

 As part of a modern SLS, one can distinguish (see, for example, [2] on p.221 of Fig. 5.9) a core (contains a processor or a single-chip electronic computer (computer), a synchronization and initial setup circuit, and a combined memory (in the general case, contains RAM - random access memory, DOS - dual-port RAM, ROM - read-only memory and RPM - programmable ROM)), CLS (contains a device for inputting information of the type [1], a device for outputting information, and an exchange control device (УУО) and synchronization ( communication unit hi with the subsystem) for mutual synchronization and control of the CLS as a whole), functionally oriented devices for input-output of information during the interaction of the CLS with external objects (operator console, adjacent systems, actuators, event sensors in control objects, etc.), a power source and a system bus (Q-BUS, ISA, VME or another) for the exchange of information between the components of the SLS under computer control.

 In general, the components of an information input device are a receiver (single-channel or multi-channel) of a self-synchronizing serial binary code, a decoder for generating a serial binary code and bit synchronization pulses, and a converter of a serial binary code to a parallel or parallel-serial code (bit / word block), and a device for outputting information in each channel contains a parallel binary code to serial binary code converter (block words / messages), encoder and transmitter.

 For the rational distribution of functions in the HFS between hardware and software, the converter of a serial binary code into a parallel-serial code (as a component of the HLC included in the HLS) should be flexibly controlled from the computer using the CID and be as invariant as possible to the type of system bus and LAN protocols , i.e. when improving CLS, the varied parts should be mainly UUOs, receivers, transmitters, encoders and decoders.

 It should be noted that when constructing digital equipment, the use of parallel-serial code (also called serial-parallel code) for transmission allows to save equipment [3, p.66-69], and the operation of converting a serial binary code to parallel (or parallel serial) code is implemented trivially, in particular, on a simple register of type 1533 ИР8 with serial input and parallel byte output or a universal byte register of type 1533 ИР24 for bidirectional exchange information with both sequential and parallel codes - see, for example, [4, p.103].

 However, in the CLS of each message receiving operation, a pause detection procedure must be preceded to prepare the device for inputting information for the next operation, and the process of each operation should be monitored (for example, generating information error signals with an even number of units in the received code and bit synchronization failure when rejecting bit depth of the received code from the selected number of lengths).

In this regard, the creation of a simple converter of serial binary code to parallel-serial code with wide functionality that provides flexible controllability from a computer with maximum independence from both the type of system backbone and the methods of exchanging information between computers and components of the CLS and LAN protocols, is , in our opinion, an urgent technical problem, the resolution of which will improve the quality of the developed CLS, including devices of the type [1], which support x in the local network with minimal hardware costs, high reliability of operation during the exchange of serial binary codes in the selected number of lengths, for example, in the bit series
{n} = {8, 16, ..., 120, 128}. (1)
Reliability of operation is a property of a digital device that characterizes the ability of controls to recognize the output of a device as correct or erroneous with the help of hardware-software controls [5, p.6], which ensure its suitability. Controllability - a property of a device that determines the adaptability of control of its technical condition during manufacturing and operation [5, p.153]. It is precisely controllability that makes it possible to obtain in practice the necessary reliability of the operation of information processing and control transmission systems [6, p.12], which in modern equipment are also subscribers (or stations) of local networks.

 The main disadvantage of the known converters [7-10] for their use in modern CLS is the limited or narrow specialization of their functionality.

 Indeed, the n-bit converter [7] is functionally equivalent to the register type 1533 ИР8, the (n + 2)-bit converter [9] is functionally also equivalent to the register 1533 ИР8, except that in it two high order bits are used to control bit synchronization at receiving an n-bit code, and the converters [8] and [10] are narrowly specialized, since the converter [8] is intended to be converted to parallel code of a sequential combined code, and the converter [10] is used to convert a serial two Nogo code BCD.

 Of the known technical solutions, the closest to the proposed one is the converter, which is part of the device [1] and contains n-bit shift register and buffer register of the parallel code, summing the counter, trigger, AND element, serial binary code input connected to the information input the shift register, the input of the bit synchronization pulses connected to the clock input of the shift register and the counting input of the totalizing counter, the overflow output of which is connected to the trigger setup input and the input behind write the buffer register, the parallel code output, which is the output of the buffer register, whose code input is connected to the shift register code output, the operation result ready reset input, connected to the buffer register and trigger reset inputs, the output of the operation result ready signal, connected to the trigger output and the first input of the AND-NOT element, a clock input connected to the second input of the AND-NOT element, the output of which is connected to the reset inputs of the shift register and the totalizing counter.

 The device Converter [1] operates as follows.

 Before starting the next conversion operation, it is in its initial state (pause mode) - shift register, buffer register, totalizing counter and trigger reset to zero states.

Upon receipt, serial information is transmitted to the shift register by bit synchronization pulses, which are counted by a summing counter. If the shift register is full, then the summing counter generates an overflow signal, which is a pulse of the start of a pause, according to which the contents of the shift register are sent to the buffer register and a trigger is set that sets the operation result ready signal to transmit the contents of the buffer register to the computer during the readiness time T1g <Tp, where Tn is the duration of the pause, ranging from 4T to 40T of periods T of the pulse repetition rate of the bit synchronization pulses. By the signal of readiness of the result of the operation, clock pulses pass through the AND-NOT element and reset the shift register and the totalizing counter, and the computer, after reading the result of the operation (the contents of the buffer register), sets the converter to its initial state by resetting the buffer register and the trigger with the signal from the reset ready reset input operations. Therefore, the computer during the time T1g readiness duration
40T>T1g> 3T (2)
must complete all exchange operations with the device, which will be ready for the next operation only upon completion of the operation readiness reset signal from the computer.

 The main disadvantage of the converter [1] is its complexity, which is proportional to the bit width n of the shift register and buffer register, and the limited functionality of it (there is no possibility of converting the input code in a number of lengths, for example, in a number of (1), and controlling the operation of the converter), as well as relatively small minimum availability time (2) and loss of controllability of the transformation for an indefinite time when the bit synchronization fails, especially in the direction of decreasing from a fixed length n of the transformation, since the ready signal (pause) is generated by the overflow of the totalizing counter, and not by the real absence of bit synchronization pulses. It is easy to see that when the trigger is installed, the serial information coming to the converter is completely lost, because the I-NOT element constantly resets the shift register and the totalizing counter by the signal of readiness of the result of the operation and clock pulses.

 The present invention solves the problem of simplifying the converter and expanding its functionality by providing the possibility of converting the input code in a number of lengths with the output of the operation by fragments of a parallel-serial code accompanied by a code of the fragment number and signals of readiness and synchronization of the fragment, as well as the formation of control signals for the functioning of the converter ( information error with an even number of units in the input code and bit synchronization failure when deviating times the input signal (from the established number of lengths) and the signal of readiness of the result of the operation by detecting a pause with a programmable threshold.

 To achieve this technical result, a serial binary to parallel-serial code converter containing a first trigger, a shift register, a first AND-NOT element, a totalizing counter, clock inputs, bit synchronization pulses, a serial binary code, and resetting the result of the operation and signal output the readiness of the result of the operation, connected to the output of the first trigger and the first input of the first AND-NOT element, an EXCLUSIVE OR element is added, second-to-fifth triggers p, pause detector, OR-NOT element, second to fifth NAND elements, first OR element, three AND elements, initial reset input, programmable pause detection threshold code input connected to the pause detector code input, fragment ready signal outputs, fragment synchronization, information error and bit synchronization failure, code output of the parallel-serial code fragment number, which is the information output of the summing counter, the transfer output of which is connected to the first input of the first AND element , and the output of a parallel-serial code fragment, the output of the highest bit of which is connected to the output of the second trigger and the serial information input of the shift register.

 The outputs of the upper bits of the shift register are connected to the outputs of the lower bits of a fragment of a parallel-serial code, the output of the least significant bit of which is connected to the second input of the first AND element, the output of which is connected to the first input of the second AND element and the clock input of the first trigger, the information input of which is connected to bus LOGIC "0" of the converter, the clock input of which is connected to the clock input of the pause detector, the input of the installation of which in the detection mode is connected to the input of the pulse synchronization bits converter, the third input of the first AND-NOT element, the direct input of the second AND-NOT element and the first input of the third AND-element, the second input of which is connected to the inverse input of the second AND-element and the output of the first AND element, the second input of which is connected to direct input of the fourth AND-NOT element, the first input of the first OR element, synchronous mode control input, parallel write / shift to the right of the shift register, the low-order output of the shift register and the output of the parallel-serial fragment ready signal ode converter input serial binary code, which is connected to the data input of second flip-flop and the first input of the EXCLUSIVE OR gate.

 The output of the latter is connected to the information input of the third trigger, the output of which is connected to the second input of the EXCLUSIVE OR element and the information input of the fourth trigger, the clock input of which is connected to the output of the synchronization signal of the fragment of the parallel-serial converter code and the output of the fifth AND-NOT element, the first input of which is connected with the counting input of the totalizing counter and the output of the fourth AND-NOT element, the inverse input of which is connected to the output of the second AND-NOT element and the clock inputs of the second and a third trigger and a shift register, the parallel information input of which is connected to the input of the converter constant code, which has the highest digit one and the remaining bits are zero, the output of the fourth trigger is connected to the output of the information error signal of the converter, the output of the bit synchronization failure signal of which is connected to the output of the fifth trigger the inverse input of the installation of which is connected to the output of the third AND element, the first input of which is connected to the output of the third AND element, the second input of the third AND element is connected to the output of the first OR element, the first output of the pause detector is connected to the second inputs of the fifth AND-NOT element and the first OR element and the asynchronous inverse input of the installation of the first trigger, the asynchronous inverse reset input of which is connected to the output of the OR-NOT element and the second input of the second AND element whose output is connected to the asynchronous inverse inputs of the installation of the fourth trigger and reset the totalizing counter and the fifth trigger.

 The second output of the pause detector is connected to the asynchronous inverse inputs of resetting the shift register and setting the second and third triggers, the first input of the OR-NOT element is connected to the input of the readiness reset of the result of the operation of the converter, the initial reset input of which is connected to the second input of the OR-NOT element and the installation input to pause state of the pause detector, which contains clock inputs, pause detection settings, pause settings, first and second outputs, element NOT, sixth element AND NOT subtracting the count a chick, the second, third and fourth OR elements and a code input that is connected to the information inputs of a subtracting counter, the outputs of the highest digits of which are connected to the inputs of the second OR element, the output of which is connected to the first inputs of the third and fourth OR elements, the clock input of the detector is connected to the first the input of the sixth AND-NOT element, the output of which is connected to the counting input of the subtracting counter and the second input of the third OR element, the output of which is the first output of the detector, the second output of which is connected with the second input of the sixth AND-NOT element and the output of the fourth OR element, the second input of which is connected to the low-order output of the subtracting counter, whose asynchronous inverse recording input is NOT connected through the element to the setup input to the detector pause detection mode, the setup input to the pause state of which is connected with asynchronous reset input of subtracting counter.

 The authors are not aware of technical solutions containing features equivalent to distinctive features (introduction of an EXCLUSIVE OR element, second to fifth triggers, pause detector, OR-NOT element, NAND elements from second to fifth, first OR element, three AND elements, initial input reset, programmable code input of the pause detection threshold, output of a fragment of a parallel-serial code and outputs of a code of a fragment number of a parallel-serial code and signals of readiness and synchronization of a fragment, information hydrochloric error and bit synchronization failure), allowing its use in the construction of simple hardware KLS supporting with high reliability in a local network exchange successive binary codes of different lengths belonging to, for example, a number of type (1).

 In FIG. 1-2, a functional diagram of the converter of a serial binary code into a parallel-serial code is shown when it is implemented, in particular, using a library of integrated circuit elements (ICs) of the 533 series for working with input codes whose lengths correspond to series (1).

 The converter of the serial binary code into parallel-serial code (Fig. 1) contains the first trigger 1, byte register 2 of the shift, the first element 3 AND-NOT, summing the counter 4, element 5 EXCLUSIVE OR, triggers from the second 6 to the fifth 9, detector 10 pauses, element 11 OR NOT, elements NAND from second 12 to fifth 15, first element 16 OR, three elements AND 17-19, clock input 20, input 21 pulses of bit synchronization, input 22 of a serial binary code, input 23 of reset readiness of the result of the operation, input 24 initial reset, programmable the pth code input of the pause detection threshold connected to the code input of the detector 10, the output 25 of the signal of readiness of the result of the operation, connected to the output of the trigger 1 and the first input of the element 3, the outputs 26, 27, 28 and 29, respectively, of the signals of fragment readiness, fragment synchronization, information error and failure of bit synchronization, the output 30 of the transfer of the counter 4 connected to the first input of the element 17, the first 31 and second 32 outputs of the detector 10, the output of the code number of the fragment of the parallel-serial code, which is an information output ohm counter 4, and the output of a fragment of parallel-serial code, the output of the highest bit of which is connected to the output of trigger 6 and the serial information input of register 2.

 The outputs of the upper bits of the register are connected to the outputs of the lower bits of a fragment of a parallel - sequential code, the output of the least significant bit of which is connected to the second input of element 3, the output of which is connected to the first input of element 18 and the clock input of trigger 1, the information input of which is connected to the LOGIC "0" bus the converter, the clock input 20 of which is connected to the clock input of the detector 10, the input of the installation of which in the detection mode is connected to the input 21 of the pulse bits of the synchronization of the Converter, the third input m of element 3, the direct input of element 12 and the first input of element 13, the second input of which is connected to the inverse input of element 12 and the output of element 17, the second input of which is connected to the direct input of element 14, the first input of element 16, the synchronous mode selection input, parallel recording / shift to the right of register 2, the output of the least significant bit of register 2 and the output 26 of the ready signal of a fragment of the parallel-serial code of the converter, the input of the 22 serial binary code of which is connected to the information input of trigger 6 and the first Odom element 5, whose output is connected to the data input of flip-flop 7, the output of which is connected to the second input member 5 and the data input of flip-flop 8.

 The clock input of the trigger 8 is connected to the output 27 of the synchronization signal of the fragment of the parallel-serial code of the converter and the output of the element 15, the first input of which is connected to the counting input of the counter 4 and the output of the element 14, the inverse input of which is connected to the output of the element 12 and the clock inputs of the triggers 6 and 7 and register 2, the parallel information input of which is connected to the input of the constant code of the converter, which has the highest digit one and the remaining bits are zero, the output of trigger 8 is connected to the output 28 of the information signal the error of the converter, the output 29 of the bit synchronization failure signal of which is connected to the output of the trigger 9, the inverse input of which is connected to the output of the element 19, the first input of which is connected to the output of the element 13, the second input of the element 19 is connected to the output of the element 16, the output 31 of the detector 10 connected to the second inputs of the elements 15 and 16 and the asynchronous inverse input of the trigger 1, the asynchronous inverse reset input of which is connected to the output of the element 11 and the second input of the element 18, the output of which is connected to the inverse asyn the chronic inputs of the installation of trigger 8 and reset the counter 4 and trigger 9, the output 32 of the detector 10 is connected to the asynchronous inverse inputs of the reset of register 2 and the installation of triggers 6 and 7, the first input of element 11 is connected to the input 23 of the reset ready result of the operation of the converter, input 24 of the initial reset which is connected to the second input of the element 11 and the input of the installation in the pause state of the detector 10.

 The pause detector 10 (FIG. 2) contains clock inputs 20, 21 and 24, pause detection and pause settings, the first 31 and second 32 outputs, element 33 NOT, the sixth element 34 AND NOT, the first input of which connected to the clock input 20, subtracting counter 35, second 36, third 37 and fourth 38 elements OR and a code input that is connected to the information inputs of the counter 35, the outputs of the senior bits of which are connected to the inputs of the element 36, the output of which is connected to the first inputs of the elements 37 and 38, the output of element 37 is output an ode 31 of the detector 10, the output of which 32 is connected to the second input of the element 34 and the output of the element 38, the second input of which is connected to the low-order output of the counter 35, whose inverse asynchronous recording input is connected through the element 33 to the input 21 of the detector pause detection mode of the detector 10, the input 24 of the installation in a pause state which is connected to the asynchronous reset input of the counter 35.

 When implementing the Converter (Fig.1-2) in the library of elements of the IC series 533, you can execute triggers 1, 6-8 on two TM2 ICs, and for triggers 6-8 asynchronous inverse reset inputs must be connected to the LOGIC "1" bus of the converter ( in Fig. 1 it is not shown); register 2 is made on two IR11A ICs, which form a byte register with asynchronous inverse reset and synchronous operation along the edges of the pulses at the clock input or in the parallel code recording mode (10 ... 0) of the constant at W = 1, or in the input serial input mode code from the output of the trigger 6 by lower digits forward (i.e., with a shift to the right) at W = 0, where W is the signal of the operating mode of register 2 at the corresponding input of each of the IR11A, which is a four-bit reverse shift register with parallel output house, synchronous serial-parallel input and asynchronous inverse reset.

 Counter 4 is performed on IE IE10, a four-digit binary counter with asynchronous inverse reset; counter 35 is made on IE IE7 — a four-digit binary reversible counter with an asynchronous reset input and an asynchronous inverse download input to the code counter from parallel information inputs; other components of the device are made on combinational elements of the respective ICs, in particular trigger 9 is implemented on two elements 2I-NOT IS LA3.

 A description of the operation of the converter is carried out using the system of positions and designations defined in the following paragraphs.

 1. Input, intermediate (formed at the outputs of the corresponding components of the converter) and output (formed at the outputs of the converter) direct (or inverse) variables are denoted by Xi, Zj (or NZj) and Yk (or NYk), respectively, where the number from the set { i, j, k} means either the input number, or the component number, or the output number of the converter or its component. For example, X20 - clock pulses at the clock input 20, X21 - pulses at the input 21 of the bit synchronization pulses; NZ12 and NZ13 are inverse pulses at the outputs of the elements 12 and 13, respectively; Y25 = Z1 is the signal of the readiness of the result of the operation at the output 25 of the converter, Y30 is the signal at the output 30 of the transfer of the counter 4, NY31 and NY32 are the inverse pulse of the start of a pause and the inverse signal of a pause at the outputs 31 and 32 of the detector 10. In addition, the codes at the output a fragment of a parallel-serial code, the output of the code of the number of the fragment of the parallel-serial code, the output of the counter 35 and the code input of the detector 10 are denoted by G (7: 0) = G7 ... G0, C (3: 0) = C3 C2 C1 C0, respectively , СР (3: 0) = СР3 СР2 СР1 СР0 and Р (3: 0) = Р3 Р2 Р1 Р0, where G0, С0, СР0 and Р0 are junior, and G7, С3, СР3 and Р3 are high-order digit digits (i.e. 0 or 1) of these codes.

 2. A modified description language of Boolean (logical) functions ABEL is used, in which the operators "Conjunctions", "Disjunctions", "Inversions" and "Exclusive OR" have the notation "&", "#", "!" and "$" respectively. For example, elements 12 and 17 form the variables NZ12 and Z17 according to the expressions NZ12 =! [(! Z17) & X21] and Z17 = Y30 & Y26, respectively.

 3. The front or the fall of any signal (direct or inverse) is understood as the change in the logical value of this signal from "0" to "1" or from "1" to "0", respectively.

 4. By resetting (or setting), for example, trigger 9, we mean switching this trigger to “0” (or “1”).

5. During the operation of the converter, a signal Y25 is prepared for the result of the operation and a pause signal NY32 so that the following four modes of operation can be distinguished:
PP0 standby (idle) at Y25 NY32 = 00 (3),
PP1 conversion at Y25 NY32 = 01 (4),
PP2 readiness at Y25 NY32 = 10 (5),
PP3 readiness and conversion at Y25 NY32 = 11 (6).

 Given the adopted system of provisions and notation, we first describe the operation of the converter as a whole as a finite state machine with memory, and then the operation of its components.

 The initial state of the converter is PP0 mode (3), in which triggers 1 and 9, counter 4 are reset, trigger 8 is set, register 2 is reset by inverse signal NY32 = 0 pauses, triggers 6 and 7 are set. The installation of the converter in its initial state is carried out either when the equipment is turned on by the signal X24 = 1 of the initial installation, or when switching from PP2 mode (5) by the signal X23 = 1 of the readiness reset of the operation result.

Each conversion operation begins when a sequence of П pulses X21 of bit synchronization and signal X22 of a serial binary code, the length of which in bits must belong to series (1), is received at inputs 21 and 22, i.e. for the correct functioning of the converter, the number П must also belong to the series (1). Directly by the first pulse X21 of the sequence П, the detector 10 is set to the pause detection mode (by the first, and then for each pulse NZ33 =! X21 = 0, the code CP (3: 0) = P (3: 0) of the pause detection threshold is loaded into the counter 35 ) and the converter goes into conversion mode PP1 (4), in which elements 12-14 generate inverse pulses according to the expressions
NZ12 =! [(! Z17) & X21], (7)
NZ13 =! [Z17 & X21], (8)
NZ14 =! [Y26 & Z12], (9)
where Y26 is the signal switching to "1" on the decline (or edge) of each multiple of eight pulses X21 (or NZ12) of the sequence P, where the number P belongs to series (1).

On the front of each pulse NZ12 =! X21, triggers 6 and 7 are set to
Z6 = G7 = X22 (at the moment of front NZ12), (10)
Z7 = X22 $ Z7 (at the moment of front NZ12), (11),
and the contents of register 2 with Y26 = 0 are shifted to the right with the reception of the bit G7 = Z6 (at the moment of the front NZ12) to the upper bit G6, and with Y26 = 1 the highest bit G6 of register 2 is set, and the lower bits are reset, i.e. G (6: 0) = (1,000,000), Y26 = 0.

Therefore, after the end of the 8th, 16th, ..., 120th, 128th pulses of NZ12 (7), register 2 will set the signal Y26 = 1 for the readiness of the fragment of the 0th, 1st, ..., 14 and the 15th output G (7: 0) parallel-serial code and the following states will be established:
G (7: 0) = D (7: 0), D (16: 8), ..., D (119: 112) and D (127: 120), (12)
C (3: 0) - (0000), (0001), ..., (1110) and (1111), (13)
and then an impulse will form
Y27 = Z15 = (! NZ14) # (! NZ31) = Z14 # Z31 (14)
synchronization of fragment G (7: 0) of a parallel-sequential result code (12) for the 9th, 17th, ..., 121 pulses NZ12 =! X21 and inverse pulse NZ31 for detecting a pause. On the front of each pulse Y27 (14), trigger 8 is set to
Y28 = Z8-Z7 (at the moment of front Y27), (15)
and also the corresponding fragment G (7: 0) of the result (12) of the operation can be removed from the converter. In the process of performing the operation, element 19 generates an inverse impulse at П not belonging to set (1)
NZ19 = NZ13 & (Y26 # NZ31), (16)
so that NZ19 = NZ13 (or (Y26 # NZ31)) at P> 128 (or at P <128 and not a multiple of eight). By pulse NZ19 = 0, trigger 9 is set and sets the signal Y29 = 1 bit synchronization failure.

 During the conversion time along the edge of each pulse NZ12 (or Y27), trigger 7 (or 8) with X22 = 1 switches to the opposite state (11) (or to state Z7). Therefore, after the end of the sequence of pulses X21 of bit synchronization and at the end of the pulse front Z27 =! NZ31, triggers 7 and 9 are in the same states (i.e., Z7 = Z8 = Y28) and there is no information error at Y28 = 0, and at Y28 = 1 an informational error was detected, i.e. an even number of units in the converted input binary sequence code X22.

In addition, trigger 1 is set directly by the inverse pulse NY31 = 0 and sets the signal Y25 = Z1 = 1 for the readiness of the operation result
{D ((n-1): 0), C (3: 0), Y25, Y28, Y29}, (17)
where n belongs to the set (1).

 At the end of the NY31 pulse, the detector 10 sets the inverse signal NY32 = 0 to pause, and the converter goes into PP2 mode (5), in which the computer is interrupted by signal Y25 = 1 to signal the completion of the next conversion operation and to remove the code C (3: 0) of the number the last fragment G (7: 0) of the parallel code D ((n-1): 0) and signals Y28 (15) of the information error and Y29 bit synchronization failure. During the execution of the interrupt program, the computer generates a result ready reset signal X23, which, through element 11, resets trigger 1, and through elements 11 and 18, resets counter 4 and trigger 9, sets trigger 8 and switches the device to its initial state - PP0 mode (3).

If the computer does not generate a signal X23 = 1, then the converter switches to PP3 mode (6) with the arrival of its next sequence of P pulses X21 bit synchronization and signal X22 of a serial binary code. In this mode, at the end of the 7th pulse NZ12 =! X21, register 2 sets the signal G0 = 1, with the help of which elements 3 and 18 form inverse pulses on the 8th pulse X21
NZ3 =! (Y25 & G0 & X21), (18)
NZ18 =! (Z3 # X23 # X24). (19)
Directly by pulse NZ18 = 0, counter 4 and trigger 9 are reset, trigger 8 is set, and at the end of pulse NZ3 = 0, trigger 1 is reset (generates signal Y25 = Z1 = 0), and the converter goes into PP1 mode (4), described earlier.

 Thus, the functioning of the converter as a finite state machine with memory consists in the alternation of its operating modes, for example, PP0, PP1, PP2, PP3, PP1, etc., so that the transition to PP0 can be carried out from any other mode by the initial signal X24 reset either from the PP2 mode by the signal X23 of the result ready reset, in PP1 - from the PP0 mode directly by the first pulse X21 of the sequence of P pulses X21 bit synchronization or from the PP3 mode directly by the signal X23 or at the end of the inverse pulse NZ3 (18), in PP2 - only from PP1 mode at the end of the inverse pulse NY31, in PP3 - only from PP2 for the first pulse X21.

 The functioning of the individual components of the Converter is as follows.

 Trigger 1 on the inverse pulse NY31 is set, and is reset either by the inverse signal NZ11 =! (X23 # X24), or by the edge of the pulse NZ3 (18).

 Register 2 for the inverse signal NY32 = 0 pauses is fixed at zero, and for NY32 = 1 along the edge of each inverse pulse NZ12 (7) the contents of register 2 with Y26 = 0 (or Y26 = 1) are shifted to the right with the reception of the G6 bit G7 = Z6 (or becomes equal to the code (10000000) of the converter constant), where Y26 is the value of the least significant bit of register 2.

Counter 4 for the inverse signal NZ18 = 0 (19) is fixed at zero, and with NZ18 = 1 at the end of each inverse pulse NZ14 (9) the contents of counter 4 (code C (3: 0)) increases by one and a signal is generated at output 30 carry
Y30 = C0 & C1 & C2 & C3. (20)
Trigger 6 (or 7) is set to the inverse signal NY32 = 0; pause is set, and when NY32 = 1, trigger 6 (or 7) functions according to (10) (or (11)).

 Trigger 8 operates according to (15).

 The trigger 9 for inverse pulses NZ19 (16) and NZ18 (19) is set and reset, respectively.

The detector 10 (figure 2) generates an inverse pulse NY31 detect pause and inverse signal NY32 pause according to the expressions
NY31 = [! (X20 & CP0)] # CP1 # CP2 # CP3, (21)
NY32 = CP0 # CP1 # CP2 # CP3, (22)
so that it is paused at NY32 = 0, and at pause detection at NY32 = 1, which ends at the end of the NY31 pulse edge. From figure 2 and (21) it follows that the pulse NY31 is generated by the clock pulse X20 when the counter 35 is in the state CP (3: 0) = (0001), and the pause signal NY32 = 0 is set when the counter 35 is in the state CP ( 3: 0) = (0000), in which the counter 35 can be fixed by the signal X24 = 1 of the initial reset. At X24 = 0, the counter 35 according to the code P (3: 0) and inverse pulses NZ33 =! X21 and NZ34 =! (X20 & NY32) operates as follows. With each pulse NZ33 = 0, counter 35 is fixed in the state СР (3: 0) = Р (3: 0), which defines the detection threshold Р as a number according to the expression
P = P0 + 2P1 + 4P2 + 8P3. (23)
When there is a pause, the formation of pulses NZ33 =! X21 stops, and with NY32 = 1, element 34 generates exactly P (23) pulses NZ34 (counted from the last pulse NZ33 = 0), along the front of each of which the content of counter 35 decreases by one, and by the pulse P of this sequence generates a pause detection pulse NY31 (21), after which the counter 35 switches to the state CP (3: 0) = (0000), the detector 10 sets the pause signal NY32 = 0 and blocks the operation of the element 34 by clock pulses X20. In the paused state, the detector 10 remains until it receives the next sequence of P pulses X21 bit synchronization. In this regard, the detection threshold P (23), the frequency F20 = kxF21 of the clock pulses X20 and the pulse repetition rate F21 X21 of the bit synchronization must be selected from the condition
2 / F21> P / F20> 1 / F21 = T (24).

a variation of two numbers k> 1 and P> 2, providing the duration T0 of the temporary threshold for detecting pauses according to the expression
To = P / F20 = P / (kxF21) = T (P / k), (25)
where k is the coefficient of proportionality;
x and / are the operators of arithmetic operations of multiplication and division, respectively.

According to the impulse NY31 = 0, trigger 1 sets the signal Y25 = 1 for the readiness of the result, the duration of which is maximum in the absence of the signal X23 from the computer and taking into account condition (24) at Тп = 4Т is estimated by the expression
T25g = 10 T. (26)
Comparing (2) and (26), we obtain
T25g / T1g> 2.5, (27)
that the duration of the availability time T25g (26) of the operation result of the proposed converter is several times higher than the duration of the availability time T1g (2) of the prototype [1].

 It is easy to see that in the general case, the proposed converter is hardware much simpler than the prototype [1], since the prototype contains multi-bit (n-bit) buffer register and shift register, the capacity of each of which is many times larger than the capacity of the shift register of this converter (for example, for n = 128 16 times).

 The presence at the outputs of the converter of the ready signal Y26 and the synchronization pulse Y27 (14) of each fragment G (7: 0) of a parallel-serial code (see its form in (12) with n = 128) provides many options for transmitting the result of the operation to the computer via the UUO (17).

 We describe two possible options for entering the result (17), respectively, according to pulses Y27 (14) and signals Y26 of the readiness of fragments.

 In the first case, in the CID, along the edge of each pulse Y27, the current fragment G (7: 0) is loaded into the register of type IR23 and causes an interruption of the computer of the first type. When executing the first interrupt program, the computer generates code D ((n-1): 0) in its RAM. At the end of each operation, the converter sets the signal Y25 = 1 and causes an interruption of the second type of computer. When executing the second interrupt program, the computer reads the remaining part {C (3: 0), Y28, Y29} of the result (17), generates a signal X23 = 1 for resetting the result, then the computer sends Y28 # Y29 = 0, for example, the information part of the code D ((n-1): 0) to the subscriber (receiver), and with Y28 # Y29 = 1 the result is ignored, because an error was detected in the code D ((n-1): 0) with Y28 = 1 or / and the bit synchronization fails with Y29 = 1.

 In the second case, the CID for each signal Y26 = 1 and code C (3: 0) writes each fragment G (7: 0) of the code D ((n-1): 0) into the RAM (RAM, DOS or hardware stack). At the end of each operation, the converter sets a computer interrupt signal Y25 = 1, which during T25g (26) executes the interrupt program similar to the second interrupt program described for the first case.

 Thus, the proposed converter, due to its essential features, is simpler than the prototype [1] and, in comparison with it, has wider functionality due to the possibility of converting the input binary binary code in a number of lengths of type (1) with the detection of an information error and a bit synchronization failure, and a wide variety of options for inputting into computer the result (17) with an increased time (26) of the readiness of the result of the operation several times (see estimate (27)). In this regard, this converter can be used to build hardware-simple CLSs that support the exchange of serial binary codes with both fixed and various lengths belonging, for example, to series (1) with high reliability in a local network.

Literature
1. A.S. 1786491, M.cl. G 06 F 13/00, USSR. Device for entering information. D.Yu. Gusev and Yu.V. Hooks. Publ. 01/07/1993. Bull. 1 (prototype).

 2. Organization of serial multiplex channels of automatic control systems. S.T. Horsetail, V.V. Doroshenko, V.V. Mount. Under the total. ed. S.T. Horsetail. - Engineering. Leningrad Separation, 1989 .-- 271 p., Ill.

 3. Kagan B. M. - Electronic computers and systems: textbook for universities. - 3rd ed., Revised. and additional - Energoatomizdat, 1991 .-- 592 p., ill.

 4. Yu. V. Novikov, D.G. Karpenko. The equipment of local area networks: functions, selection, development. Edited by Yu.V. Novikov. - M.: Publishing house ECOM, 1998. - 288 pp., Ill.

 5. Scherbakov N. S. Reliability of digital devices. - M.: Mechanical Engineering, 1989.222 s., Ill.

 6. Monitoring the functioning of large systems. G.P. Shibanov, E.A. Artemenko, A.A. Mateshkin, N.I. Tsiklinsky. Ed. Honored Inventor of the RSFSR Doctor of Technical Sciences G.P. Shibanova. - M.: Mechanical Engineering, 1977, 360 p.

 7. A. p. 822175, M.C. 3 G 06 F 5/04, USSR. Convert serial code to parallel code. Yu.A. Pluzhnikov, E.A. Evseev, V.I. Kosogorov and A.N. Hunchbacks. Publ. 04/15/1981. Bull. 14.

 8. A. p. 1078424, M.C. G 04 F 5/04, USSR. Converters sequential combined code to parallel binary code. V.D. Gladkov. Publ. 03/07/1984. Bull. 9.

 9. A.S. 1081639, M.C. G 06 F 5/04, USSR. A device for converting serial code to parallel. IN AND. Soloviev and A.E. Kravets. Publ. 03/23/1984. Bull. eleven.

 10. A. p. 1084780, M.cl. G 06 F 5/02, USSR. Convert serial binary code to parallel binary decimal code. E.A. Shurmukhin and K.V. Queen. Publ. 04/07/1984. Bull. thirteen.

Claims (1)

A serial binary to parallel-serial code converter containing a first trigger, a shift register, a first AND-NOT element, a totalizing counter, clock inputs, bit synchronization pulses, a binary binary code, and an operation result readiness reset signal and an operation result ready signal output connected to the output of the first trigger and the first input of the first AND-NOT element, characterized in that it further comprises an EXCLUSIVE OR element, second to fifth triggers, pause detector, OR element, NAND elements from second to fifth, first OR element, three AND elements, initial reset input, programmable code input of the pause detection threshold, connected to the code input of the pause detector, outputs of the fragment ready signals, fragment synchronization, information error and bit synchronization failure, the output of the code of the fragment number of the parallel-serial code, which is the information output of the summing counter, the transfer output of which is connected to the first input of the first AND element, and the output of the fragment of pairs allele-sequential code, the output of the highest bit of which is connected to the output of the second trigger and the serial information input of the shift register, the outputs of the highest bits of which are connected to the outputs of the lower bits of the fragment of the parallel-serial code, the output of the least significant bit of which is connected to the second input of the first NAND element, the output of which is connected to the first input of the second AND element and the clock input of the first trigger, the information input of which is connected to the LOGIC “0” bus of the converter, the input of which is connected to the clock input of the pause detector, the input of setting which to the detection mode is connected to the input of the bit synchronization pulses of the converter, the third input of the first AND-NOT element, the direct input of the second AND-NOT element and the first input of the third AND-NOT element, the second input which is connected to the inverse input of the second AND-NOT element and the output of the first AND element, the second input of which is connected to the direct input of the fourth AND-NOT element, the first input of the first OR element, synchronous parallel control input write / shift to the right of the shift register by the low-order output of the shift register and the output of the ready signal of the converter fragment, the input of the serial binary code of which is connected to the information input of the second trigger and the first input of the EXCLUSIVE OR element, the output of which is connected to the information input of the third trigger, the output of which is connected with the second input of the EXCLUSIVE OR element and the information input of the fourth trigger, the clock input of which is connected to the output of the synchronization signal of the pre a processor and the output of the fifth AND-NOT element, the first input of which is connected to the counting input of the totalizing counter and the output of the fourth AND-NOT element, the inverse input of which is connected to the output of the second AND-NOT element and the clock inputs of the second and third triggers and shift register, parallel information the input of which is connected to the input of the constant code of the converter, the highest bit of which is one, and the remaining bits are zeros, the output of the fourth trigger is connected to the output of the information signal error of the converter, the signal output a bit synchronization failure of which is connected to the output of the fifth trigger, the inverse input of which is connected to the output of the third AND element, the first input of which is connected to the output of the third AND element, the second input of the third AND element is connected to the output of the first OR element, the first output of the pause detector is connected with the second inputs of the fifth AND-NOT element and the first OR element and the asynchronous inverse input of the installation of the first trigger, the asynchronous inverse reset input of which is connected to the output of the OR-NOT element and the second input to of the second AND element, the output of which is connected to the asynchronous inverse inputs of the fourth trigger and reset the totalizing counter and the fifth trigger, the second output of the pause detector is connected to the asynchronous inverse inputs of the reset register shift and the second and third triggers, the first input of the OR-NOT connected to the input resetting the result of the operation of the converter, the initial reset input of which is connected to the second input of the OR-NOT element and the installation input is in the pause state of the pause detector that contains the input clock, pause detection, pause, first and second outputs, element NOT, sixth AND element, subtracting counter, second, third and fourth OR elements, and code input that is connected to information inputs of the subtracting counter, the high-level outputs of which are connected to the inputs of the second OR element, the output of which is connected to the first inputs of the third and fourth OR elements, the detector's clock input is connected to the first input of the sixth AND-NOT element, the output of which is connected to the counting input the subtracting counter and the second input of the third OR element, the output of which is the first output of the detector, the second output of which is connected to the second input of the sixth AND-NOT element and the output of the fourth OR element, the second input of which is connected to the low-order output of the subtracting counter, whose asynchronous inverse recording input is through the element it is NOT connected to the installation input in the pause detection mode of the detector, the installation input in the pause state of which is connected to the asynchronous reset input of the subtracting counter.

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