RU2188502C1 - Serial-binary-to-parallel code converter - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device intended to provide for programming conversion length, shaping check signals, enhancing availability time length, and shaping ready signal due to detection of interval by absence of bit synchronization shift pulses with aid of programmed threshold has shift register, bit counter, buffer register, comparator, interval detector, monitoring unit, and shaper of data record pulses entered in buffer register. EFFECT: enlarged functional capabilities. 4 dwg

Description

 The invention relates to the field of computer technology and is intended to perform the operation of converting a serial binary code (word, message) with programmable length to parallel binary code with the formation of information error signals (or failure) with an even number of units in the converted code, bit synchronization failure when deviating from set conversion length and readiness (end of conversion) by detecting a pause with a programmable threshold and can be used to build devices properties for entering information of the type [1] and LAN controllers (CLS), for example, CLS based on GOST 18977-79 and RTM 1495-75 according to the protocols that are the rules for the exchange of information [1, p. 57-64] between stations of the local network ( SLS) via multiplex and / or separate communication lines by messages (sequential binary codes of length 16 or 24 or 32 bits with the least significant bits ahead and the highest bit of parity of the number of units in the lower bits), separated by pauses of duration (4-40) periods of T frequency pulse synchronization tion message transmission.

 As part of a modern SLS, it is possible to distinguish (see, for example, in [2] on page 221, Fig. 5.9) CLS (contains a device for inputting information of the type [1]), a device for outputting information, and an exchange control device (CID) and synchronization (communication unit with the subsystem) for mutual synchronization and control of the CLS as a whole), an electronic computer (computer) containing a processor (single-chip computer) and combined memory (in the general case, contains RAM - random access memory, DOS - dual-port RAM, ROM - read-only memory and RPZU- eprogrammiruemoe ROM), and a system line (Q-BUS or ISA or VME, or other) for the exchange of information between the components of the computer running the SLS via ATO. In general, the constituent parts of a device for inputting information are a receiver (single-channel or multi-channel), a decoder for generating a serial binary code and shift pulses of bit synchronization, and a converter of a serial binary code to a parallel code (bit / word block), and a device for outputting information to each channel contains a parallel binary code to serial converter (word / message block), an encoder and a transmitter.

 For the rational distribution of functions in the HFS between the hardware and software, the serial binary to parallel code converter (as part of the HLC included in the HLS) must be flexibly controlled from the computer using the CID and be as invariant as possible to the type of system backbone and to the protocols LAN, i.e. when improving CLS, the varied parts should be mainly UUOs, receivers, transmitters, encoders and decoders.

 It should be noted that currently the operation of converting a serial binary code to a parallel code itself is technically implemented trivially, in particular on a simple register type 1533IR8 with serial input and parallel byte output, or a universal byte register type 1533IR24 for bidirectional exchange of information both sequential and and parallel codes - see, for example, [3, p. 103].

 However, in the CLS of each operation of receiving a message, a pause detection procedure must be preceded to prepare the device for entering information for the next conversion operation, and the process of each operation should be monitored (for example, generate informational error signals (or failures) with an even number of units in the code being converted and bit synchronization failure when deviating from the set length of the converted code).

 In this regard, the creation of a simple serial binary to parallel converter with wide functionality that provides flexible controllability from a computer with maximum independence from both the type of system backbone and the methods of exchanging information between computers and components of the CLS and LAN protocols, represents our opinion, an urgent technical problem, the resolution of which will improve the quality of the developed CLS (including devices of the type [1]) that support a local network and with minimal hardware costs, high reliability of operation during the exchange of sequential binary codes with a fixed or programmable length.

 Reliability of operation is a property of a digital device that characterizes the ability of controls to recognize the output of a device as correct or erroneous with the help of hardware-software controls [4, p.6], which ensure its suitability. Controllability - a property of a device that determines the adaptability of control of its technical condition during manufacturing and operation [4, p. 153]. It is controllability that makes it possible to obtain in practice the necessary reliability of the functioning of transmission systems, information processing, and control [5, p. 12], which in modern equipment are also subscribers (stations) of local networks.

 The main disadvantage of the known converters [6-9] for their use in modern CLS is the limited or narrow specialization of their functionality.

 Indeed, an n-bit converter [6] is functionally equivalent to a register type 1533IR8, an (n + 2)-bit converter [8] is functionally also equivalent to a register 1533IR8 except that it has two high order bits to control bit synchronization when receiving n- bit code, and the converters [7] and [9] are narrowly specialized, since the converter [7] is designed to convert serial combined code into parallel code, and the converter [9] is used to convert serial binary Go code into binary decimal code.

 Of the known technical solutions, the closest to the proposed one is a serial binary code to parallel converter, which is part of the device [1] and contains n-bit shift register and parallel code buffer register, bit counter, trigger, AND-NOT element, serial binary input code connected to the information input of the shift register, the input of the shear pulses of the bit synchronization connected to the clock input of the shift register and the counting input of the bit counter, the overflow output of which it is single with the trigger setup input and the buffer register write input, the parallel code output is the output of the buffer register, the code input of which is connected to the shift register code output, the readiness reset input connected to the buffer register and trigger reset inputs, the clock input connected to the first the input of the AND gate, and the output of the ready signal connected to the trigger output and the second input of the AND gate, the output of which is connected to the reset inputs of the shift register and the bit counter.

 The device Converter [1] operates as follows.

 Before starting the next conversion operation, it is in the initial state (in the pause mode) - the shift register, buffer register, bit counter and trigger are reset to zero states.

Upon receipt, the serial information is transmitted to the shift register by the shear pulses of the bit synchronization, which are calculated by the bit counter. If the shift register is full, the bit counter generates an overflow signal, which is a pulse of the start of a pause, according to which the contents of the shift register are sent to the buffer register and a trigger is set that sets the ready signal for transmitting the result of the operation (contents of the buffer register) to the computer during the ready time T1g < Tn, where Tn is the pause duration, which is in the range from 4T to 40T of periods T of the repetition frequency of the shear pulses of bit synchronization. According to the ready signal, clock pulses pass through the AND-NOT element and reset the shift register and the bit counter, and the computer, after reading the result of the operation, sets the converter to its initial state by resetting the buffer register and the trigger with a pulse from the ready reset input. Therefore, the computer during the standby time duration
40T>T1g> 3T (1)
must complete all exchange operations with the device, which will be ready for the next operation only at the end of the readiness reset pulse from the computer.

 The main disadvantage of the converter [1] is its limited functionality (it is not possible to program the length of the converted code, control the operation of the converter, the relatively short availability time T1g (1)) and lose its controllability for an indefinite time when bit synchronization fails, especially in the direction of decreasing from the desired conversion length, because the ready signal (pause) is generated by overflow of the bit counter, and not by the real absence of shear pulses synchronization. It is easy to see that when the trigger is installed, the serial information coming to the converter is completely lost, because the I-NOT element constantly resets the shift register and the bit counter by the ready signal and clock pulses.

 The present invention solves the problem of comprehensively expanding the converter's functionality by providing the possibility of programming the conversion length, generating control signals (information error (or failure) with an even number of units in the converted code and bit synchronization failure when deviating from the set conversion length), increasing the availability time, generating a ready signal by detecting a pause due to the absence of shear pulses of bit synchronization using programmable threshold, as well as by ensuring the independence of the code output as a parallel code of the type of system host computer or LAN protocols.

 To achieve this technical result, a serial binary to parallel code converter comprising a shift register, a bit counter, a buffer register, a parallel code output, which is a buffer register code output, the code input of which is connected to the shift register code output, ready signal output and inputs serial binary code, bit synchronization shift pulses, clock pulses and standby reset, additionally introduced a comparator, a pause detector, a contact block Ole, pulse shaper to write information to the buffer register, initial reset input, enable inputs of the buffer register byte outputs connected to control inputs of the buffer register containing K byte registers whose output enable inputs are separately connected to the control inputs of the buffer register, information inputs of byte registers of which connected accordingly with its code input (for example, with K = 4 and byte code input, the byte input lines are connected to information inputs in a byte register (and with a two-byte code input, the lines of the low byte of the code input are connected to the information inputs of the first (low) and third byte registers, and the lines of the high byte of the code input are connected to the information inputs of the second and fourth (high) byte registers), information signal outputs errors with an even number of units in the converted code and failures when the bit synchronization deviates from the set conversion length, connected to the first and second outputs of the control unit, respectively o, m-bit (where m is determined by the capacity n = 8K of the output register so that 2 to the power (m-1) is equal to n), a programmable code input of the conversion length connected to one of the information inputs of the comparator, the other information input of which is connected to m-bit code output of the bit counter and code input of the pulse shaper, the outputs of which are connected to the inputs of recording information in byte registers of the buffer register in accordance with the connection of the information inputs of byte registers to the code output of the shift register a, programmable code input of the pause detection threshold connected to the code input of the pause detector, the first output of which is the output of the readiness signal of the converter, the input of the serial binary code of which is connected to the information input of the shift register and the first information input of the control unit, the second information input of which is connected to the output comparator, the input of the shear pulses of the bit synchronization of the Converter is connected to the sync input of the shift register, summing the counting input of the counter and the first pulse inputs of the pulse shaper, the control unit and the pause detector, the second pulse input of which is connected to the input of the clock pulses of the converter, the initial reset input and the readiness reset input of which are connected respectively to the first and second reset inputs of the pause detector, the second output of which is connected to the second pulse inputs of the pulse shaper and the control unit, the first installation input of which is connected to the third output of the pause detector, which contains two pulse inputs , two reset inputs, four outputs, the first trigger subtracting the counter, three OR elements, two OR-NOT elements and a code input that is connected to the information input of the subtracting counter, whose inverse asynchronous input is connected to the first pulse input of the detector, the second pulse input which is connected to the first input of the first OR element, the first reset input of the detector is connected to the first input of the first OR-NOT element and the asynchronous reset input of the subtracting counter, the information outputs of the upper digits of which connected to the inputs of the second OR element, the output of which is connected to the first inputs of the second OR-NOT element and the third OR element, the second input of which is connected to the output of the first OR element and the counting input of the subtracting counter, the low-order information output of which is connected to the second input of the second OR element -NOT, the first output of the detector is connected to the output of the first trigger, the inverse input of which is connected to the output of the third OR element and the second output of the detector, the second reset input of which is connected to the first input of the first OR-NOT element, the output of which is connected to the inverse reset input of the first trigger and the third output of the detector, the fourth output of which is connected to the second input of the first OR element, the output of the second OR-NOT element, the reset bit counter input and the second control unit installation input , which contains two information inputs, two pulse inputs, two installation inputs, two outputs, an EXCLUSIVE OR element, a NOT element, second, third and fourth triggers with inverse reset and installation inputs, and a LOGIC 1 bus, with unified with the reset inputs of the second and third triggers and the installation input of the fourth trigger, the first information input of the control unit connected to the first input of the EXCLUSIVE OR element, the output of which is connected to the information input of the second trigger, the output of which is connected to the second input of the EXCLUSIVE OR information information of the third trigger, the output of which is the first output of the control unit, the second information output of which is connected to the inverse output of the fourth trigger, the information input of which of the second is connected to the second information input of the control unit, the first pulse input of which is connected to the sync input of the second trigger, the second pulse input of the control unit is connected to the sync inputs of the third and fourth triggers, the input of the third trigger setting and the reset input of the fourth trigger are connected to the first input of the control unit installation, the second the installation input of which is connected through the element NOT to the installation input of the second trigger.

 The authors are not aware of technical solutions containing features equivalent to distinguishing features (introducing a comparator, pause detector, control unit, pulse shaper to write information to the buffer register, enable inputs of the buffer register byte outputs, programmable code inputs of the conversion length and detect pause and information error outputs if even the number of units in the converted code and the failure of bit synchronization when deviating from the set conversion length) of the proposed converter For those which (in comparison with the prototype) comprehensively expand its functional capabilities, which can be used in the construction of CLSs that support, with high reliability, the exchange of serial binary codes with a fixed conversion in a single-channel or programmable length in a multi-channel CLS with the input of serial information from channels with different characteristics in time division mode.

 Figures 1 to 4 show a functional diagram of a serial binary to parallel code converter when it is implemented, in particular, when K = 4 (i.e., n = 32), m = 6, and a byte shift register in the library of integrated circuit elements series type 533 and / or 1533.

 The serial binary to parallel code converter (Fig. 1) contains a shift byte register 1, a 2-bit counter, a buffer register 3 formed by K = 4 byte registers, the outputs of which form an n = 32-bit code output of the converter parallel code, and the information inputs byte registers are interconnected and connected to the code output of register 1, comparator 4, pause detector 5, control unit 6, pulse shaper 7 for writing information to register 3, input 8 of serial binary code, input 9 shift bit synchronization pulses, input 10 clock pulses, input 11 initial reset, input 12 readiness reset, first 13, second 14, third 15 and fourth 16 outputs of the detector 5, output 13 of which is the output of the readiness signal of the converter, the first 17 and second 18 outputs of the block 6, which are outputs from the converter, respectively, of information error signals with a parity of the number of units in the converted code and a bit synchronization failure when deviating from the set conversion length, the enable inputs of the byte outputs 3, m = 6-bit programmable code input of the conversion length connected to one of the information inputs of the comparator 4, the other information input of which is connected to the m = 6-bit code output of the counter 2 and the code input of the shaper 7, the outputs of which are separately connected to the inputs of information recording in byte registers of the buffer register 3, and a programmable code input of the pause detection threshold connected to the code input of the update circuit breaker 5, the first pulse input of which is connected to the first pulse inputs of block 6 and the driver 7, a sync input of register 1, the summing counter input of the counter 2 and the input 9 of the shear pulses of the bit synchronization of the converter, the input 8 of the serial binary code of which is connected to the information input of the register 1 and the first the information input of block 6, the second information input of which is connected to the output of the comparator 4, the input 10 of the clock pulses of the Converter is connected to the second pulse input of the detector 5, the first the second and second reset inputs of which are connected to the input 11 of the initial reset and input 12 of the readiness reset of the converter, respectively, the second output 14 of the detector 5 is connected to the second pulse inputs of the unit 6 and the driver 7, the third output 15 of the detector 5 is connected to the first installation input of the unit 6, the second the installation input of which is connected to the reset input of the counter 2 and the fourth output 16 of the detector 5.

 The detector 5 (figure 2) contains two pulse inputs 9 and 10, two inputs 11 and 12 of the reset, four outputs 13-16, the first trigger 19, subtracting the counter 20, three elements OR 21-23, the first 24 and second 25 elements OR -NOT and a code input that is connected to the information input of the subtracting counter 20, whose inverse asynchronous input is connected to the first pulse input 9 of the detector 5, the second pulse input 10 of which is connected to the first input of the first element 21 OR, the first input 11 of the reset of the detector 5 is connected with the first input of the first element 24 OR NOT and AC a reset reset input of the subtracting counter 20, the high-order information outputs of which are connected to the inputs of the second OR element 22, the output of which is connected to the first inputs of the second OR element 25 and the third OR element 23, the second input of which is connected to the output of the first OR element 21 and the subtracting counting input a counter 20, the low-order information output of which is connected to the second input of the second element 25 OR NOT, the first output 13 of the detector 5 is connected to the output of the first trigger 19, the inverse input of which is connected nen with the output of the third element 23 OR and the second output 14 of the detector 5, the second input 12 of the reset which is connected to the second input of the first element 24 OR NOT, the output of which is connected to the inverse input of the reset of the first trigger 19 and the third output 15 of the detector 5, the fourth output 16 which is connected to the second input of the first element 21 OR and the output of the second element 25 OR NOT.

 The control unit 6 (Fig. 3) contains the first 8 and second information inputs, the first 9 and second 14 pulse inputs, the first 15 and second 16 installation inputs, the first 17 and second 18 outputs, element 26 EXCLUSIVE OR, element 27 NOT, second 28 , the third 29 and fourth 30 triggers with inverse reset and installation inputs and a LOGIC 1 bus connected to the reset inputs of the second 28 and third 29 triggers and the installation input of the fourth trigger 30, and the first information input 8 of block 6 is connected to the first input of element 26 EXCLUSIVE OR whose output is connected to the information the input of the second trigger 28, the output of which is connected to the second input of the EXCLUSIVE OR element 26 and the information input of the third trigger 29, the output of which is the first output 17 of block 6, the second information output 18 of which is connected to the inverse output of the fourth trigger 30, the information input of which is connected to the second information input of block 6, the first pulse input 9 of which is connected to the clock input of the second trigger 28, the second pulse input 14 of block 6 is connected to the clock inputs of the third 29 and fourth 30 triggers, input the frames of the third trigger 29 and the reset input of the fourth trigger 30 are connected to the first input 15 of the installation of block 6, the second input 16 of the installation of which is connected via the element 27 NOT with the installation input of the second trigger 28.

 A possible implementation of the shaper 7 pulses of information recording in register 3 (figure 4) contains m = 6-bit code input, the first 9 and second 14 pulse inputs, a group of four pulse outputs, four elements 2I-2I-OR 31-34 ( each of these elements can be implemented, for example, on three elements 2AND), element 35 AND NOT, three elements NOT 36-38, two elements 39 and 40, and four elements 41-44.

 When implementing the Converter (Fig.1-4) in the library of integrated circuit elements (ICs) of the 533 and / or 1533 series, it is possible to perform: register 1 - on one IR8 IC (byte register with sequential input along the edges of the shear pulses of the bit synchronization and parallel code output and inverse asynchronous reset connected to the bus of the logical unit of the converter, the input of the serial binary code of which is connected to two information inputs of the IR8 chip register 1, operating on And); counter 2 (or 20) - on two (or one) IS IE7 (IS IE7 - reversible 4-bit counter with asynchronous direct reset input and asynchronous inverse load input from parallel information inputs and summing (+1) and subtracting (-1) counting inputs, which ensure functioning along the edges of the counting pulses acting on them), whereby the summing counting input of the IE7 chip of counter 20 and the subtracting counting inputs and asynchronous inverse load inputs of both IE7 counter 2 chips are connected to the logical unit bus of the converter; register 3 - on four IR23 IRs (IR23 is a byte register with synchronous recording of information on the edge of the recording pulse and with the resolution of the byte output inverted control signal); comparator 4 - on two IP SP1; flip-flops 19, 28-30 - on two TM2 ICs, each of which contains two D-flip-flops with direct and inverse outputs and separate information inputs, edge sync inputs, asynchronous inverse reset and installation inputs, and the first D-trigger 19 has an information input and the sync input is connected to the logical unit bus of the converter; the remaining components of the converter are on the combination elements of the corresponding ICs.

 Further, the operation of the converter is described using the system of positions and designations defined in the following paragraphs.

 1. A modified description language of Boolean (logical) functions ABEL is used, in which the CONJUNCTION, DISJUNCTION, INVERSION and EXCLUSIVE OR operators are designated "&", "#", "!", "$" Respectively. For example, Z26 = X8 $ Z28 means an EXCLUSIVE OR operation performed by element 26 (Fig. 3) on variables X8 and Z28. In addition, the initial (X), resulting (Y) and intermediate (Z) inverse variables are denoted by the letter N, equivalent to the operator "!" inversions, for example, NCX9 =! CX9 (or NCX10 =! CX10) are bit-synchronization shear pulses (or clock pulses) received at the input 9 (or 10) of the converter in inverse form, i.e. at the input j = 9 (or 10) with NCXj = 1, there is no pulse, but with NCXj = 0 it acts; NCZ21 = NCX10 # Y16 means that at the output of the OR element 21 (FIG. 2), an inverse pulse NCZ21 is generated by the MCX10 at Y16 = 0.

 2. The codes at the outputs of register 1, counter 2, register 3, counter 20 and programmable code inputs of the comparator 4 and detector 5 are denoted (see Fig. 1, 2), respectively, through GD (7: 0) = GD7 GD6 ... GD0 , С (5: 0) = С5 С4 ... С0, D (31: 0) = D31 D30 ... D0, СР (3: 0) = СРЗ СР2 СР1 СР0, F (5: 0) = F5 F4 ... F0 and P (3: 0) = Р3 Р2 Р1 Р0), where (GD0, C0, D0, СР0, F0, Р0) are lower, and (GD7, С5, D31, СР3, F5, Р3) are senior bit digits (0 or 1) of these codes.

 3. As inverse variable signals NE0, NE1, NE2, NE3 on the control inputs of register 3 are designated as components of the vector (code) NE (3: 0) = NE3 NE2 NE1 NE0, which by zero enable the byte outputs of register 3.

 4. Depending on the bit capacity (for example, p = 32 or p = 16 or p = 8) of the data bus of the system line (SM) station of the local network (SLS) byte outputs D (31:24), D (23:16), D (15: 8), D (7: 0) of register 3 at p = 32 are independent and are allowed simultaneously at NE3 = NE2 = NE1 = NE0 = 0; at p = 16 are combined in pairs bytes (T. e. D (31: 24) = D (15: 8), D (23:16) = D (7: 0) and the outputs of the highest word D are allowed (32:16 ) for NE3 # NE2 #! (NE1 & NE0) = 0, or the low word D (15: 0) for! (NE3 & NE2) # NE1 # NE0 = 0; and for p = 8 the byte outputs are combined bitwise, i.e. D ( 31:24) = D (23:16) = D (15: 8) = D (7: 0) and only the outputs of one of the bytes of code D (31: 0) can be allowed, due to activation (during byte reading code D (31: 0)) of only one of the signals of the NE vector (3: 0) .In this regard, the proposed converter turns out to be practically independent of the type of SM SLS.

 5. Shaper 7 generates a vector signal CW (3: 0) = CW3 CW2 CW1 CW0 of the write pulses of the GD (7: 0) code along the edges sequentially, starting from the write pulse CWO in the low byte register D (7: 0).

 6. At input 8, the signal of the serial binary code is denoted by X8, at inputs 9 and 10, inverse pulse signals are denoted by NCX9, NCX10, and at inputs 11 and 12, the pulses of the initial reset and the ready reset are indicated by CX11 and CX12, respectively. The signals generated at outputs 13.14, 15 and 16 by the detector 5 through Y13, NCY14, NCY15 and Y16, respectively, and at outputs 17 and 18 of block 6 through Y17 and Y18, respectively. In addition, the direct and inverse static (or pulsed) signals generated inside the converter components are denoted by Zj and NZj (or CZj and NCZj), respectively, where j is the number of the element generating the corresponding signal, for example, elements 38 and 44 of driver 7 (Fig. .4) generate pulse signals CZ38 and CZ44, respectively.

7. Comparator 4 continuously compares the codes F (5: 0) and C (5: 0) and generates the resulting variable Y4 according to the expressions
Y4 = 0 for F (5: 0) not equal to C (5: 0), (2)
Y4 = 1 with F (5: 0) equal to C (5: 0). (3)
8. The front or the fall of any signal (direct or inverse) means the change in the logical value of this signal from "0" to "1" or from "1" to "0", respectively.

 9. By setting (or resetting), for example, trigger 19 of detector 5 (FIG. 2), it means switching this trigger to “1” (or “0”).

10. In the process of functioning, the detector 5 generates a ready signal Y13 (computer interruption through the UCL CLC) and a pause signal Y16 so that the following four converter operation modes can be distinguished
PP0 standby (idle) with Y13Y16 = 01, (4)
PP1 conversion at Y13Y16 = 00, (5)
PP2 availability with Y13Y16 = 11, (6)
PP3 conversion and availability at Y13 Y16 = 10. (7)
Given the adopted system of provisions and notation, we first describe the operation of the converter as a whole as a finite state machine with memory, and then the operation of its components.

The initial state of the converter is PP0 mode (4). In this mode, with a pause signal Y16 = 1, counter 2 is fixed at “000000”, trigger 28 is set with NZ27 =! Y16 = 0, register 3 contains the result due to the inverter’s operation history, trigger 19 is reset, trigger 29 is set (sets a fault signal Y17 = 1 of the input code), and the trigger 30 is reset (sets the signal Y18 = 1 bit synchronization failure), moreover, the reset of the trigger 19 and the transfer of triggers 29 and 30 to the fault state was carried out earlier by an inverse pulse
NCY15 =! (XC11 # XC12), (8)
formed at the output 15 of the detector 5 either by the pulse XC11 (when the equipment is turned on), or by the pulse XC12, which the computer generates by the ready signal Y13. Each conversion operation starts at Y16 = 1 with the arrival of a serial binary code and inverse shift pulses of NCX9 bit synchronization to the X8 signal converter, the number of which “F” for the correct operation to be performed must be at least two and no more than 32 and precisely determined by the programmable code F ( 5: 0) the length of the transformation according to the formula
F = F0 + 2F1 + 4F2 + 8F3 + 16F4 + 32F5. (9)
At the beginning of the first of the sequence of pulses F of the NCX9, the detector 5 switches the signal Y16 from “1” to “0” and the conversion operation begins so that by the sequence F (9) of the pulses NCX9 in byte 1, bytes (starting from the lowest) of the input the converted code X8, and the driver 7, for example, for F> 24, sequentially generates pulses CW0 (on the 9th NCX9), CW1 (on the 17th NCW9) and CW2 (on the 25th NCX9) write information to the first (youngest) ), the second and third byte registers of buffer register 3 on the edges (i.e., on cn I give the corresponding NCX9). Each conversion operation ends with the formation by the detector 5 of the pulse NCY14 of the beginning of the pause, according to which the driver 7, depending on the number F (9), generates one of the pulses of the vector CW (3: 0) so that: CW0 with F <9; CW1 at F> 9 and less than or equal to 16; CW2 at F> 16 and less than or equal to 24; CW3 at F> 24. In addition, the trigger 19 is directly set by the pulse NCY14 = 0 and sets the ready signal Y13 = 1, and by the edge of the NCY14 pulse, the triggers 29 and 30 are set to the formation states of the output signals Y17 and Y18 according to the expressions
Y17 = Z28 (at the moment of front NCY14), (10)
Y18 =! Y4 (at the moment of front NCY14), (11)
counter 20 goes into the state "000000", detector 5 sets the signal Y16 = 1 pause and the converter goes into PP2 mode (6).

 Further, the operation of the converter as a whole in time consists in sequentially alternating its operating modes, for example, PP0, PP1, PP2, PP3, PP1, PP2, PP3, PP1, etc., so that the transition to PP0 can be carried out from any mode by pulse CX11 of initial reset, or from PP2 mode by pulse CX12; transition to PP1 - or from PP0 at the first pulse of NCX9 (each pulse of NCX9 transfers the counter 20 from any state to the state "P3P2P1P0" defined by the code P (3: 0)), or from PP3 by pulse NCY15 =! CX12 as the inverse of the input pulse CX12; transition from PP2 to PP3 by the pulse of NCX9.

 At the beginning of the PP3 (7) mode, register 1, counter 2, and driver 7 are busy with the current conversion operation, and register 3 contains the result of the previous operation. To eliminate the loss of the result of the previous operation, it is necessary to read the computer before writing from register 1 to register 3 of each byte generated during the current conversion operation, and then transfer the converter to PP2 mode by pulse CX12 = 1.

 The functioning of the individual components of the Converter is as follows.

 Register 1 on the front of each shift pulse NCX9 bit synchronization receives the next bit X8 of the input sequential binary code with a shift to the right. Every eight pulses of the NCX9 (after the start of the operation), the corresponding byte GD (7: 0) of the result of the operation is generated (starting from the low byte).

 Counter 2 by a pause signal Y16 = 1 is fixed in state C (5: 0) = 000000, and with Y16 = 0 along the edge of each NCX9 pulse, the contents of counter 2 are increased by "1".

 In buffer register 3, each byte register j = 0,1,2,3 according to the signals CWj and NEj functions so that from register 1 the code GD (7: 0) is entered into register j along the edge of the pulse CWj and removed from the byte output of this register only with NEj = 0, since with NEj = l the byte output of register j is in a high-impedance state (disabled).

 Comparator 4 generates signal Y4 as a combinational device according to expressions (2) and (3).

The detector 5 (figure 2) generates an inverse pulse NCY14 start pause according to the formula
NCY14 = NCX10 # Y16 # SRZ # CP2 # CP1, (12)
NCY15 inverse pulse according to (8), pause signal Y16 according to the formula
Y16 =! (СРЗ # СР2 # СР1 # СРО) (13)
and a ready trigger signal Y13 set and reset by pulses NCY14 (12) and NCY15 (8), respectively. From figure 2 and expressions (12), (13) it follows that the NCY14 pulse is generated by the NCX10 pulse when the counter 20 is in the state CP (3: 0) = 0001, and the signal Y16 = 1 is set when the counter 20 is in the state " 0000 ". In this state, the counter 20 can be fixed by the pulse CX11 = 1 of the initial reset. With CX11 = 0, the counter 20 is according to the P code (3: 0) and NCX9 inverse pulses and inverse pulses
NCZ21 = NCX10 # Y16, (14)
generated element 21, operates as follows.

With each pulse NCX9 = 0, the counter 20 is fixed in the state CP (3: 0) = P (3: 0), which defines the detection threshold P as a number according to the expression
P = P0 + 2P1 + 4P2 + 8P3. (fifteen)
When there is a pause in the transmission, the feed to the NCX9 pulse converter stops and at Y16 = 0, element 21 generates exactly P (15) pulses NCZ21 = NCX10 (counted from the last NCX9 pulse), along the edge of each of which the content of counter 20 decreases by "1", and the pulse P of this sequence generates a pulse NCY14 = NCX10 (12) of the beginning of a pause, after which the counter 20 goes into the state "0000" and the detector 5 sets the signal Y16 = 1 pause, inhibiting the formation of signal NCZ21 (14). In the "0000" state, the counter 20 remains until the next sequence F (9) of shear pulses NCX9 of the bit synchronization arrives at the converter. In this regard, the detection threshold P (15) and the frequency fl0 = kf9 of the NCX10 clock pulses (where k is the proportionality coefficient greater than "1"; f9 is the pulse repetition rate of the NCX9 bit synchronization) must be selected from the condition
2 / f9> P / fl0> l / f9 = T (16)
a variation of two numbers k> 1 and P> 2 at a temporary threshold for detecting pause. Then = P / fl0 = P / (k f9) = T (P / k).

 Block 6 on the input information signals X8 and Y4, the pulse signals NXC9, NCY14 and NCY15 and the pause signal Y16 operates as follows. Before the start of each conversion operation, trigger 28 is set by the signal NZ27 =! Y16 = 0, trigger 29 is set, and trigger 30 is reset, and the translation of triggers 29 and 30 to the indicated states was carried out earlier by the inverse pulse NCY15 (8). During the conversion time along the edge of each NCX9 pulse, trigger 28 at X8 = 1 switches to the opposite state Z26 = X8 $ Z28 (at the time of the NCX9 front). Therefore, after passing through the sequence F (9) of pulses NCX9, the trigger 28 will be in the correct state Z28 = 0 (or in the state Z28 = 1 error detection) with an odd (or even) number "1" in the converted code X8. Then block 6 receives an NCY14 pulse of the beginning of a pause, at the end of which triggers 29 and 30 generate signals Y17 and Y18 according to (10) and (11) so that when Y17 = Y18 = 0, no failures were detected, and when Y17 = 1 (or Y 18 = 1) in the process of performing the conversion operation, an information error was detected in the converted code X8 (or a bit synchronization failure, i.e., a bit synchronization deviation from the set length F (9)).

Shaper 7 (figure 4) is implemented taking into account two-way restrictions
33>F> 1 (17)
length (9) and the signals of the code C (5: 0) and inverse pulses NCX9 and NCY14 generates combination signals of the vector CW (3: 0) according to the expressions
CW0 = [CZ44 & (C3 &! C4)] # [CZ38 & (! C3 &! C4 &)], (18)
CW1 = [CZ44 & (! СЗ & С4)] # [CZ38 & (С3 &! С4)], (19)
CW2 = [CZ44 & (СЗ & С4)] # [CZ38 & (! С3 & С4)], (20)
CW3 = [CZ44 & C5] # [CZ38 & (C3 & C4)] (21)
using intermediate variables (pulses)
CZ44 = [! (C0 # C1 # C3)] & (CX9 # CY14), (22)
CZ38 = [(C0 # C1 # C3)] & CY14. (23)
From Fig. 4 and formulas (18) - (23) it can be seen that, for example, for a length F> 24 (the length F is determined by formula (9) and constraint (17)), pulses CW0, CW1 and CW2 are generated at (С0 # С1 # C2) = 0 by pulse sequence CZ44 = CX9 sequentially (CW0 by the ninth NCX9 with (C3 &! C4) = 1; CW1 by the 17th NCX9 with (! C3 & C4) = 1; CW1 by the 25th NCX9 with (C3 & C4) = 1), and according to the pulse NCY14, depending on the value of the length F, only one of the pulses of the vector CW (3: 0) is always generated, namely: CW0 for F <9; CW1 at 17>F>8; CW2 at 25>F>16; CW3 at F> 24.

Condition (16) and the sequential generation of pulses of the vector CW (3: 0) according to (18) - (23) determine that, when a ready signal Y13 of duration T2g appears, it is necessary (to exclude the loss of the result of the operation) that bytes D (7: 0) , D (15: 8), D (23:16), D (31:24) were read by a computer during the times T0, Tl, T2, T3, defined respectively by the expressions
T0 = Tn + 6T, (24)
T1 = Tp + 14T, (25)
T2 = Tn + 22T, (26)
T3 = Tp + 30T, (27)
where Tn = T (4-40) - the duration of the pause;
T = l / f9 - period of the repetition frequency of the shear pulses of the NCX9 bit synchronization.

Therefore, in the worst case (at Tn = 4T), the duration T2g of the converter ready signal can be estimated by
T2g = T0 = 10T. (28)
Comparing (1) and (28) at Tn = 4T, we obtain
T2g / Tg = 2.5, (29)
that the duration of the availability of the proposed Converter is several times higher than the duration of the availability of the prototype [1], the capacity of the shift register which is K times (ie four times with n = 32) more than the capacity of the register 1 shift.

 Thus, the proposed converter, due to its essential features, has broader functionality than the prototype [1] due to the programming of the conversion length F according to (9) and (17), the formation of two bits of functioning control according to (10) and (11) ), increase the availability time by several times (compared with the prototype - see rating (29)) and detect a pause using the programmable threshold P according to (15) and (16). In this regard, this converter can be used in the construction of CLSs that support high-reliability exchange of serial binary codes fixed in a single-channel or programmable conversion format in a multi-channel CLS with the input of serial information from channels with different characteristics in time-division mode, for example, with using a device for inputting information of the type [1], with the implementation of this converter.

Literature
1. Prototype, a.s. 1786491, M. G 06 F 13/00, USSR. Device for entering information / D.Yu. Gusev and Yu.V. Hooks. Publ. 01/07. 1993. Bull. 1.

 2. Horsetail S.T. et al. Organization of sequential multiplex channels of automatic control systems / S.T. Horsetail, V.V. Doroshenko, V.V. Mount. Under the total. ed. S.T. Horsetail. - L .: Mechanical engineering. Leningrad Separation, 1989 .-- 271 p., Ill.

 3. Yu.V. Novikov, D.G. Karpenko. The equipment of local networks: functions, selection, development / Edited by Yu.V. Novikov. M .: Publishing house ECOM, 1998. - 288 p.: Ill.

 4. Scherbakov N. S. Reliability of digital devices. - M.: Engineering, 1989 .-- 224 p.: Ill.

 5. Shibanov G.P. et al. Control of the functioning of large systems / G.P. Shibanov, E.A. Artemenko, A.A. Mateshkin, N.I. Tsiklinsky. Ed. Honored Inventor of the RSFSR Doctor of Technical Sciences G.P. Shibanova. - M.: Mechanical Engineering, 1977, 360 p.

 6. A. p. 822175, M. Cl. 3 G 06 F 5/04, USSR. The serial to parallel converter / Yu.A. Pluzhnikov, E.A. Evseev, V.I. Kosogorov and A.N. Hunchbacks. Publ. 04/15/1981. Bull. 14.

 7. A.S. 1078424, M. G 04 F 5/04, USSR. Convertible sequential combined code to parallel binary code / V.D. Gladkov. Publ. 03/07/1984. Bull. 9.

 8. A. p. 1081639, M. G 06 F 5/04, USSR. Device for converting serial code to parallel / V.I. Soloviev and A.E. Kravets. Publ. 03/23/1984. Bull. eleven.

 9. A.S. 1084780, M. G 06 F 5/02, USSR. Convert serial binary code to parallel binary decimal code / E.A. Shurmukhin and K.V. Queen. Publ. 04/07/1984. Bull. thirteen.

Claims (1)

 A serial binary to parallel converter containing a shift register, a bit counter, a buffer register, a parallel code output, which is a buffer register code output, the code input of which is connected to the shift register code output, the ready signal output and serial binary code inputs, shift pulses bit synchronization, clock pulses and reset readiness, characterized in that it further comprises a comparator, pause detector, control unit, shaper them The information is written into the buffer register, the input of the initial reset, the resolution enable inputs of the buffer register connected to the control inputs of the buffer register containing K byte registers, the output enable inputs of which are the control inputs of the buffer register, the information inputs of the byte registers of which are connected accordingly to its code input, information error signal outputs for an even number of units in the code to be converted, and failure when the bit synchronization deviates from the set the length of the conversion, connected to the first and second outputs of the control unit, respectively, m-bit (where m is determined by the capacity n = 8K so that 2 to the power m-1 is equal to n) programmable code input of the conversion length connected to one of the information inputs of the comparator , the other information input of which is connected to the m-bit code output of the bit counter and the code input of the pulse shaper, the outputs of which are connected to the inputs of recording information in byte registers of the buffer register in accordance with by the information inputs of byte registers to the code output of the shift register, the programmable code input of the pause detection threshold connected to the code input of the pause detector, the first output of which is the output of the converter ready signal, the input of the serial binary code of which is connected to the information input of the shift register and the first information input of the block control, the second information input of which is connected to the output of the comparator, the input of the shear pulses of the bit synchronization of the Converter connected to the shift register sync input, summing the counting input of the bit counter and the first pulse inputs of the pulse shaper, control unit and pause detector, the second pulse input of which is connected to the input of the converter clock pulses, the initial reset input and the readiness reset input of which are connected respectively to the first and second inputs reset the pause detector, the second output of which is connected to the second pulse inputs of the pulse shaper and the control unit, the first input of which is connected with the third output of the pause detector, which contains two pulse inputs, two reset inputs, four outputs, the first trigger, a subtracting counter, three OR elements, two OR elements - NOT and a code input connected to the information input of the subtracting counter, inverse asynchronous boot input which is connected to the first pulse input of the detector, the second pulse input of which is connected to the first input of the first OR element, the first reset input of the detector is connected to the first input of the first OR element - NOT and asynchronous input the wasp of the subtracting counter, the information outputs of the upper digits of which are connected to the inputs of the second OR element, the output of which is connected to the first inputs of the second OR element and the third OR element, the second input of which is connected to the output of the first OR element and the counting input of the subtracting counter, the information output of the lowest the discharge of which is connected to the second input of the second element OR - NOT, the first output of the detector is connected to the output of the first trigger, the inverse input of which is connected to the output of the third element and OR and the second output of the detector, the second reset input of which is connected to the second input of the first OR element - NOT, the output of which is connected to the inverse reset input of the first trigger and the third output of the detector, the fourth output of which is connected to the second input of the first OR element, the output of the second OR element - NOT, the reset bit counter input and the second installation input of the control unit, which contains two information inputs, two pulse inputs, two installation inputs, two outputs, the element EXCLUSIVE OR, the element NOT, the second, third and h the fourth triggers with inverse reset and installation inputs and a logical 1 bus connected to the reset inputs of the second and third triggers and the installation input of the fourth trigger, the first information input of the control unit connected to the first input of the EXCLUSIVE OR element, the output of which is connected to the information input of the second trigger, the output of which is connected to the second input of the EXCLUSIVE OR element and the information input of the third trigger, the output of which is the first output of the control unit, the second output of which is the inverse output of the fourth trigger, the information input of which is connected to the second information input of the control unit, the first pulse input of which is connected to the clock input of the second trigger, the second pulse input of the control unit is connected to the clock inputs of the third and fourth triggers, the input of the third trigger setting and the reset input of the fourth trigger are connected to the first installation input of the control unit, the second installation input of which is connected through the element NOT to the installation input of the second trigger.

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