RU2644530C2 - Method of electric impulses conversion into manchester code and device for its implementation - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: impulses sequence from the device input are subjected to the sign inversion for each even impulse by storing the input state in the memory at the previous step with the help of the auxiliary trigger, if the signal level was fixed in the previous step, then the current calculation step is considered even. The impulses sequence at the input is subjected to inversion to provide the signal detector trigger actuation at the previous step in the antiphase with respect to the main trigger, to which the obtained intermediate impulses sequence with the sign inversion for each even impulse is received, that is previously subjected to additional correction.

EFFECT: provision of the direct path and the feedback interaction elimination, and the aperiodic effect from the feedback elimination.

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Description

FIELD OF THE INVENTION

The invention relates to electronic information technical solutions for general purposes, in which control and regulation are required to coordinate channels for processing and transmitting information in which the Manchester code is preferred, since the receiver does not need to have information about the information transfer rate in such a code.

State of the art

Known devices [4, 5, 6] designed to convert normalized pulses and Manchester code cells MIL-STD 1553 manufactured by AIT USA, US Patent No. 5,325,359, 5,367,641 and others, as well as devices and methods [6, 7, 8] for control signals and hold them in predetermined states US 5564090A (18 dec, 1997), US 2015/0286607 A1 (Oct 8, 2015) with a priority of 1997 and 2015. In addition, microprocessor devices, for example breadboard-debug board ЕВ- 552 [1] manufactured by KTC-MK.

The well-known MIL-STD 1553 device is mass-produced in different versions: for the PXI bus of the National Instruments PXI signal processing station based on visual programming in the LabView environment, which is very cumbersome, which leads to the need to build a program from several blocks at the very initial stage, and the main the problem is not solved (hardware and software complexity and cost with this approach increase significantly); for PCI bus in AIT1553 version for 32-bit platform; and also performed with the USB interface. Some well-known devices that are convenient for simple execution and software implementation in Assembler language, such as the EV-552 board, are not designed to work with signals and codes in the Manchester format. The EB-552 board does not have an organized USB port, however, it has an I2C bus (US 2015/0286607 A1, etc.) that is convenient for operation with a connector for peripheral expansion. Thus, the method used in the prototype [1], allows you to process only standard (normalized) pulses and does not allow you to convert them to Manchester code.

Manchester code [5], clause 4.3.3 of GOST R 52070-2003 (Serial interface of electronic module systems. General requirements) uses a bipolar phase-manipulated code (Manchester II). The unit is transmitted as a bipolar encoded signal 1/0 (a positive pulse is followed by a negative pulse). Zero is transmitted as a bipolar encoded signal 0/1 (a negative pulse is followed by a positive pulse). The transition through the zero level is carried out in the middle of the time interval during which the information bit is transmitted.

Disclosure of invention

The proposed method consists in the fact that the sequence of pulses from the input of the device is subjected to sign inversion for each even pulse by storing the input state in the previous step using the auxiliary trigger, if the signal level was fixed in the previous step, then the current calculation step is considered as even. The sequence of pulses at the input is inverted to ensure that the trigger of the signal detector at the previous step is in antiphase with respect to the main trigger, which receives the received intermediate sequence of pulses with sign inversion for each even pulse, which is then subjected to additional correction (see Fig. . 1; 17; 18; 19 and FIG. 3; 16, 17, 18).

The device [Fig. 1] to implement the method (p. 9) consists of two triggers with amplitude A, in which the first trigger supports the main output at zero input impact, and the second trigger has an inverter at the input with correction through the product from the output of the first trigger, and with correction for output, to equalize the feedback weight in which the second trigger is installed, and sequentially invert the polarity for each even pulse coming from the input of the device to the input of the first trigger, the output of which is the output of the device, which It is equipped with a microprocessor system in which the binding of microcircuits is carried out using the I2C interface, and the installation of an additional processor on it to support the USB interface. Correction of the output circuits of the second trigger requires the installation of an amplifier, the only one requiring precise adjustment, therefore, the triggers themselves, as well as circuits that implement the directly proposed method, do not need to be separately removed for tuning on the auxiliary unit and executed as a separate board.

Description of the method:

the sequence of pulses from the input of the device is subjected to sign inversion for each even pulse, by storing the state of the input in the previous step using the auxiliary trigger,

if at the previous step the signal level was fixed, then the current calculation step is considered as even,

then the sequence of pulses at the input is inverted to ensure that the auxiliary trigger of the signal detector at the previous step is triggered in antiphase with respect to the main trigger,

the state of the level determined by the obtained pulse sequence with sign inversion for each even pulse, which is subjected to additional correction before that, is fixed at the output of the main trigger,

obtained in the course of fixation in the main trigger, and in general, the pulse sequence obtained as a result of the general conversion is the resulting signal in which the level change occurs when a bit of the initial pulse sequence arrives,

those. when a bit of the input sequence arrives, the signal level changes with the inverse of the output sign, which corresponds to transmitting a signal in the format of a Manchester code that does not require normalization by the data transfer rate, thus, to the external receiver for which the output information packet is prepared, set the transmission speed no data required.

Device description

A device for implementing the method of converting electrical pulses to Manchester code [Fig. one]:

contains a microprocessor system (1), a transistor-transistor logic unit (2) for controlling the address / data bus (3), an additional optional processor (4) with a USB port (5); RS232 connector (6); a second optional processor connected via the I2C bus (7) and a liquid crystal display (8); connector for the input of the pulse signal (9); three blocks of the work (10; 14; 18); two triggers with triggering at an arbitrary input amplitude (11; 15); output connector in Manchester format (12); two adders (13; 17); an amplifier with fine tuning of the back-up voltage (17); a sign determination unit (signal level limiter) sgn (19) and a reference voltage generator (20), a switching circuit for obtaining a pulse sequence in the Manchester code (21);

microprocessor system (1) has a duplex RS232 serial port (1.1), a dedicated standard processor port (1.2) or a PWM input (1.2) for a pulse-width modulated (PWM) signal, as well as an I2C duplex serial port (1.3);

RS232 connector (6) with microprocessor system (1) connects duplex communication through port (1.1) of block (1) and port (6.1) of block (6); the I2C bus connector (6) with the microprocessor system (1) couples duplex communication through port (1.3) of block (1) and port (7.1) of block (7); the signal from the output in the Manchester format - port (12.1) of the connector (12) is transmitted via communication to a dedicated standard port or PWM input, i.e. on the duplex port (2.1); the address / data bus operates under the control of the duplex port (3.3) of the transistor-transistor logic unit (2);

the address / data bus of the first duplex port (3.1) is connected to the response port (1.4) of the microprocessor system, and the second duplex port of the address / data bus (3.2) is connected to the response duplex (8.1) of the liquid crystal display (8);

the port (9.1) of the pulse input connector (9) is connected to the input (10.1) of the product block (10); in addition, port (9.1) is connected to the first inverse input (13.1) of the adder (13);

the output of the adder (13.2) is connected to the input (14.2) of the product block (14); the output (10.3) of the block of the product (10) is connected to the input (11.1) of the trigger (11);

the trigger output (11.2) (11) is connected to the port (12.1) of the signal output connector in Manchester format;

the non-inverted input (13.3) of the adder (13) is connected to the output (20.1) of the reference voltage source (20);

the output (11.2) of the trigger (11) is connected to the input (14.1) of the block of the product (14);

the output (14.3) of the block of the product (14) is connected to the input (15.1) of the trigger (15);

the output (15.2) of the trigger (15) is connected to the input (base) (16.1) of the amplifier-inverter (16) with the input for the backup (16.3) associated with the output (20.2) of the reference voltage source (20);

the output (16.2) of the amplifier-inverter (16) is connected to the input (17.1) of the adder (17);

the output (17.2) of the adder (17) is connected to the input (18.1) of the block of the product (18);

the input (17.3) is connected to the output (20.1) of the reference voltage source (20);

the input (18.3) of the block of the product (18) is connected to the port (9.1) of the pulse input (9);

the output (18.2) is connected to the input (19.1) of the level limiting unit and determining the sign of the signal (19);

the output (19.2) of the signal sign determination unit (19) is connected to the input (10.2) of the product block (10).

In order to prepare the input signal for the device, an intermediate conversion should be obtained by issuing pulses at a higher frequency than the frequency of the channel from which the information was received, for example, the I2C bus, then the increased pulse transmission frequency at the device input will be less than 512 kbaud (maximum bus speed I2C), but it can be more and significantly than the data transfer rate via the RS232 interface at a speed of no more than 19,200 baud.

Description of the device prototype

Breadboard-debug board ЕВ552 (prototype) [Fig. 2] consists of: a microprocessor system (1), two transistor-transistor logic units (2) and (3) for controlling the address / data bus (4), an additional optional processor (5) alternative to the central processor of the microprocessor system; RS232 connector (6); a second optional processor connected via the I2C bus (7) and a liquid crystal display (8); RAM - random access memory (9);

port (6.1) the RS232 bus connector (6) is connected to a similar RS232 port (1.1) of the microprocessor system (1);

the standard port (1.2) of the microprocessor system (1) is displayed on the prototype board space;

the duplex port (1.3) of the i2c bus of the breadboard-debug board ЕВ552 is displayed on the port (7.2) of the I2C bus connector (7);

the duplex port (2.2) of the i2c bus of the second optional processor of the EB552 breadboard and debugging board is output to the port (7.1) of the I2C bus connector (7);

port (1.4) of the EV552 development board (1) is connected to port (4.1) of the address / data bus (4)

the output (2.1) of the transistor-transistor logic unit (2) is connected to the port (4.3) of the address / data bus (4);

the output (3.1) of the transistor-transistor logic unit (2) is connected to the port (4.4) of the address / data bus (4);

the port (4.2) of the ardes / prototype data bus is connected to the control port (8.1) of the random access memory (8);

the port (4.6) of the ardes / prototype data bus is connected to the control port (9.1) of the liquid crystal display (8);

the port (4.5) of the address / data bus (4) is used to connect the optional processor (5) and is the main one in comparison with the port (5.2);

the port (4.5) of the address / data bus (4) is connected to the port (5.1) of the data bus / address of the second optional processor (5).

The claims in terms of the method

A method of converting a sequence of electrical impulses to a Manchester code, which consists in the fact that the initial sequence of impulses, normalized by speed, is processed using a program algorithm that is updated into the processor and presented in assembly language for the A51 compiler, while the transmission of information pulses is carried out with determination of the level of pulse amplitude using the comparator for a pre-set and set pulse duration, with this normalization of the period and duration of the pulse, the information bit is limited to the minimum duration and period, and the processing algorithm for the final conversion of the pulse sequence into a given code is carried out by the proposed method, characterized in that the pulse sequence is subjected to sign inversion for each even pulse by storing the input state in the previous step using the auxiliary trigger, if at the previous step the signal level was fixed, then the current calculation step is even, p after which the sequence of pulses at the input is inverted to ensure that the auxiliary trigger of the signal detector at the previous step is triggered in antiphase with respect to the main trigger, the state of the level determined by the obtained sequence of pulses with sign inversion for each even pulse, which is subjected to additional correction, is fixed at the output of the main trigger obtained in the course of fixing in the main trigger, but in general obtained as a result of the general The pulse sequence is the resulting pulse sequence in which a level change occurs when a bit of the initial pulse sequence arrives, as a result of which a bit of the initial pulse sequence arrives, the signal level changes with the inverse of the output sign, which corresponds to signal transmission in code format Manchester, and the interval and period of the pulses are not limited to the minimum values.

The claims in terms of the device

A device for implementing a method of converting a sequence of electrical pulses into a Manchester code, comprising a microprocessor system, including a basic input input system with a transistor-transistor logic unit for controlling the address / data bus, an additional optional processor, alternative to the central processor of the microprocessor system, RS232 interface with a connector , I2C bus with a connector, a second optional processor connected via I2C bus, and a liquid crystal indicator, distinguishing by the fact that a converter of an informational pulse signal into an output in the Manchester format has been introduced into the device; an optional processor connected via the I2C bus to provide a USB port, the switching circuit of the device contains a main pulse input, two triggers with triggering at an arbitrary amplitude, product blocks designed to control the trigger input; correction blocks for the output of the second trigger, and a fine-tuned amplifier for correcting the output of the second trigger, a signal offset adder and a product block with the output of the reference constant signal of a single level from the reference voltage block, and after correction of the output of the second trigger, the signal level, the amplitude of which is at least one to the module, it is limited by the unit for determining the sign of the signal sgn, interconnected so that the output signal after correction and limitation from the second trigger has an amplitude minus dyne volt for each even pulse, and plus one volt for each odd one, thus when an information bit arrives at the main input, providing switching of the first trigger with a level change, while the second trigger is in antiphase with respect to the first trigger and receives an input signal with the main input through the inverter, in contrast to the first trigger, determining the state at the previous step at zero level at the main input, which avoids the use of delay links as for Manchester converted I or delay occurrence in the program of the signal processing by the microprocessor system of the device.

Description of drawings

In Fig 1. presents a diagram of a device for implementing the method of converting electrical pulses into Manchester code. In Fig 2. presents a brief diagram of the prototype breadboard-debug board EV-552. In FIG. 3 is a diagram explaining the implementation of the proposed method. In FIG. 4 shows a change in polarity when converting unipolar pulses at the input to a signal to control a switching trigger [Fig. one; 10, 11] [Fig 3; 1, 3] devices for implementing the proposed method. In FIG. 5 is a diagram for a hardware implementation of the method [FIG. 3]. In FIG. 6 shows a General view of the indicative schematic diagram for the proposed device. In FIG. 7. and 8 show sections of the circuit diagram in scale. In FIG. 9. presents the wiring diagram of the proposed device. In FIG. 10 shows the appearance of a DV40400 liquid crystal display device. In FIG. 11 shows the appearance of a device for implementing the proposed method with a microprocessor control system. An indicative view of the industrial implementation of the proposed device in an assembly with a liquid crystal display (LCD) is shown in FIG. 12, and without the LCD in FIG. 13.

The functioning of the invention

The device of FIG. 1 operates as follows: an input information pulse signal is input 9, in which information is transmitted in binary code with a conditional unit voltage level set for the duration of a bit transmission, for example, from a preliminary encoder, then using a complex trigger [Fig. one; 9-20] the original signal is converted into a signal in which the determination of the single and zero bits is performed not by fixing a single or zero voltage level, for example, using a comparator, but in the process of changing the level, for example, when changing the level from 1.3 V to 0 In, it is believed that zero is transmitted, and when the voltage level changes from 0 V to 1.3 V, it is considered that one is transferred, or vice versa. The resulting output is introduced into the microprocessor system [figure 1; 1-8] to a regular processor port or PWM port of a pulse-width modulator, information about the output signal can be accumulated in the EEPROM AT24C64 ROM chip or another with the I2C interface, and time monitoring is synchronized using a calendar clock chip, for example PCF8583.

The implementation of the device of the invention is performed on the basis of a microprocessor system with processors AT89C51id2 and AT89C5131 on microcircuits of the product AD834 [Fig. 5]. The unit for determining the exit sign of the second trigger can be performed on a KT644a transistor with amplitude limitation using Zener diodes KC113A. Obtaining shoulders of negative voltage -1 V is performed using ADM660 microcircuits with approximate adjustment and limitation using a zener diode. Thus, when all levels of voltage cutoff are reduced to one stabilization level, and the voltage of 1.3 V from the standard series can be considered as an indicative voltage of a single level. Feedback correction of the output of the second switching trigger is performed using the KT295a high-frequency transistor, with a +7 V backup and a gain of -2 (minus two), with +7 V being the only input voltage of the backup that requires an exact substring. Thus, only one knob is precisely tuned, the rest are only tentatively calculated with a subsequent zener diode limitation.

Description of the blocks of the preliminary modeling circuit [Fig. 3], confirming the feasibility of the proposed method

The preliminary simulation circuit of the pulse signal converter (9) to the Manchester code on the main output of the circuit (6) consists of:

- two triggers with an arbitrary input amplitude (1, 2);

- two blocks of the work (3, 13, 18);

- an inverter as part of an amplifier-inverter (11) of the adder (12) and a unit voltage source (20);

- an inverter amplifier (16) with a gain of ky = -2 (minus two);

- adder (17);

- control voltage control oscilloscope (19);

- a block of signal limitation by amplitude and signal definition sgn (10).

The first trigger (1) with an arbitrary input amplitude consists of: adders (4) and (8); isolation amplifier with unit gain (5); unit for determining the input voltage module (6); block of the product (7); voltage source 1 V (9). The second trigger (2) with an arbitrary input amplitude consists of: adders (14) and (23); decoupling amplifier with unity gain (15); unit for determining the input voltage module (21); block of the product (22); voltage source 1 V (24).

First, input pulses (9) having a positive amplitude are converted into a control signal [Fig. 4.2] with an inverse polarity for each even pulse, after which the polarity of the control signal is remembered by the first trigger (1), while the input voltage is zero. Thus, at the output of the first trigger, when a pulse arrives at the input, a level change occurs, which corresponds to data transfer in the Manchester code.

Bibliography

Prototype:

1. Golov A.A. EB552. Technical publication. KTC-MK, 1998, 8 pp.

Analogs:

2. MIL-STD 1553. Getting starting manual. AIM USA. Avioncs interface mofules. Elkhorn, NE 68022.

3. USB1553-1 / 2. Single or Dual Stream MIL-STD-1552A / B. Test & Simulation module for USB. AIT USA Omaha, NE 68022.

4. US Patent 5,367,641. MIL-STD-1553 Interface device having a bus controller minor frame timer. Nov 22, 1994.

5. US Patent 5,325,359. MIL-STD-1553 Interface device having concurrent remote terminal and monitor terminal operation. Jan 28, 1994.

6. US 6212224B1. MIL-STD-1553 buffer / driver. 18 dec, 1997.

7. US 2015/0286607 A1. Determination of the state of an I2C bus. Oct 8, 2015.

8. US 5564090 A. Method apparatus for dynamical adjusting receiver squelch threshold. Oct 8, 1996.

Sources that determine the technical level of the invention

9. Remisevich T.V. Microcontrollers for embedded applications: from common approaches to the Motorola HC05 and HC08 families. M .: DODEKA, 2000, - 272 p.

10. Hammel R.L. Serial data transfer. Guide for the programmer. M.: WORLD SC PRESS, 1996, - 752 p.

11. Voloshinovsky K.I. Certificate of official registration of the computer program No. 2011515700, June 22, 2012, Program for the breadboard and debug board ЕВ552 with driver modules for the RS232 port, I2C bus, PCF8583 clock, EEPROM АТ24С64, LCD, Sevc-91 electronic corrector, and description module Ports Atmel (Intel) - compatible 8-bit processor.

12. Voloshinovsky K.I. Certificate on official registration of a computer program No. 2005611489, June 20, 2005. Module for interrogating and processing archived data of PRIZ microprocessor computers (PR3-WIN).

13. Voloshinovsky K.I. Research and testing of both instruments and systems. Textbook Allowance. - M .: MGGU, 2014 .-- 120 p.

14. Voloshinovsky K.I. Certificate on the official registration of a computer program No. 2015619051, August 24, 2015. Switching triggers on continuous elements and binary.

Terms and Definitions

15. GOST R 52070-2003. The interface is a serial serial system of electronic modules. General requirements.

Claims (2)

1. A method of converting a sequence of electrical impulses to a Manchester code, which consists in the fact that the initial sequence of impulses, normalized by speed, is processed using a program algorithm that is flashed into the processor and presented in assembly language for the A51 compiler, while the transmission of information pulses is carried out with determination of the level pulse amplitude using a comparator for a pre-configured and set pulse duration, with this normalization of the period and duration of the pulse the information bit is limited to the minimum duration and period, and the processing algorithm for the final conversion of the pulse sequence into a given code is carried out by the proposed method, characterized in that the pulse sequence is subjected to sign inversion for each even pulse by storing the input state in the previous step using the auxiliary trigger, if at the previous step the signal level was fixed, then the current calculation step is even, after which the sequence of pulses at the input is inverted to ensure that the auxiliary trigger of the signal detector at the previous step is triggered in antiphase with respect to the main trigger, the state of the level determined by the obtained sequence of pulses with sign inversion for each even pulse, which is subjected to additional correction, is fixed at the output of the main trigger, obtained during fixation in the main trigger, and the result of the conversion is followed by pulse duration is the resulting pulse sequence in which the level change occurs when a bit of the initial pulse sequence arrives, as a result of which, when the bit of the initial pulse sequence arrives, the signal level changes with the inverse of the output sign, which corresponds to signal transmission in the Manchester code format, and the interval and period of the pulses are not limited to the minimum values. 2. A device for implementing a method of converting a sequence of electrical pulses into a Manchester code, comprising a microprocessor system including a basic input input system, with a transistor-transistor logic unit for controlling the address / data bus, an additional optional processor, alternative to the central processor of the microprocessor system, interface RS232 with a connector, I2C buses with a connector, the second optional processor connected via I2C, and a liquid crystal display, I distinguish the fact that a pulsed information signal converter is output into the device in Manchester format; an optional processor connected via the I2C bus to provide a USB port, the switching circuit of the device contains a main pulse input, two triggers with triggering at an arbitrary amplitude, product blocks designed to control the trigger input; second trigger output correction blocks and an amplifier with fine tuning to correct the second trigger output, a signal offset adder and a product block, with the output of a reference constant signal of a single level from the reference voltage block, and after the second trigger output correction, the signal level, the amplitude of which is at least one to the module, it is limited by the unit for determining the sign of the signal sgn, interconnected so that the output signal after correction and limitation from the second trigger has an amplitude minus dyne volt for each even pulse, and plus one volt for each odd one, thus when an information bit arrives at the main input, providing switching of the first trigger with a level change, while the second trigger is in antiphase with respect to the first trigger and receives an input signal with the main input through the inverter, in contrast to the first trigger, determining the state at the previous step at zero level at the main input, which avoids the use of delay links as for Manchester converted I or delay occurrence in the program of the signal processing by the microprocessor system of the device.

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