CN218446655U

CN218446655U - Bus communication interface circuit

Info

Publication number: CN218446655U
Application number: CN202122766598.3U
Authority: CN
Inventors: 孙海
Original assignee: Shanghai Shiningic Electronic Technology Co ltd
Current assignee: Shanghai Shiningic Electronic Technology Co ltd
Priority date: 2021-11-10
Filing date: 2021-11-10
Publication date: 2023-02-03
Anticipated expiration: 2031-11-10

Abstract

A bus communication interface circuit is arranged in each external device for exchanging data through a bus and comprises upper communication interfaces A1 and A2 connected to the bus, a first control module connected with the communication interface A1 and a second control module connected with the communication interface A2; the first and second control modules respectively comprise a pull-up assist cell, an NFET, a control cell, and a receiver; the drain electrode of the NFET is grounded, and the source electrode of the NFET is connected with the communication interface A1 or A2; the control unit outputs a first pulse control signal gate _ n to a grid electrode of the NFET, the control unit outputs a second pulse control signal to the pull-up auxiliary unit, an input end of the receiver is connected to the communication interface A1 or A2, an output end of the pull-up auxiliary unit is connected to the communication interface A1 or A2, and the receiver outputs a signal Rev which is an input receiving stage of the control unit. Therefore, the utility model discloses can improve the communication rate of communication success rate, data transmission rate of accuracy and bus.

Description

Bus communication interface circuit

Technical Field

The utility model belongs to the technical field of bus communication, a bus communication interface circuit and reinforcing bus communication effect's communication method is related to.

Background

A bus is a common communication trunk that carries information between the various device components of the system, and is a transmission line bundle comprised of wires. The asynchronous clock bus includes a data bus and a clock bus for transmitting data and clock signals, respectively.

Referring to fig. 1, fig. 1 is a schematic diagram illustrating a connection relationship between a bus and peripheral devices in the prior art. As shown in fig. 1, the two communication interfaces A1 and A2 of the bus are connected to the power source VCC through a pull-up resistor R1 and a resistor R2, and are connected to the external device U1, the external device U2, and the external device U3 of the bus through the two communication interfaces A1 and A2. For example, an I2C (Inter-Integrated Circuit) bus is a bus for connecting a microcontroller and its peripheral devices; SDA (serial data line) and SCL (serial clock line) are both bidirectional I/O lines, and interface driving is open-drain output and needs to be connected with a power supply VCC through a pull-up resistor.

External device U1, external device U2, and external device U3 are sometimes referred to as masters (masters) and sometimes as slaves (slaves), the masters being used to enable the bus to transfer data and generate clocks to transfer data information to other devices, when any addressed device is considered a slave. The relation of master and slave, send and receive on the bus is not constant but depends on the direction of data transfer at the moment. If the host is to send data to the slave device, the host first addresses the slave device, then actively sends data to the slave device, and finally the data transfer is terminated by the host. In this case, the controller in the host is responsible for generating the timing clock and terminating the data transfer.

Referring to fig. 2, fig. 2 is a schematic diagram illustrating a communication interface of a conventional external device (e.g., U1, U2, and U3 in fig. 1). As shown in fig. 2, the external device U1, the external device U2, and the external device U3 are connected to the bus through the communication interface A1 and the communication interface A2, and the communication interface A1 and the communication interface A2 of the bus need to be connected to the power source VCC through the pull-up resistors R1 and R2.

Each external device typically contains an NFET, a control unit and a receiver. The drain electrode of the NFET is grounded, the source electrode of the NFET is connected with a communication interface A, the control unit outputs a first pulse control signal to the grid electrode of the NFET, the input end of the receiver is connected with the communication interface A1 or the communication interface A2, the signal Rev is an output signal of the receiver, and the signal Rev is an input receiving stage of the control unit.

Referring to fig. 3, fig. 3 is a signal waveform schematic of a conventional communication interface circuit. As shown in fig. 3, when the port NFET is turned off, waveform a has a pull-up resistor on the bus to implement a high level signal, and the resistor and parasitic capacitance on the bus create an RC delay, so that the rising edge of waveform a is slow. However, the rising edge of the waveform a signal is slow, and the receiving stage Rev on the waveform a receives a signal with a single-side delay, which may cause a communication error when the delay is too large.

That is, since each bus interface of each device has a certain equivalent capacitance, when the number of devices extended on the bus reaches a certain number, the total capacitance is too large, and the RC delay is too large, so that the rising edge of the bus a is slow to cause delay of received signals, which may cause communication errors. The faster the communication rate, the more likely communication errors will result.

SUMMERY OF THE UTILITY MODEL

In order to solve the above technical problem, the utility model provides a bus communication interface circuit and communication method of reinforcing bus communication effect, its technical scheme as follows:

a bus communication interface circuit is arranged in each external device which exchanges data through a bus, and comprises:

the communication interface A1 and the communication interface A2 are connected to the bus, and the communication interface A1 and the communication interface A2 are connected with a power VCC through a pull-up resistor R1 and a pull-up resistor R2 respectively;

the first control module is connected with the communication interface A1, and the second control module is connected with the communication interface A2, wherein the first control module and the second control module respectively comprise a pull-up auxiliary unit, an NFET (N-channel field effect transistor), a control unit and a receiver; the drain of the NFET is grounded, and the source of the NFET is connected with a communication interface A1 or a communication interface A2; the control unit outputs a first pulse control signal gate _ n to the grid electrode of the NFET, the control unit outputs a second pulse control signal to the pull-up auxiliary unit, the input end of the receiver is connected to a communication interface A1 or a communication interface A2, the output end of the pull-up auxiliary unit is connected to the communication interface A1 or the communication interface A2, the receiver outputs a signal Rev, and the signal Rev is an input receiving stage of the control unit;

when the first pulse control signal gate _ n changes from a high level to a low level, the second pulse control signal gate _ p simultaneously outputs a control signal for a time t; at this time, the first pulse control signal gate _ n goes low, the NFET is turned off, and the pull-up resistor R1 pulls up the level of the communication port A1 or the pull-up resistor R2 pulls up the level of the communication port A2; and the second pulse control signal gate _ p controls the pull-up auxiliary unit to output a high level within time t, so as to increase the rising edge speed of the communication interface A1 or the communication interface A2 from a low level to a high level.

Further, the pull-up assist unit is a PFET, a gate of the PFET is connected to a second pulse control signal gate _ p, a source of the PFET is connected to a power source VCC, and a drain of the PFET is connected to the communication interface A1 or the communication interface A2.

Furthermore, the time t is a short pulse signal, which is less than the duration of the low level of the first pulse control signal gate _ n.

Further, one of the N pieces of external equipment is a master, and one or more of the rest N-1 pieces of external equipment are slaves.

According to the above technical solution, the utility model discloses in the embodiment of bus communication interface circuit and the communication method of reinforcing bus communication effect, following beneficial effect has:

(1) the success rate of communication is improved;

(2) the method has the advantages that more equipment on the bus is realized, and the data transmission accuracy is high under the condition that the equivalent capacitance of each equipment bus interface is unchanged;

(3) and the communication speed of the bus is improved.

Drawings

FIG. 1 is a schematic diagram of a prior art bus and peripheral device connection

FIG. 2 is a schematic circuit diagram of a conventional communication interface

FIG. 3 is a signal waveform diagram of a prior art communication interface circuit

FIG. 4 is a schematic diagram of a preferred embodiment of the communication interface circuit of the present invention

FIG. 5 shows the signal waveform of the communication interface circuit of the present invention

Detailed Description

The following describes the present invention in further detail with reference to fig. 4-5.

Referring to fig. 4 in conjunction with fig. 1, fig. 4 is a schematic diagram of a bus communication interface circuit according to a preferred embodiment of the present invention. As shown in fig. 1, in the embodiment of the present invention, a plurality of external devices (e.g., external device U1, external device U2, and external device U3) may be connected to the bus, and the bus communication interface circuit of the present invention may be disposed in each external device that interacts data through the bus.

The bus communication interface circuit comprises a communication interface A1 and a communication interface A2 which are connected to the bus, a first control module connected with the communication interface A1 and a second control module connected with the communication interface A2. The communication interface A1 and the communication interface A2 are connected with a power supply VCC through a pull-up resistor R1 and a pull-up resistor R2. Preferably, the pull-up resistor R1 and the pull-up resistor R2 may have the same resistance.

In general, one of the external devices is a master, one or more of the other external devices are slaves, the master is configured to send data, and the slaves are configured to receive data, or the slaves are configured to receive data and process the data and then send the data to the master.

Each of the external devices includes a first control module connected to the communication interface A1 and a second control module connected to the communication interface A2, which may be the first control module or the second control module shown in fig. 4.

The first control module and the second control module respectively comprise a pull-up auxiliary unit, an NFET, a control unit and a receiver; the drain of the NFET is grounded, and the source of the NFET is connected to communication interface A1 or communication interface A2.

In the preferred embodiment of the present invention, the control unit outputs a first pulse control signal gate _ n to the gate of the NFET, the control unit outputs a second pulse control signal to the pull-up auxiliary unit, the input end of the receiver is connected to the communication interface A1 or the communication interface A2, the output end of the pull-up auxiliary unit is connected to the communication interface A1 or the communication interface A2, the receiver outputs a signal Rev, and the signal Rev is the input receiving stage of the control unit.

Preferably, the pull-up assist unit may be a PFET, a gate of the PFET is connected to the second pulse control signal gate _ p, a source of the PFET is connected to the power source VCC, and a drain of the PFET is connected to the communication interface A1 or the communication interface A2.

It should be noted that, the communication interface circuit of the present invention, similar to the conventional communication interface circuit, is that the bus signal mainly has the level value realized by NFET and pull-up resistor R1 or R2 on the bus; unlike conventional communication interface circuits, the present invention adds a pull-up assist unit (e.g., a PFET) that only assists pull-up resistor R1 or R2 to quickly achieve high levels, thereby achieving the goal of increasing rising edge speed.

Referring to fig. 5, fig. 5 is a schematic diagram of a signal waveform of the communication interface circuit of the present invention. As shown in fig. 5, when the first pulse control signal gate _ n changes from a high level to a low level, the second pulse control signal gate _ p changes from a high level to a low level at the same time, and the low level of the second pulse control signal gate _ p changes to a high level for a time t; at this time, the first pulse control signal gate _ n goes low, the NFET is turned off, and the pull-up resistor R1 pulls up the level of the communication port A1 or the pull-up resistor R2 pulls up the level of the communication port A2; and the second pulse control signal gate _ p controls the pull-up auxiliary unit to output a high level within time t, so as to increase the rising edge speed of the communication interface A1 or the communication interface A2 from a low level to a high level.

The rising edge of the communication interface a signal from low to high level shown in fig. 5 is almost vertical compared to the graph shown in fig. 3. That is to say, the utility model discloses a bus communication interface circuit can solve current interface circuit effectively and realize that bus A rises to lead to slowly that received signal delays along, and the communication error that causes.

Wherein the time t is less than a low level time for which the first pulse control signal gate _ n lasts. Because the PFET is in the off state after the short period of time tDRIVE is finished, the execution of the bus communication protocol is not influenced. Furthermore, the time t is a short pulse signal, which is less than the duration of the low level of the first pulse control signal gate _ n.

Next, a description will be given of a communication method for enhancing bus communication effect provided by the present invention, which can be applied to communication between one host and one slave, and also can be applied to communication between one host and multiple slaves.

Referring to fig. 4, the master for transmitting data and the slave for receiving data respectively include the bus communication interface circuit. The communication method for enhancing the bus communication effect is used for communication between external devices for exchanging data through a bus, and the data communication between the host and the slave comprises the following steps:

step S1: a first control module and a second control module in the host respectively generate a first pulse control signal gate _ n and a second pulse control signal gate _ p according to a protocol to control the communication interface A1 and the communication interface A2 to send data; when the first pulse control signal gate _ n changes from a high level to a low level, the second pulse control signal gate _ p changes from a high level to a low level at the same time, and the low level of the second pulse control signal gate _ p changes to a high level after lasting for a time t; at this time, the first pulse control signal gate _ n goes low, the NFET is turned off, and the pull-up resistor R1 pulls up the level of the communication port A1 or the pull-up resistor R2 pulls up the level of the communication port A2; the second pulse control signal gate _ p controls the pull-up auxiliary unit to output a high level within a time t, and increases the rising edge speed of the communication interface A1 or the communication interface A2 from the low level to the high level; wherein the time t is less than a low level time for which the first pulse control signal gate _ n lasts.

That is, each time the first pulse control signal gate _ n controls the NFET to be turned off, the second pulse control signal gate _ p controls the PFET to be turned on, allowing the bus A signal to rise rapidly, and the second pulse control signal gate _ p turns the PFET back off immediately. That is, the time t for turning on the PFET is very small, and only the instant auxiliary bus pull-up resistor increases the rising edge speed of the A signal, and does not influence the bus communication protocol.

Step S2: the first control module and the second control module of the slave respectively receive data sent by the first control module and the second control module of the host for controlling the communication interface A1 and the communication interface A2, and respectively receive the data through the receivers of the first control module and the second control module, and the receivers output signals Rev to the respective corresponding control units.

To sum up, the utility model discloses a bus communication interface circuit and reinforcing bus communication effect's communication method can improve the communication success rate, has increased the equipment quantity that interface circuit on the bus can realize on more buses, and has improved the communication rate of bus.

What has just been said is the preferred embodiment of the present invention, the embodiment is not used for limiting the patent protection scope of the present invention, therefore all the equivalent structural changes made by the contents of the description and the drawings of the present invention should be included in the protection scope of the present invention.

Claims

1. A bus communication interface circuit provided in each of external devices that exchange data via a bus, comprising:

the first control module is connected with the communication interface A1, and the second control module is connected with the communication interface A2, wherein the first control module and the second control module respectively comprise a pull-up auxiliary unit, an NFET (N-channel field effect transistor), a control unit and a receiver; the drain electrode of the NFET is grounded, and the source electrode of the NFET is connected with a communication interface A1 or a communication interface A2; the control unit outputs a first pulse control signal gate _ n to the grid electrode of the NFET, the control unit outputs a second pulse control signal to the pull-up auxiliary unit, the input end of the receiver is connected to a communication interface A1 or a communication interface A2, the output end of the pull-up auxiliary unit is connected to the communication interface A1 or the communication interface A2, the receiver outputs a signal Rev, and the signal Rev is input to the control unit.

2. The bus communication interface circuit of claim 1, wherein the pull-up assist element is a PFET, a gate of the PFET is connected to a second pulse control signal gate _ p, a source of the PFET is connected to a power source VCC, and a drain of the PFET is connected to the communication interface A1 or the communication interface A2.

3. The bus communication interface circuit as claimed in claim 2, wherein the time t is a short pulse signal less than the duration of the first pulse control signal gate _ n.