CN101770443B - Time sequence adjusting method for internal IC (integrated circuit) bus, corresponding device and system thereof - Google Patents
Time sequence adjusting method for internal IC (integrated circuit) bus, corresponding device and system thereof Download PDFInfo
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- CN101770443B CN101770443B CN2009100003901A CN200910000390A CN101770443B CN 101770443 B CN101770443 B CN 101770443B CN 2009100003901 A CN2009100003901 A CN 2009100003901A CN 200910000390 A CN200910000390 A CN 200910000390A CN 101770443 B CN101770443 B CN 101770443B
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Abstract
The embodiment of the invention discloses a time sequence adjusting method for an I2C bus. The method comprises the steps of receiving signals on an SCL (serial clock) bus and an SDA (serial data) bus, judging the transmission directions of the signals on the I2C bus according to the received signals on the SCL bus and the SDA bus, outputting a signal delay time T on the SDA bus according to the judged direction when the signal on the SCL bus is located at each falling edge, and outputting the signal on the SCL bus according to the judged direction. The embodiment of the invention further provides a corresponding device and a system. In the technical scheme, the transmission directions of the signals are judged according to the signals transmitted on the I2C bus, and the delay time T outputs the SDA signal when the SCL signal is located at the falling edge, so as to ensure constant output on the SDA bus when in jumping of the signal on the SCL bus, thereby reducing time sequence errors on the I2C bus.
Description
Technical field
The present invention relates to the electronic communication field, be specifically related to a kind of I
2C bus timing control method, related device and system.
Background technology
Internal integrated circuit I
2C bus (Inter-Integrated Circuit Bus) is by the twin wire universal serial bus of Philip PHILIPS company exploitation, is used to connect microcontroller and peripherals thereof.I
2The C bus for the audio and video equipment exploitation, nowadays is mainly used in the server admin and uses at first.Adopt I
2The C bus can realize the communication between a plurality of equipment, is convenient to control, visit to equipment, therefore, is widely used in the electronic communication field.
I
2The C bus is to be made up of serial data (SDA, Serial Data) bus and serial time clock line (SCL, Serial Data), and the data of transmitting between the equipment are to be carried on the SDA I
2Transmit on the C bus the kind of signal have three kinds, be respectively: commencing signal, end signal and answer signal.Wherein, commencing signal is meant: when SCL was high level, SDA was a low level from the high level saltus step, at this moment, and I
2One of them equipment is to another equipment transmission data in the equipment at C bus two ends; End signal is meant: when SCL was low level, SDA was a high level from low transition, at this moment, and I
2One of them device end is to another equipment transmission data in the equipment at C bus two ends; Answer signal is meant: I
2After one of them equipment receives 8 bit bit data in the equipment at C bus two ends, send low level pulse to another equipment, the response that receives the 8bit data as this equipment is notified to corresponding equipment with it.
At I
2When being defined in SCL in the C agreement and being high level, SDA has the saltus step of high-low level, then representes I
2In the equipment at C bus two ends, an end sends beginning/the finish command of read/write operation to the other end.Between the beginning and end of a read/write operation, when the last level of SDA changed, requiring the level on the SCL was low level, and this is correct I
2The C sequential, as shown in Figure 1.Otherwise receiving equipment is thought and has been received wrong signal.Common I
2The sequential mistake of C bus occurs in the negative edge of SCL, and promptly the level on the SCL is in negative edge, and the level on the SDA also is in the transitional states of high-low level, at this moment, and I
2Sequential on the C bus is wrong sequential, and is as shown in Figure 2.
In order to reduce I
2Sequential on the C bus makes a mistake, and way of the prior art has two kinds usually, and a kind of is as shown in Figure 3, the I between device A and equipment B
2On the SCL of C bus and the SDA bus, be connected to ground capacitance C1, C2 respectively,, make the negative edge of SDA slow down and/or the negative edge steepening of SCL, increase I through regulating the appearance value of the ground capacitance that is connected on SCL and the SDA
2C sequential nargin.Need to prove that it is that the level that SCL is on negative edge and the SDA begins the time interval between the saltus step that sequential nargin is appreciated that, large interval, the probability that wrong sequential then occurs is little, on the contrary the time interval is little, I then
2The probability that sequential on the C bus makes a mistake is big.Adopt this method to realize to I
2The shortcoming of the adjusting of the sequential of C bus is that the scope of regulating is little, can not reach usually and avoid I fully
2The purpose of the sequential mistake on the C bus.
The another kind of I that regulates
2The method of the sequential on the C bus is between two equipment of communication, to insert isolating device, and this isolating device is to I
2The effect that sequential on the C bus is regulated is quite limited, and the scope of promptly regulating is also very little, makes to regulate I
2Sequential mistake DeGrain on the C bus.
Summary of the invention
The embodiment of the invention provides a kind of I
2C bus timing control method, related device and system can be according to design demand, and selection needs range of adjustment, can effectively reduce sequential mistake on the I2C bus.
The embodiment of the invention provides a kind of internal integrated circuit I
2C bus timing control method comprises:
Signal on the reception serial clock SCL bus and the signal on the serial data SDA bus;
According to signal on the said SCL bus that receives and the signal on the SDA bus, judge I
2The direction of signal transmission on the C bus;
When the signal on the SCL bus is in each negative edge, according to the said direction of judging, with T output signal delay time on the SDA bus;
According to the said direction of judging, the signal on the SCL bus is exported.
The embodiment of the invention also provides a kind of internal integrated circuit I
2C bus timing regulating device comprises:
Receiving element is used to receive signal and the signal on the serial data SDA bus on the serial clock SCL bus;
Judging unit is used for according to signal on the said SCL bus that receives and the signal on the SDA bus, judges I
2The direction of signal transmission on the C bus;
Delay cell is used for when the signal on the SCL bus is in each negative edge, according to the said direction of judging, with T signal delay time on the SDA bus;
Transmitting element is used for the direction judged according to said, with signal and the output of the signal on the SCL bus behind the time delay T on the SDA bus.
The embodiment of the invention also provides a kind of communication system, comprising:
First equipment is used on serial clock SCL bus, sending signal, on serial data SDA bus, sends signal;
Internal integrated circuit I
2C bus timing regulating device is used to receive the signal that said first equipment sends on serial clock SCL bus, the signal that on serial data SDA bus, sends according to signal on the said SCL bus that receives and the signal on the SDA bus, is judged I
2The direction of signal transmission on the C bus; When the signal on the SCL bus is in each negative edge; According to the said direction of judging,, send signal and the signal on the SCL bus behind T time delay on the SDA bus to second equipment with T signal delay time on the SDA bus;
Second equipment is used to receive said internal integrated circuit I
2Signal on the SDA bus that C bus timing regulating device is sent behind the time delay T and the signal on the SCL bus.
The embodiment of the invention adopts PLD according to being transmitted in SCL signal and SDA signal wherein, judges the direction of signal transmission, and the SCL signal is not processed output; And when the SCL signal is in negative edge; Time delay, T was with the output of SDA signal, thereby had guaranteed at the SCL signal during in saltus step, and is constant during output on the SDA signal; Therefore, reduced I
2Sequential mistake on the C bus.Guaranteed I
2The signal transmission is efficient, accurate on the C bus.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do one to the accompanying drawing of required use in embodiment or the description of the Prior Art below introduces simply; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work property, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is through I
2Correct sequential chart during C bus transfer signal;
Fig. 2 is through I
2The sequential chart of mistake during C bus transfer signal;
Fig. 3 regulates I in the prior art
2The system schematic of the signal sequence that transmits on the C bus;
Fig. 4 is a kind of I that the embodiment of the invention one provides
2C bus timing control method general flow chart;
Fig. 5 is a kind of I that the embodiment of the invention two provides
2C bus timing control method general flow chart;
Fig. 6 is a kind of internal integrated circuit I that the embodiment of the invention three provides
2The logic composition diagram of C bus timing regulating device;
Fig. 7 is a kind of internal integrated circuit I that the embodiment of the invention four provides
2The logic composition diagram of C bus timing regulating device;
Fig. 8 is the logic composition diagram of a kind of communication system of providing of the embodiment of the invention five.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
The embodiment of the invention provides a kind of I
2C bus timing control method and internal integrated circuit I
2C bus timing regulating device below is elaborated respectively.
Embodiment one
The embodiment of the invention provides a kind of I
2C bus timing control method for the ease of understanding the method that the embodiment of the invention provides, at first, is done brief description to each equipment in the system that carries out this method, and said system comprises that at least two are passed through I
2The equipment that the C bus communicates is because I
2The C bus is a kind of universal serial bus, has only an equipment sending data to give another equipment at synchronization, and the data of promptly on a moment SDA, transmitting have only a direction.In order to guarantee I
2Sequential on the C bus is correct, in embodiments of the present invention at I
2Increase a PLD on the C bus, this PLD control SDA output timing reaches and reduces I
2The purpose of sequential mistake on the C bus.For the ease of the explanation of following literal, will adopt I
2At least two equipment that the C bus communicates are called A equipment and B equipment respectively.
Carry out a kind of I in the face of this PLD down
2C bus timing control method is done explanation, participates in shown in Figure 4ly, and this method comprises:
Step 1: receive I
2Signal on the C bus promptly receives signal and the signal on the SDA bus on the SCL bus;
Step 2:, judge I according to signal on the SCL bus that receives and the signal on the SDA bus
2The direction of signal transmission on the C bus;
Wherein, judge I in the step 2
2The direction of signal transmission specifically can be according to I on the C bus
2The C agreement, signal on the SCL bus that analysis receives and the signal on the SDA bus obtain I
2The direction of signal transmission on the C bus.
Step 3: when each negative edge of SCL signal,, SDA is gone up T output signal delay time of transmission according to the direction of the signal transmission of judging;
Wherein, time delay, T was far smaller than I
2The C bus cycles, normally tens nanoseconds (ns), the deviser can select the size of concrete T.
Step 4: the signal on the SCL bus is exported.
Through the explanation of step 1 to step 4, PLD is judged the direction of signal transmission through being transmitted in SCL signal and SDA signal wherein in this method; The SCL signal is not processed output, and when the SCL signal is in negative edge, time delay, T was with the output of SDA signal; Thereby guaranteed at the SCL signal during in saltus step; Output on the SDA signal is constant, therefore, has reduced I
2Sequential mistake on the C bus has guaranteed I
2The signal transmission is efficient, accurate on the C bus.
Embodiment two
The embodiment of the invention provides a kind of I
2C bus timing control method comprises:
Steps A 1: signal on the reception SCL bus and the signal on the SDA bus, output SCL signal;
Wherein, need to prove that the device of execution in step A1 can be a PLD, this PLD is equivalent to transmission line at this moment, and does not know that SDA and SCL go up the direction of transmission signals.This logical device is equivalent to path for the signal that transmits on the SCL bus, except detecting the signal on the SCL, can be left intact to the signal on the SCL and directly export.
Steps A 2: judge whether to receive I
2The C commencing signal is if get into steps A 3;
Wherein, an I of this logical device in the steps A 2
2The I of C EBI and an equipment
2The C EBI links to each other, another I in the logical device
2The I of C EBI and another equipment
2The C EBI links to each other, and promptly this PLD is positioned at two and passes through I
2Between the equipment of C bus communication, be used to adjust I
2The C bus timing.This PLD is judged two I respectively
2SDA on the C EBI and SCL go up the relation of the electric signal of transmission, judge whether to receive commencing signal, and promptly SCL is a high level, and to low transition, represent that an equipment begins to transmit data to another equipment this moment to SDA by high level.
Need to prove that also logical device is carried out and judged whether to receive I in the steps A 2
2The concrete grammar of C commencing signal is: judge whether the last level of SCL is high level, if then judge this I when SDA is negative edge
2The C EBI receives I
2The C commencing signal.
Steps A 3: according to the I that receives
2The C commencing signal obtains the sense that SCL and SDA go up transmission, and promptly signal is from receiving I
2The I of C commencing signal
2This logical device of C EBI input is from another I
2This logical device of C EBI output;
For the ease of later explanation, the equipment that will export signal here is called main frame, and the equipment that receives signal is called slave.The direction of the signal of the i.e. last transmission of this moment SCL and SDA is from the main frame to the slave.
Steps A 4: receive I
2After the C commencing signal, the clock number on the record SCL bus specifically can be the rising edge number and the negative edge number of record;
When steps A 5:SCL bus is gone forward 8 negative edges, with exporting to slave after the data delay time T that receives on the direction from the main frame to the slave on the SDA bus;
In fact, also can be to each the clock signal delay time T on the SCL bus ' back output, time delay, T ' was less than the time T of this device to the signal delay on the SDA bus usually, just can reach sequential output preferably.For example: T ' is 30ns, and T is 50ns, and T ' and T are far smaller than the clock period on the SCL.
Wherein, Need to prove that also the time T, the T ' that postpone in the steps A 5 are normally pre-configured, can be the code that this logical device input is finished writing in advance; Regulation is T, T ' to time delay of data in this code, the unit of T and T ' normally nanosecond the order of magnitude.
Steps A 6: whether the rising edge number of judging SCL is 8, if, get into steps A 7, if not, get into steps A 4;
Steps A 7: obtain SCL when the 8th rising edge, the signal value that SDA is last;
Wherein, the signal in the steps A 7 on the SDA is high or ground level, and high level is represented read operation usually, and low level is represented write operation.Also need to prove, at I
2Signal is to transmit with the form of byte on the C bus, and promptly 8 clock period on the SCL can be transmitted a byte, and the first seven transmission of first byte of transmission is the address of slave usually, and two are passed through I
2The bytes in that the C bus carries out transmitting between the equipment of transmission signals at every turn is unrestricted, still, all needs a response signal ACK after each byte, and main frame is carried out corresponding the operation according to the ack signal that receives.It will be appreciated that also main frame discharges the SDA bus after having sent each byte, slave sends ack signal and takies the SDA bus.Usually, it is that low level signal is given main frame that slave sends ack signal, can send the notice of next byte as main frame.
Steps A 8: according to SCL signal on the SDA bus when the 8th rising edge, the transmission direction of obtaining next byte;
Usually; The transmission direction of obtaining in the steps A 8 comprises: if the SDA that gets access in the steps A 7 is a high level; Then to judge this byte be that the main frame requirement is carried out read operation to slave to PLD, and the transmission direction of then judging next byte on the SDA bus is to main frame by slave; If the SDA that obtains in the steps A 7 is a low level, then to judge this byte be that the main frame requirement is carried out write operation to slave to PLD, and the transmission direction of then judging next byte on the SDA bus is to slave by main frame.
It will be appreciated that also the signal that on the I2C bus, transmits is between commencing signal and end signal; The transmission direction of SCL bus is constant; Direction for judging always according to commencing signal, for example in the present embodiment, the direction of SCL is the direction of main frame to slave always; After receiving end signal, this PLD rejudges the direction of SCL again.
Steps A 9: with on the SCL bus during the 9th negative edge, on the direction on the SDA bus from the slave to the main frame, the data delay time T that receives is exported to main frame;
Through the explanation of above steps A 1 to steps A 9, PLD is gone up the signal on signal and the SCL according to the SDA that receives in this method, judges the direction of signal transmission, the bound-time of SDA signal is deferred to after the negative edge of SCL minimizing I
2Sequential mistake on the C bus, in the time of can realizing that main frame sends the read or write order to slave, the slave of receiving end can receive correct order.
This method can also comprise:
Steps A 10: with the clock number zero clearing of SCL of record, since 1 record again;
Steps A 11:, when the SCL bus that writes down is again gone forward 8 negative edges, export after the data delay time T that receives on the SDA bus according to the transmission direction of the next byte of obtaining in the steps A 8;
Steps A 12: on the SCL bus of record again during the 9th negative edge, the signal on the direction that the transmission direction of obtaining in transmission direction on the SDA bus and the steps A 8 is opposite, time delay, T exported;
Wherein, need to prove, after steps A 11; Be PLD according to the transmission direction of the next byte of judging, after the data transmission of 8 bytes is finished, when the 9th clock; An end equipment that receives byte should send ack signal; Therefore, at 9 clock negative edges of the 8th clock negative edge to the during this period of time, the transmission direction of data is opposite with the transmission direction of preceding 8 clocks on the SDA bus.Therefore, in steps A 12, when the 9th clock negative edge, according to the direction in the above explanation, the signal on the SDA that obtains should be exported according to this direction behind the T signal delay time.
Steps A 13: when obtaining again on the SCL bus of record the 9th rising edge, the value of the signal on the opposite direction of the transmission direction of obtaining in transmission direction and the steps A 8 on the bus of SDA;
Wherein, In steps A 12 and the steps A 13; On the SCL bus during the 9th clock period the signal of (the 9th clock period comprises that the 9th rising edge and the 9th negative edge are constantly) last transmission of SDA be ack signal, the transmission direction of the byte of judging in the transmission direction of this ack signal and the steps A 8 is opposite.
Steps A 14: according to the value of obtaining signal on the SDA bus in the steps A 13, judge whether to continue the transmission byte, if, get into steps A 10, if not, get into steps A 15;
Wherein, Need to prove that above steps A 10 to steps A 14 is to have realized the directly data of second byte of transmission of main frame and slave, because between main frame and slave; Between a commencing signal and an end signal, can transmit a plurality of bytes, the number of byte is unrestricted.But, because I
2C agreement regulation, transmit a byte at every turn after, receiving end will send ACK and give an end that sends byte.Therefore, the situation for a plurality of bytes of transmission needs the cycling of execution in step A10 to steps A 14.
Also it will be appreciated that, judge whether in the steps A 14 that continuing to transmit byte specifically can be:, judge whether to continue the transmission byte according to the value of obtaining signal on the SDA bus in the steps A 13; Usually, when ack signal is low level, think that main frame can continue transmission signals; If that is: signal value is 0; Then get into steps A 10,, then get into steps A 15 if signal value is 1.
Steps A 15: judge whether to receive I
2The C end signal is if can think that then this method finishes.
Wherein, judge whether to receive I in the steps A 15
2The C end signal specifically can be: judge whether this PLD receives I in the time that is provided with
2The C end signal is not if directly end operation receives I if having in the time that is provided with
2C end signal, then also process ends after the time that surpass to be provided with.
Need to prove; In steps A 1 to steps A 15; PLD is not done any processing to the signal that transmits on the SCL bus; Promptly a port from this device receives the signal on the SCL bus, and another port from this device transfers out the signal on this SCL bus again, at an I
2C commencing signal and an I
2Between the C end signal, the direction of the signal that transmits on the SCL bus is constant.This PLD mainly is to do detection to the signal on the SCL bus; According to the clock signal on the SCL bus; As judge side signal transmission on the SDA bus to basis for estimation, according to side signal transmission on the SDA bus of judging to, the signal on the SDA bus is done delay; Thereby more intelligence guarantees I more efficiently
2The correctness of the sequential on the C bus.
Explanation through above steps A 1 to steps A 15; Can draw this PLD according to SCL that receives and the signal on the SDA bus; Judge the transmission direction of signal on SCL and the SDA bus, according to the transmission direction of signal on SCL that judges and the SDA bus, with SCL when the negative edge; T signal delay time that transmits on the SDA bus reduces I thereby reach
2The purpose of C bus timing mistake.This PLD can be easy to arrive designing requirement the time T that will postpone.Usually the time that postpones is nanosecond ns level.Also need to prove, usually I
2The frequency of C bus is 400KHz, and the cycle is 2.5us, and to the requirement of PLD be to the data delay time on the SDA bus be tens nanoseconds.
Adopt another advantage of this method to be, PLD is flexible to the adjusting of sequential, and only needing to change logical code just can the control lag time, and the scope of adjusting is bigger, need not revise hardware.
Embodiment three
The embodiment of the invention provides a kind of internal integrated circuit I
2C bus timing regulating device, referring to shown in Figure 6, this internal integrated circuit I
2C bus timing regulating device comprises: receiving element 11, judging unit 21, delay cell 31 and transmitting element 41.
Wherein, receiving element 11 is used to receive I
2Signal on the C bus promptly receives SCL signal and SDA signal;
Judging unit 21 is used for judging I according to the SCL signal and the SDA signal that receive
2The direction of signal transmission on the C bus;
Delay cell 31 is used for when the SCL signal is in each negative edge, according to the direction of judging, SDA is gone up the signal delay T of transmission;
Transmitting element 41 is used for the signal on the SCL is not processed output and with the output of the signal on the SDA bus behind the time delay T.
Through above a kind of internal integrated circuit I that the embodiment of the invention is provided
2The explanation of C bus timing regulating device, this device are judged the direction of signal transmission through being transmitted in SCL signal and SDA signal wherein; The SCL signal is not processed output, and when the SCL signal is in negative edge, time delay, T was with the output of SDA signal; Thereby guaranteed at the SCL signal during in saltus step; Constant during output on the SDA signal, therefore, reduced I
2Sequential mistake on the C bus.Guaranteed I
2The signal transmission is efficient, accurate on the C bus.
Embodiment four
The embodiment of the invention provides a kind of internal integrated circuit I
2C bus timing regulating device, this internal integrated circuit I
2C bus timing regulating device also comprises: receiving element 11, judging unit 21, delay cell 31 and transmitting element 41.A kind of internal integrated circuit I that the embodiment of the invention provides
2C bus timing regulating device is similar with the device that enforcement three provides, still, and the internal integrated circuit I that the embodiment of the invention provides
2Each logical block of C bus timing regulating device can also comprise a plurality of functional units, does detailed explanation below in conjunction with accompanying drawing 7.
Wherein, judging unit 21 comprises: first judging unit 201, first acquiring unit 202, recording clock unit 203; Delay cell 31 comprises: first delay cell 301.Need to prove that receiving element 11 receives signal and the signal on the SDA bus on the SCL bus.
First judging unit 201 judges whether to receive I
2The C commencing signal is if notify first acquiring unit 202;
First acquiring unit 202 is according to the I that receives
2The C commencing signal obtains the direction that SCL and SDA go up the signal of transmission, and promptly signal is from receiving I
2The I of C commencing signal
2This logical device of C EBI input is from another I
2This logical device of C EBI output;
I is received in recording clock unit 203
2After the C commencing signal, the clock number of record SCL specifically can be the rising edge number and the negative edge number of record;
Transmitting element 40, is exported the signal on the SCL with the signal output on the SDA after postponing based on obtaining the direction that SCL and SDA go up the signal of transmission.
Through above explanation to this PLD, this logical device first acquiring unit 202 is according to the I that receives
2The C commencing signal, obtain the direction of signal that SCL and SDA go up transmission after, SDA is gone up from I
2After the C commencing signal, I takes place thereby reduce in each the bit signal T time delay output on first byte when transmitting first byte
2C sequential mistake.
Usually at I
2After the C commencing signal, first byte of the last transmission of SDA is a control byte, and this control byte generally includes address code and controlled quentity controlled variable, and promptly high 7 of first byte is address code, and lowest order is controlled quentity controlled variable (controlled quentity controlled variable generally includes and reads or write operation).Therefore, this internal integrated circuit I
2C bus timing regulating device also should realize reducing except that first byte, I during other byte transmission
2The function of the mistake of the sequential on the C bus.Referring to following detailed description.
This internal integrated circuit I
2Delay cell 31 in the C bus timing regulating device also comprises second delay cell 302; SCL that is used for obtaining according to first acquiring unit 202 and SDA go up the direction of the signal of transmission; With on the SCL bus during the 9th negative edge; The T output of transmitting on SDA bus signal delay time, the signal of transmission is in the opposite direction on SCL that obtains in the direction of this signal and first acquiring unit 202 and the SDA.Wherein, need to prove, in preceding 8 clocks and the 9th clock, be transmitted in the in the opposite direction of signal on the SDA bus.The 9th clock, promptly from the time of the negative edge of 9 clocks of negative edge to the of the 8th clock, the signal that transmits on the SDA bus is an ack signal, the direction of the byte of the direction of ack signal and preceding 8 clock transfer is opposite.Therefore, in second delay cell 302, the signal of delay is on the basis according to the transmission direction judged, obtains the signal on the SDA bus, again according to the direction of having judged with T output signal delay time.
Wherein, need to prove, during the 9th SCL clock, the last transmission of SDA be the response signal ACK after receiving trap receives this byte, therefore, direction be with first acquiring unit 202 in the SCL that obtains and SDA go up the in the opposite direction of the signal that transmits.
This internal integrated circuit I
2Judging unit 21 in the C bus timing regulating device can also comprise: second judging unit 204, second acquisition unit 205, the 3rd acquiring unit 206, zero clearing unit 207.
Wherein, second judging unit 204, the rising edge number of judging SCL whether be 8 if, notice second acquisition unit 205,
The transmission direction of the next byte that the 3rd acquiring unit 206 will obtain sends to first delay cell 301; After the SCL clock number of record in the recording clock unit 203 was 9, zero clearing unit 207 was 203 zero clearings of recording clock unit, and from 1 opening entry SCL clock number again, promptly zero clearing unit 207 receives I at device
2After the C commencing signal, the clock number on each SCL arrives 9 backs with regard to zero clearing, again record.
The transmission direction of the next byte that first delay cell 301 also is used for will obtaining according to the 3rd acquiring unit 206, during with the negative edge on preceding 8 the SCL buses after the zero clearing, the data delay time T that SDA is last, the data output after transmitting element 40 will postpone.When second delay cell 302 also was used for after zero clearing the 9th negative edge, with the data delay time T on the SDA, the direction that need to prove the signal of delay was during with preceding 8 clocks, the last transmission signals of SDA in the opposite direction.
Through above explanation, this internal integrated circuit I
2C bus timing regulating device can realize guaranteeing I
2I after the C commencing signal
2The correctness of transmission time sequence on the C bus.
Need to prove that also this judging unit 21 can also comprise: the 3rd judging unit 208 and the 4th judging unit 209.Wherein, the 3rd judging unit 208 is used for according on the SCL bus that receives during the 9th rising edge, the value of the signal on the bus of SDA on the direction in the opposite direction of transmission on preceding 8 clocks; Judge whether to continue the transmission byte; If if notice zero clearing unit 207 is not; Notify the 4th judging unit 209, the four judging units 209 to be used to judge whether to receive I
2The C end signal.
Wherein, In the time of can specifically judging on the SCL bus that receives the 9th rising edge in the 3rd judging unit 208; The value of the signal on the bus of SDA on the direction in the opposite direction of transmission on preceding 8 clocks is 1; Still 0, if 1 is notified the 4th judging unit 209, if be 0 then for continuing the transmission byte; The 209 concrete execution of the 4th judging unit are judged: judge in the time of presetting, whether to receive I
2The C end signal is if receive operation; If in the time of presetting, do not receive I
2C end signal, also end operation.
It will be appreciated that above explanation all is that in fact, the sequential of the clock signal of transmitting on the SCL bus also can be regulated to the way of only regulating the sequential on the SDA bus.Then this PLD can also comprise the 3rd delay cell, is used for obtaining the direction that SCL goes up the signal of transmission according to first acquiring unit 202, with the clock signal delay time T ', the clock signal output after first transmitting element 41 will postpone.Usually T ' was less than time T and just can reaches sequential output preferably time delay.
Through above a kind of internal integrated circuit I that the embodiment of the invention is provided
2The explanation of C bus timing regulating device, this internal integrated circuit I
2C bus timing regulating device is according to SCL that receives and the signal on the SDA bus; Judge the transmission direction of signal on SCL and the SDA bus; Transmission direction according to signal on SCL that judges and the SDA bus; When the negative edge, T signal delay time that transmits on the SDA bus reduces I thereby reach with SCL
2The C bus realizes wrong purpose.This internal integrated circuit I
2C bus timing regulating device can be easy to arrive designing requirement the time T that will postpone, and the value of T regulates flexibly, only needing to change logical code just can the control lag time, and the scope of adjusting is bigger, need not revise hardware.
At last, need to prove a kind of internal integrated circuit I that the embodiment of the invention provides
2C bus timing regulating device can be a CPLD (CPLD; Complex Programmable Logic Device), perhaps can wipe formula PLD (EPLD off; Erasable Programmable Logic Device) etc., the pin that links to each other with the I2C bus can be that CPLD or EPLD go up any four pins.
Embodiment five
The embodiment of the invention provides a kind of communication system, and referring to shown in Figure 8, this communication system comprises: first equipment 81, second is provided with 85 and internal integrated circuit I
2C bus timing regulating device 83.
Wherein, first equipment 81 is used on serial clock SCL bus, sending signal and gives internal integrated circuit I
2C bus timing regulating device 83 and on serial data SDA bus, send signal and give programmable logic device 83;
Internal integrated circuit I
2C bus timing regulating device 83 is used to receive the signal that said first equipment 81 sends on serial clock SCL bus, the signal that on serial data SDA bus, sends according to signal on the said SCL bus that receives and the signal on the SDA bus, is judged I
2The direction of signal transmission on the C bus; When the signal on the SCL bus is in each negative edge; According to the said direction of judging,, send signal and the signal on the SCL bus behind T time delay on the SDA bus to second equipment 85 with T signal delay time on the SDA bus;
Internal integrated circuit I in this communication system
2C bus timing regulating device 83 can also be used for according to the direction of judging the T ' signal delay time on the SCL bus being sent to second equipment 85, time T ' less than said time T.
Understand this communication system for clearer, need to prove that also first equipment 81 and second equipment 85 are through I
2The C bus communicates, and internal integrated circuit I
2C bus timing regulating device 83 is at I
2On the C bus, be used to regulate I
2Sequential on the C bus guarantees that the signal of transmission between first equipment 81 and second equipment 85 is accurate.Therefore, first equipment 81 is used for through internal integrated circuit I
2The C bus timing regulating device 83 and second equipment 85 communicate.
Need to prove that also the programmable logic device 85 in the present embodiment can be the programmable logic device that provides among embodiment three or four.Specify can reference implementation the explanation of example three, four.
The I that transmits between first equipment and second equipment in this communication system
2The C bus signals is regulated I through programmable logic device
2The C bus timing has reduced I
2Sequential mistake on the C bus.Guaranteed I
2The signal transmission is efficient, accurate on the C bus.
One of ordinary skill in the art will appreciate that all or part of step in the whole bag of tricks of the foregoing description is to instruct relevant hardware to accomplish through program; This program can be stored in the computer-readable recording medium, and storage medium can comprise: ROM, RAM, disk or CD etc.
More than to a kind of I that the embodiment of the invention provided
2C bus timing control method, related device and system have carried out detailed introduction; Used concrete example among this paper principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that on embodiment and range of application, all can change, in sum, this description should not be construed as limitation of the present invention.
Claims (16)
1. internal integrated circuit I
2C bus timing control method is characterized in that, comprising:
Signal on the reception serial clock SCL bus and the signal on the serial data SDA bus;
According to signal on the said SCL bus that receives and the signal on the SDA bus, judge I
2The direction of signal transmission on the C bus;
When the signal on the SCL bus is in each negative edge, according to the said direction of judging, with T output signal delay time on the SDA bus;
According to the said direction of judging, the signal on the SCL bus is exported.
2. method according to claim 1 is characterized in that, and is said according to signal on the said SCL bus that receives and the signal on the SDA bus, judges I
2The direction of signal transmission on the C bus comprises:
Judge whether to receive I
2The C commencing signal, if, according to the I that receives
2The C commencing signal obtains the direction of the signal that transmits on SCL and the SDA bus.
3. method according to claim 2 is characterized in that, and is said when the signal on the SCL bus is in each negative edge, and according to the said direction of judging, T output signal delay time with on the SDA bus comprises:
Clock number on the record SCL bus;
When the SCL bus is gone forward 8 negative edges, according to the direction of the signal that transmits on the said SDA bus of obtaining, with T output signal delay time on the SDA bus.
4. method according to claim 3 is characterized in that, said method also comprises:
On the SCL bus during the 9th negative edge, with signal delay time on the SDA bus behind the T, according to the transmission direction output opposite with the signal of preceding 8 negative edges transmission.
5. according to claim 3 or 4 described methods, it is characterized in that said method also comprises:
Signal value on the SDA bus that receives during according to the 8th rising edge, the transmission direction of obtaining next byte, SDA has transmitted a byte in said preceding 8 clock period;
When the clock number on the SCL bus of record is 9, with the clock number zero clearing on the SCL bus of said record;
Write down the clock number on the SCL bus once more;
Said when writing down preceding 8 negative edges of clock number purpose on the SCL bus once more, according to said transmission direction of obtaining next byte, with T output signal delay time on the SDA bus.
6. method according to claim 5 is characterized in that, said method also comprises:
When said the 9th negative edge of clock number purpose that writes down once more on the SCL bus, with signal delay time on the SDA bus behind the T, according to the transmission direction output opposite with the signal of preceding 8 clock period transmission.
7. method according to claim 1 is characterized in that, and is said according to the said direction of judging, and with the output of the signal on the SCL bus, comprising:
According to the said direction of judging, with T ' output signal delay time on the SCL bus, said time T ' less than said time T.
8. internal integrated circuit I
2C bus timing regulating device is characterized in that, comprising:
Receiving element is used to receive signal and the signal on the serial data SDA bus on the serial clock SCL bus;
Judging unit is used for according to signal on the said SCL bus that receives and the signal on the SDA bus, judges I
2The direction of signal transmission on the C bus;
Delay cell is used for when the signal on the SCL bus is in each negative edge, according to the said direction of judging, with T signal delay time on the SDA bus;
Transmitting element is used for the direction judged according to said, with signal and the output of the signal on the SCL bus behind the time delay T on the SDA bus.
9. want 8 described devices according to right, it is characterized in that, said judging unit comprises:
First judging unit is used to judge whether to receive I
2The C commencing signal is if notify first acquiring unit;
First acquiring unit is used for according to the I that receives
2The C commencing signal obtains the direction of the signal that transmits on SCL and the SDA bus;
The recording clock unit is used to write down the clock number on the SCL bus, and said delay cell is according to the clock number of said record, and the direction of the signal that transmits on the SDA bus of obtaining according to said first acquiring unit is with T signal delay time on the SDA bus.
10. device according to claim 9 is characterized in that, said delay cell comprises:
First delay cell is used for the clock number according to said recording clock unit record, when the SCL bus is gone forward 8 negative edges, according to the direction of the signal that transmits on the said SDA bus of obtaining, with T output signal delay time on the SDA bus.
11. device according to claim 10 is characterized in that, said delay cell also comprises:
Second delay cell, when being used on the SCL bus the 9th negative edge, with T output signal delay time on the SDA bus, the transmission direction of said signal with the side signal transmission of preceding 8 negative edges transmission on the contrary.
12. device according to claim 11 is characterized in that, said judging unit also comprises:
The zero clearing unit is used for when the clock number on the SCL bus of record is 9, with the clock number zero clearing on the SCL bus of said record;
Said recording clock unit writes down the clock number on the SCL bus once more after said zero clearing unit is with the clock number zero clearing on the SCL bus of record.
13. device according to claim 12 is characterized in that, said judging unit also comprises:
Second judging unit is used for judging according to the clock number of said recording clock unit record whether the rising edge of SCL is the 8th rising edge;
Second acquisition unit, be used for when second judgment unit judges be as a result the time, obtain the value that SDA goes up the signal of transmission;
The 3rd acquiring unit, when being used for according to said the 8th rising edge, the signal value on the SDA bus that gets access to, the transmission direction of obtaining next byte, SDA has transmitted a byte in said preceding 8 clock period;
Said first delay cell also is used for said when writing down preceding 8 negative edges of clock number purpose on the SCL bus once more, according to said transmission direction of obtaining next byte, with T output signal delay time on the SDA bus.
14. device according to claim 13; It is characterized in that; Said second delay cell; Also be used for when said the 9th negative edge of clock number purpose that writes down once more on the SCL bus, with T output signal delay time on the SDA bus, the transmission direction of signal is opposite when the transmission direction of the signal on the said SDA bus and preceding 8 clock period.
15. a communication system is characterized in that, comprising:
First equipment is used on serial clock SCL bus, sending signal, on serial data SDA bus, sends signal;
Internal integrated circuit I
2C bus timing regulating device is used to receive the signal that said first equipment sends on serial clock SCL bus, the signal that on serial data SDA bus, sends according to signal on the said SCL bus that receives and the signal on the SDA bus, is judged I
2The direction of signal transmission on the C bus; When the signal on the SCL bus is in each negative edge; According to the said direction of judging,, send signal and the signal on the SCL bus behind T time delay on the SDA bus to second equipment with T signal delay time on the SDA bus;
Second equipment is used to receive said internal integrated circuit I
2Signal on the SDA bus that C bus timing regulating device is sent behind the time delay T and the signal on the SCL bus.
16. communication system according to claim 15 is characterized in that, said internal integrated circuit I
2C bus timing regulating device also is used for the direction judged according to said, the T ' signal delay time on the SCL bus is sent to second equipment, said time T ' less than said time T.
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| CN2009100003901A CN101770443B (en) | 2009-01-07 | 2009-01-07 | Time sequence adjusting method for internal IC (integrated circuit) bus, corresponding device and system thereof |
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| CN2009100003901A CN101770443B (en) | 2009-01-07 | 2009-01-07 | Time sequence adjusting method for internal IC (integrated circuit) bus, corresponding device and system thereof |
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| CN101770443B true CN101770443B (en) | 2012-05-23 |
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| CN110297794B (en) * | 2018-03-23 | 2022-08-12 | 富联精密电子(天津)有限公司 | Data communication system and method |
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| CN111027108B (en) * | 2019-08-13 | 2024-02-13 | 安天科技集团股份有限公司 | Sequential logic safety detection method and device for low-speed synchronous serial bus |
| CN111459868B (en) * | 2020-03-31 | 2021-05-18 | 北京润科通用技术有限公司 | Bit identification method, device and system of I2C bus and electronic equipment |
| CN117215983B (en) * | 2023-11-09 | 2024-03-22 | 辉芒微电子(深圳)股份有限公司 | Circuit structure and method for avoiding error starting and stopping conditions of I2C interface |
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