CN1188281A - Serial input/output circuit and serial bus interface circuit - Google Patents
Serial input/output circuit and serial bus interface circuit Download PDFInfo
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- CN1188281A CN1188281A CN97116197A CN97116197A CN1188281A CN 1188281 A CN1188281 A CN 1188281A CN 97116197 A CN97116197 A CN 97116197A CN 97116197 A CN97116197 A CN 97116197A CN 1188281 A CN1188281 A CN 1188281A
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Abstract
The invention intends to prevent a wrong stop condition from being generated at the time of switching from a port input/output circuit to the serial I/O circuit, when an I2 C-bus system is actualized in combination with the port input/output circuit. An initial value setting circuit 30 is added which is provided with a data terminal D for inputting data for setting an initial value and outputs the data inputted from the data terminal D to an output terminal OUT where transmit data to SDA is outputted when the serial I/O circuit 13 is placed in an operation inhibited state or transmit data outputted from the serial I/O circuit 13 to the SDA from the data terminal D when the circuit is placed in an operation allowed state.
Description
The present invention relates to be implemented in device and I such as central processing unit with the port imput output circuit
2Carry out the serial input/output circuit (after, abbreviate serial i/O circuit as) and the serial bus interface circuit of the serial bus interface circuit of interface between the universal serial bus such as C bus.
Serial i/O circuit application is in realizing I
2The C bus interface circuit.This I
2The C bus is the bidirectional linked list bus line of the two-wire system advocated of PHILIPS Co., by clock line (after, abbreviate SCL as) and data circuit (after, abbreviate SDA as) formation.A plurality of devices and I such as microcontroller, LCD (LCD) driver, gate array, ADC (analog digital converter), static RAM (SRAM) or EEPROM
2The C bus connects, and wherein, leading device carries out the transmission of data after specifying the address of the device of wanting the subordinate of visiting.
Below, I is described simply
2The specification of C bus.With I
2The device that the C bus connects, the two all must have open drain for SDA and SCL, and in addition, SDA and SCL are by moving a certain positive voltage on the pull-up resistor to.Like this, at I
2The SDA of C bus, SCL and and I
2Each I that the C bus connects
2Between the C bus interface circuit, setting wired AND and connecting.No matter any device does not use I
2During the C bus, SCL and SDA are in high level state.During data transmission,, just do not allow the state of SDA to change, only when SCL is low level state, just allow the state of SDA to change if SCL is in high level state.But this rule has 2 exceptions, and one is the generation of initial conditions, and another is the generation of stop condition.When SCL remained high level state, initial conditions were back along starting by SDA's, and when SCL remained high level, stop condition was by the forward position starting of SDA.
In addition, utilize I
2The data of C bus transfer are made of 8 (1 bytes), in additional affirmation position, the end of each byte.When receiving end normally receives 1 byte data and receive the 9th time clock of SCL behind the 1st of reception data, confirmation signal is returned by making SDA become low level.1 transmission byte number that can transmit without limits, how many bytes can be transmitted.Use I
2The 1st byte of C bus original transmission is 7 subordinate address, and its least significant bit (LSB) is the direction position of the direction of expression data.That is, the direction position is 0 o'clock, and the leading device of expression writes the subordinate device with data, and the direction position is 1 o'clock, and the leading device of expression reads in data from the subordinate device.
Fig. 6 a, 6b represent to pass through I
2The example of the data transmission of C bus.This is the example that after the 1st byte of the subordinate address of expression indicating target subordinate device the data of another byte is transmitted to the subordinate device, and Fig. 6 a represents the waveform on the scl line road, and Fig. 6 b represents the waveform on the sda line road.
Leading device control I
2Data transmission on the C bus.Therefore, leading device provides time clock to the subordinate device, simultaneously, shown in Fig. 6 a and Fig. 6 b, produces initial conditions and stop condition.In addition, because I
2The C bus system is the system of the leading device of multichannel, so a plurality of sometimes leading devices think to begin simultaneously to carry out the transmission of data.Confusion for fear of has at this moment adopted arbitration.The two all carries out arbitration to SDA and SCL.Here, though do not specify the discriminant approach of arbitration, because very complicated, so, I used usually
2The specialized hardware of C bus.But if carry out the processing power height of the central arithmetic processing apparatus (after, abbreviate CPU as) of system control, CPU also can control the I/O port and arbitrate.
Fig. 7 is expression and I
2The C bus connects have earlier comprise I
2The block diagram of the structure of the device of C bus interface circuit.In illustrated device, suppose processing power height, the CPU control I/O port of CPU and the processing that realizes arbitrating.Among the figure, the 1st, have the serial i that has earlier/O circuit of clock terminal CLK, input terminal IN and lead-out terminal OUT, the 2nd, the CPU that carries out the control of this entire device, the 3rd, the data bus that their are connected.
The 4th, have and be connected in I
2The input buffer of the input end that the SCL terminal of the SCL of C bus connects, the 5th, have the output buffer of the output terminal that is connected with the SCL terminal, the 6th, be used for selecting 1 also with selected 1 selector switch to the input end transmission of output buffer 5 from 2 inputs, the 7th, storage is by the output latch of the output signal value of SCL terminal output, and the 8th, the switch that the output of 1 in 2 inputs of the clock terminal CLK of serial i/O circuit 1 and selector switch 6 or input buffer 4 is connected.The 9th, have and be connected in I
2The input buffer of the input end that the SDA terminal of the SDA of C bus connects, the 10th, have the output buffer of the output terminal that is connected with the SDA terminal, the 11st, be used for selecting 1 also with selected 1 selector switch to the input end transmission of output buffer 10 from 2 inputs, the 12nd, storage is by the output latch of the output signal value of SDA terminal output.
Fig. 8 is the block diagram of the inner structure of expression above-mentioned serial i/O circuit 1.Among the figure, the 20th, the clock circuit of time clock takes place, the 21st, carry out the switch of clock selecting when the internal clocking pattern and during the external clock pattern.The 22nd, export tranmitting data register signal, transmission end interrupt request signal, transmission data write signal etc. and the sending controling circuit of control data transmission, the 23rd, will be when the internal clocking pattern from the output buffer of the tranmitting data register signal that sends control circuit 22 to clock terminal CLK output, the 24th, output receive clock signal, receive the end interrupt request signal, receive data write signal etc. and reception control circuit that control data receives.The 25th, will be transformed to the reception shift register of parallel data from the reception data of input terminal IN input from serial data, the 26th, the reception data write signal of response reception control circuit 24 and read in the reception buffer register of the content that receives shift register 25.The 27th, storage sends the transmission buffer register of data, and the 28th, the control register of the value of the pattern of setting decision serial i/O circuit 1.
Fig. 9 a～9d is the sequential chart that is used to illustrate the action of serial i shown in Figure 8/O circuit 1, Fig. 9 a represents the output waveform of clock generating circuit 20, Fig. 9 b represents from the waveform of the tranmitting data register signal of sending controling circuit 22 outputs, Fig. 9 c represents that from the waveform of the transmission data of lead-out terminal OUT output, Fig. 9 d represents the waveform of the transmission data write signal that sending controling circuit 22 takes place.
Below, explanation earlier sends action with reference to Fig. 9 a～9d.CPU2 sets data designated by data bus 3 in control register 29, carry out the setting of pattern of the serial i/O circuit 1 of internal clocking pattern/external clock pattern etc.Now, for example the setting of internal clocking pattern is carried out in supposition.When in control register 29, setting the data of specifying the internal clocking pattern, switch 21 is switched to clock generating circuit 20 1 sides, output buffer 23 conductings.Therefore, the clock signal shown in Fig. 9 a of clock generating circuit 20 generations is just imported sending controling circuit 22.In addition, CPU2 carries out by the setting of data bus 3 to the data that send buffer register 27 transmissions, like this, just indicates by the value of setting appointment in control register 29 and sends beginning.
When setting the value of indicating the appointment that sends beginning in control register 29, sending controling circuit 22 is just to sending tranmitting data register signal shown in the shift register 28 output map 9b and the transmission data write signal shown in Fig. 9 d.When taking place to send the data write signal, the data that send buffer register 27 storages are just transferred in the transmission shift register 28, send shift register 28 shown in Fig. 9 c, and these data and tranmitting data register signal Synchronization ground are transmitted by turn.At this moment, the state of the lead-out terminal OUT before the initial D0 data is that the output initial value of lead-out terminal OUT is fixed as high level or low level (in illustrated example, being fixed as high level).If send total data (at this moment, the being assumed to 9) end of output of shift register 28, just then the end interrupt request signal takes place to send sending controling circuit 22.From the tranmitting data register signal of clock terminal CLK by 22 generations of output buffer 23 output sending controling circuits.
On the other hand, when setting the data of designated external clock module in control register 29, switch 21 is switched to clock terminal CLK one side, output buffer 23 becomes cut-off state.Therefore, the clock signal from serial i/O circuit outside that is input on the clock terminal CLK is just imported sending controling circuit 22, and the tranmitting data register signal that sending controling circuit 22 generates is not exported from clock terminal CLK.Identical during in addition, with the internal clocking pattern.
Below, illustrate to receive action.Suppose that CPU2 has carried out the setting of internal clocking pattern by set data designated in control register 29.Like this, the CPU2 value of just setting appointment in control register 29 is indicated and is received beginning.When having indicated the reception beginning, the clock signal output tranmitting data register signal that sending controling circuit 22 just generates according to clock generating circuit 20.The receive clock signal takes place in the reception control circuit 24 that receives this tranmitting data register signal, and it is exported to receiving shift register 25.Receive shift register 25 and receive the data that arrive input terminal IN with this receive clock signal Synchronization ground bit by bit.When receiving 9 data, reception control circuit 24 just will receive the data write signal to receiving buffer register 26 outputs.Be transplanted in the reception buffer register 26 by the sequential of the data that receive shift register 25 receptions by this reception data write signal.In addition, when the data of receiving 9, the end interrupt request signal just takes place to receive in reception control circuit 24.
On the other hand, when in control register 29, setting the external clock pattern, because output buffer 23 becomes cut-off state, so, the tranmitting data register signal that sending controling circuit 22 generates is not from clock terminal CLK output, and the clock signal of clock terminal CLK input sending controling circuit 22.Identical during in addition, with the internal clocking pattern.
Below, illustrate and I shown in Figure 7
2The action of the device that the C bus connects.At I
2After in the C bus initial conditions taking place, transmission subordinate address is transmitted data then during beginning.Consider to use device shown in Figure 7, and with its situation of moving as leading device.Figure 10 a, 10b are this device sequential charts when moving as leading device, in Figure 10 a I have been shown
2The waveform of the SCL of C bus has illustrated the waveform of SDA in Figure 10 b.
When SCL is high level state, if SDA descends, initial conditions just take place.From take place initial conditions to the subordinate address is sent to SDA during, CPU2 controls SCL terminal and SDA terminal as port I/O circuit.This is because this control of being undertaken by CPU2 is to handle to arbitrate the complexity of 1 device in the authority imparting system of the leading device of construction system needed.When the transmission of having passed through arbitration and subordinate address finishes, CPU2 when the SCL terminal is high level for example in Figure 10 the moment shown in the with dashed lines selector switch 6, selector switch 11, switch 8 are set at the state of appointment, two terminals of SCL, SDA are switched to serial i/O circuit from port I/O circuit.That is, two terminals of SCL, SDA begin action as the terminal of serial i/O circuit 1.Then, CPU2 can carry out the transmission of data by controlling serial i/O circuit 1 as described above.Like this, if when sending the subordinate address, passed through arbitration, then leading device just is himself, later data transmission has been handled with regard to not needing to arbitrate, so, CPU2 can handle SCL terminal and SDA terminal as the terminal of serial i/O circuit, desirable data are sent on the SDA.
When port I/O circuit switched to serial i/O circuit, the original state of the lead-out terminal OUT of serial i/O circuit 1 was that the output initial value of lead-out terminal must be high level or low level fixed value with SCL terminal and SDA terminal.Here, when the subordinate device had been confirmed from the address of leading device output, just the affirmation signal with low level state was transferred on the SDA, so SDA is converted to low level state or keeps low level state.Therefore, though the initial value of the lead-out terminal OUT of serial i/O circuit 1 be high level or low level can.Because the SDA terminal is the terminal with wired AND characteristic, so, if the SDA terminal is set at low level state, then necessarily become low level state in subordinate device one side.
Below, be considered as the subordinate device and the situation of moving.
Figure 11 a, 11b are device shown in Figure 7 sequential charts when moving as the subordinate device, and Figure 11 a shows I
2The waveform of the clock signal on the SCL of C bus, Figure 11 b shows the signal waveform on the SDA.
The same when moving with the leading device of conduct, from the reception that detects the subordinate address of initial conditions, CPU2 controls two terminals of SCL, SDA as the terminal of port I/O circuit.On the other hand, after receiving the subordinate address and returning confirmation signal, be about to low level write output latch 12, with low level after the output of SDA terminal, CPU2 when the SCL terminal is high level for example in Figure 11 the moment shown in the with dashed lines and SCL terminal and SDA terminal are switched to serial i/O circuit from port I/O circuit by selector switch 6, selector switch 11, switch 8 are set at the state of appointment.Then, CPU2 carries out the transmission of data by controlling serial i/O circuit 1 as described above.
Here, when port I/O circuit switched to serial i/O circuit, the original state of the lead-out terminal OUT of serial i/O circuit 1 was that the output initial value of lead-out terminal OUT is high level or low level fixed value with SCL terminal and SDA terminal.Now, the output initial value of supposing lead-out terminal OUT is that high level is a logical one.At this moment, shown in Figure 11 b, two terminals of SCL, SDA are being switched to moment of serial i/O circuit from port I/O circuit, the SDA terminal just is changed to high level from low level.At this moment, because the SCL terminal is a high level shown in Figure 11 a, so stop condition just takes place in this variation.Originally, although do not wish to take place stop condition here, because stop condition has taken place, so, I
2The C bus system just can not set up.
Publish the document of the technology of this relevant serial i/O circuit that has earlier, for example having, the spy opens flat 5-181796 communique etc.
Because the serial i/O circuit that has earlier constitutes in a manner described, so, realize I if want with port I/O combination of circuits
2During the C bus interface circuit, under a certain condition,, make I thereby pseudo-stop condition takes place mistakenly in existence in the moment that switches to serial i/O circuit from port I/O circuit
2The problem that the C bus system can not set up.
The present invention is motion in order to address the above problem, and purpose is to realize I with port I/O combination of circuits
2Thereby the C bus interface circuit obtains can not take place mistakenly in the moment that switches to serial i/O circuit from port I/O circuit the serial i/O circuit and the I with this serial i/O circuit of stop condition
2The C bus interface circuit.
The serial i of the present invention the 1st aspect/O circuit is characterised in that: have data that receive to supply with, this serial i/O circuit become can move before the output initial value of its lead-out terminal be set at the data terminal of the value of above-mentioned data; This serial i/O circuit remain the action illegal state during receive to supply with the data of above-mentioned data terminal and these data exported to above-mentioned lead-out terminal, switch to action at this serial i/O circuit from the action illegal state and the output of above-mentioned lead-out terminal remained during License Status state by above-mentioned initial value decision, this serial i/O circuit remain the action License Status during receive data that serial supplies with and these data outputed to initial value setting device on the above-mentioned data circuit by above-mentioned lead-out terminal serial; When the internal clocking pattern, generate and send clock signal, externally receive the clock signal of supplying with above-mentioned clock terminal and the clock apparatus that sends this clock signal during clock module; Respond the clock signal of above-mentioned clock apparatus and temporary transient storage should send on the above-mentioned data circuit data and with the dispensing device of this data serial ground to above-mentioned initial value setting device transmission; Respond the clock signal of above-mentioned clock apparatus and the receiving trap of the data that temporary transient storage receives by above-mentioned input terminal and write and this serial i/O circuit is become to move or the control register of the data of prohibited acts.
The serial i of the present invention the 2nd aspect/O circuit is characterised in that: the clock generating circuit that clock signal takes place when above-mentioned clock apparatus is included in inner clock module with is connected with above-mentioned clock generating circuit select the clock signal of above-mentioned clock generating circuit when the internal clocking pattern, externally select the clock signal of above-mentioned clock terminal and the switch that selected clock signal is exported to above-mentioned dispensing device during clock module; Above-mentioned dispensing device comprises the clock signal that responds above-mentioned switch and the transmission buffer register of the data that the sending controling circuit that generates the tranmitting data register signal, temporary transient storage are supplied with and from above-mentioned transmission buffer register reading of data and the transmission shift register that these data transmitted to above-mentioned initial value setting device bit by bit with the tranmitting data register signal Synchronization ground of above-mentioned sending controling circuit; Above-mentioned receiving trap comprise the tranmitting data register signal that responds above-mentioned sending controling circuit and generate the reception shift register of the sending controling circuit, reception of receive clock signal and data that above-mentioned input terminal is supplied with on above-mentioned receive clock signal Synchronization ground by turn and temporary transient these data of storage and when all of above-mentioned data store in the above-mentioned reception shift register from the reception buffer register of above-mentioned reception shift register reading of data.
The serial i of the present invention the 3rd aspect/O circuit is characterised in that: as the data that initial value is set that are used for that are input to data terminal, and the data level of the SDA of this serial bus system when the clock of the SCL of use bidirectional series bus system changes.
The serial i of the present invention the 4th aspect/O circuit is characterised in that: as the data that initial value is set that are used for that are input to data terminal, output to the data on the SDA of bidirectional series bus system when using this serial i/O circuit for the action illegal state.
The serial interface circuit of the present invention the 5th aspect is characterised in that: comprise have data that receive to supply with, this serial i/O circuit become can move before the output initial value of its lead-out terminal be set at the data terminal of the value of above-mentioned data; This serial i/O circuit remain the action illegal state during receive to supply with the data of above-mentioned data terminal and these data exported to above-mentioned lead-out terminal, switch to action at this serial i/O circuit from the action illegal state and the output of above-mentioned lead-out terminal remained during License Status state by above-mentioned initial value decision, this serial i/O circuit remain the action License Status during receive data that serial supplies with and these data outputed to initial value setting device on the above-mentioned data circuit by above-mentioned lead-out terminal serial; When the internal clocking pattern, generate and send clock signal, externally receive the clock signal of supplying with above-mentioned clock terminal and the clock apparatus that sends this clock signal during clock module; Respond the clock signal of above-mentioned clock apparatus and temporarily store data that send on the above-mentioned data circuit and the dispensing device that this data serial ground is sent to above-mentioned initial value setting device; Respond the clock signal of above-mentioned clock apparatus and the receiving trap of the data that temporary transient storage receives by above-mentioned input terminal and write and this serial i/O circuit is become to move or the serial i/O circuit of the control register of the data of prohibited acts; And receive data on the above-mentioned data circuit and the clock signal on the above-mentioned clock line during for prohibited acts or data transmission is transferred to clock signal to the above-mentioned data circuit port I/O circuit on the clock line when serial i/O circuit.
The serial interface circuit of the present invention the 6th aspect is characterised in that: the clock generating circuit that clock signal takes place when the above-mentioned clock apparatus of serial i/O circuit is included in inner clock module with is connected with above-mentioned clock generating circuit select the clock signal of above-mentioned clock generating circuit when the internal clocking pattern, externally select the clock signal of above-mentioned clock terminal and the switch that selected clock signal is exported to above-mentioned dispensing device during clock module; Above-mentioned dispensing device comprise the clock signal that responds above-mentioned switch and the transmission buffer register of the data that the sending controling circuit that generates the tranmitting data register signal, temporary transient storage are supplied with, from above-mentioned transmission buffer register reading of data and the transmission shift register that these data transmitted to above-mentioned initial value setting device bit by bit with the tranmitting data register signal Synchronization ground of above-mentioned sending controling circuit; Above-mentioned receiving trap comprise the tranmitting data register signal that responds above-mentioned sending controling circuit and generate the reception shift register of the sending controling circuit, reception of receive clock signal and data that above-mentioned input terminal is supplied with on above-mentioned receive clock signal Synchronization ground by turn and temporary transient these data of storage and when all of above-mentioned data store in the above-mentioned reception shift register from the reception buffer register of above-mentioned reception shift register reading of data.
The serial interface circuit of the present invention the 7th aspect is characterised in that: above-mentioned port I/O circuit have in each pulse front edge of the clock signal of the clock line of above-mentioned universal serial bus or back along the time latch the latch cicuit of the data on the data circuit of above-mentioned universal serial bus, when above-mentioned serial i/O circuit remains the action illegal state, above-mentioned latch cicuit is with the data terminal output of latched data to above-mentioned serial i/O circuit, and the output initial value of above-mentioned lead-out terminal is set at above-mentioned latched data value.
The serial interface circuit of the present invention the 8th aspect is characterised in that: when above-mentioned serial i/O circuit remains the action illegal state, the data that outputed on the above-mentioned data circuit by above-mentioned serial interface circuit are input on the above-mentioned data terminal of above-mentioned serial i/O circuit, and the output initial value of above-mentioned lead-out terminal is set at the value of above-mentioned data.
Fig. 1 is the block diagram of the serial i/O circuit of the expression embodiment of the invention 1.
Fig. 2 is the I that expression comprises the serial i/O circuit that uses the embodiment of the invention 1
2The block diagram of the device of C bus interface circuit.
Fig. 3 is the sequential chart of the action of the serial i/O circuit that is used to illustrate the embodiment of the invention 1 and device.
Fig. 4 is the I that expression comprises the embodiment of the invention 2
2The block diagram of the device of C bus interface circuit.
Fig. 5 is the sequential chart of the action of the serial i/O circuit that is used to illustrate the embodiment of the invention 2 and device.
Fig. 6 is used to illustrate I
2The sequential chart of the action of C bus.
Fig. 7 is the I that expression comprises serial i/O circuit that use has earlier
2The block diagram of the device of C bus interface circuit.
Fig. 8 is a block diagram of representing serial i/O circuit of having earlier.
Fig. 9 is the sequential chart that is used to illustrate the action of the serial i/O circuit that has earlier.
Figure 10 is the sequential chart of the action when being used for illustrating the leading device of the device that has earlier.
Figure 11 is the sequential chart of the action when being used for illustrating the subordinate device of the device that has earlier.
Below, embodiments of the invention are described.
Embodiment 1.
Fig. 1 is the block diagram of inner structure of the serial i/O circuit of the expression embodiment of the invention 1.This serial i/O circuit also has the data terminal D of the data of importing the output initial value setting that is used for lead-out terminal OUT except input terminal IN, the lead-out terminal OUT that serial i/the O circuit is had and clock terminal CLK that have earlier.
Among the figure, the 20th, the clock generating circuit of clock signal takes place, the 21st, the switch of the clock signal that the clock signal that takes place when this clock generating circuit 20 of this serial i/select when the O circuit is the internal clocking pattern and externally selecting during clock module is imported from clock terminal CLK.The 22nd, thus the clock signal that input is selected by this switch and export the tranmitting data register signal, send the sending controling circuit that finishes to require look-at-me and send the transmission of control datas such as data write signal, the 23rd, the tranmitting data register signal that will send from this sending controling circuit 22 when the internal clocking pattern is to the output buffer of clock terminal CLK output.
The 24th, thus input is exported the receive clock signal from the tranmitting data register signal of sending controling circuit 22 output, receives the end interrupt request signal and is received the reception control circuit of the reception of control datas such as data write signal.The 25th, the reception data from input terminal IN input are transformed to the reception shift register of parallel data from serial data, according to the sequential of the receive clock signal of exporting from reception control circuit 24, the reception data that one side will arrive input terminal IN are shifted bit by bit, one side receives and storage.The 26th, receive buffer register, when receiving shift register 25 and be through with the reception of data, just response is read in the reception data that receive shift register 25 storages from the reception data write signal of reception control circuit 24 outputs.This reception buffer register 26 is connected with data bus 3, though Fig. 1 is not shown, and, the CPU (referring to Fig. 2) that is connected with data bus 3 can read this content.
The 27th, storage sends the transmission buffer register of data, is connected with data bus 3, and CPU can be by data bus 3 with data transmission and write this transmission buffer register 27.The 28th, will send data are transformed to serial data from parallel data transmission shift register, according to transmission data write signal from sending controling circuit 22 outputs, read in the transmission data that send buffer register 27 storages, with the tranmitting data register signal Synchronization ground of sending controling circuit 22 outputs with its input terminal in transmission of described rearwards initial value initialization circuit 30 bit by bit.The 29th, set the data that the pattern of indication this serial i/O circuit and transmitting-receiving begin etc. or the control register of numerical value, switch 21, sending controling circuit 22, output buffer 23, reception control circuit 24 etc. move according to this setting content.This control register 29 is connected with data bus 3, and CPU writes this register with data or numerical value.
Each part mentioned above be with the get the bid suitable part of each several part of the serial i that has earlier/O circuit of same-sign of Fig. 8.
Initial value initialization circuit 30 can be set from the output initial value of the lead-out terminal OUT output of serial i/O circuit, is the key component of serial i of the present invention/O circuit.This initial value initialization circuit 30 has and sends the input terminal in that shift register 28 is connected, the lead-out terminal out that is connected with the lead-out terminal OUT of this serial i/O circuit, the clock terminal clk of the tranmitting data register signal of input sending controling circuit 22, the data terminal d that the setting terminal s that is connected with control register 29 is connected with the data terminal D with serial i/O circuit, when setting terminal s permission action the value of data terminal d is exported from lead-out terminal out as the output initial value of serial i/O circuit, according to the sequential that is input to the tranmitting data register signal on the clock terminal clk, be input to the output of the transmission shift register 28 on the input terminal in from lead-out terminal out when setting terminal s prohibited acts.Here, suppose that setting terminal s is set by control register 29, when the action of O circuit disables (serial i/) is not set at and allows action when not using this serial i/O circuit, and (when serial i/O circuit allows action) is set at prohibited acts when using serial i/O circuit.
Fig. 2 is that expression comprises the serial i/O circuit of the embodiment 1 that has shown in Fig. 1 and the I of port I/O circuit
2The block diagram of the structure of the device of C bus interface circuit.In this device, also the same with situation about having earlier, suppose that the processing power height of CPU, CPU can control the processing of arbitrating of I/O port.
As shown in Figure 2, having the serial i of the present embodiment 1 of structure shown in Figure 1/O circuit 13 is connected with CPU2 by data bus 3.
In Fig. 2, the 4th, have and be connected in I
2The input buffer of the input terminal that the SCL terminal of the SCL of C connects, its value outputs on the data bus 3 when reading.The 5th, have the output buffer of the lead-out terminal that is connected with the SCL terminal, the 6th, select described from behind output latch 7 or switch 8 to obtain the selector switch of the input of this output buffer 5.The 7th, the above-mentioned output latch of the output valve of storage SCL terminal, the output valve of its SCL terminal is write by CPU2 by data bus 3.The 8th, the connecting object of the clock terminal CLK of serial i/O circuit 13 is chosen as the above-mentioned switch of input buffer 4 or selector switch 6, at serial i/when O circuit 13 is the internal clocking pattern it is connected with 1 input terminal of selector switch 6, externally its lead-out terminal with input buffer 4 is connected during clock module.
The 9th, have and be connected in I
2The input buffer of the input terminal that the SDA terminal of the SDA of C bus connects, its value outputs on the data bus 3 when reading, and simultaneously, also is input on the input terminal IN of serial i/O circuit 13.The 10th, have the output buffer of the lead-out terminal that is connected with the SDA terminal, the 11st, select described from behind output latch 12 or the serial i/lead-out terminal OUT of O circuit 13 to obtain the selector switch of the input of this output buffer 10.The 12nd, storage is to the output latch of the output valve of SDA terminal output, and the output valve of exporting to this SDA terminal is write by data bus 3 by CPU2.
Each part mentioned above except serial i/O circuit 13 is and the get the bid suitable part of each several part of the device that has earlier of same-sign of Fig. 7.
In addition, the 14th, and serial i/O circuit 13 becomes the latch cicuit of the main points of embodiment 1 together, in the forward position of the time clock of importing from the SCL terminal, latch the data (i.e. 1 bit data) that are input on the SDA terminal, and these data are outputed on the data terminal D of serial i/O circuit 13.In addition, port I/O circuit comprises input buffer 4,9, output buffer 5,10, selector switch 6,11, switch 8, output latch 7,12 and latch cicuit 14.
Below, its action is described.
Fig. 3 a～3e is used to illustrate the I with the serial i/O circuit that comprises the embodiment of the invention 1
2The sequential chart of the action of the device of C bus interface circuit, Fig. 3 a represents the waveform of the SCL terminal of device shown in Figure 2, Fig. 3 b represents the waveform of the SDA terminal of this device, Fig. 3 c represents the waveform of the setting terminal s of initial value initialization circuit 30 shown in Figure 1, Fig. 3 d represents the waveform of the data terminal d of this initial value initialization circuit 30, and Fig. 3 e represents the waveform of the lead-out terminal out of this initial value initialization circuit 30.
With I
2The I that the C bus connects
2The C bus interface circuit has open drain output to SDA and SCL, because SDA, SCL draw on being undertaken by pull-up resistor, so SDA and SCL are setting the wired AND door.Do not use this I
2During the C bus, SCL and SDA become high level, if SDA descends when SCL is high level, initial conditions just take place, if SDA rises when SCL is high level, stop condition just take place.At such I
2In the C bus, after the generation initial conditions, begin to transmit the subordinate address, transmit data then.
At first, the situation that device moves as leading device is described.If SDA descends when SCL is high level, initial conditions just take place.SCL terminal and SDA terminal are controlled as the terminal of port I/O circuit by CPU2 to sending the subordinate address from taking place after the initial conditions to SDA.For to I
21 device of C bus system is used to give the complexity arbitration processing of the authority that constitutes leading device, needs such control that utilizes CPU2 to carry out.Arbitration handle with the serial i that has earlier
2The mode that the C bus system is the same is carried out.
After device generation initial conditions, CPU2 passes through I
2The SDA terminal of C bus interface circuit is sent to I with the subordinate address
2On the SDA of C bus.In the forward position that is added to each time clock on the SCL terminal shown in Fig. 3 a, the data that are input on the SDA terminal shown in Fig. 3 b are that the every of subordinate address is latched by latch cicuit 14.The output of this latch cicuit 14, the data terminal D by serial i/O circuit 13 is input on the data terminal d of its initial value initialization circuit 30.The data that are input on the data terminal d of this initial value initialization circuit 30 are shown in Fig. 3 d.Pass through I at device
2During the C bus transfer subordinate address, serial i/O circuit 13 is set at the prohibited acts state by control register 29, and therefore, CPU2 controls SCL terminal and SDA terminal as port I/O circuit.At this moment, initial value initialization circuit 30 utilizes from the signal of the low level state shown in Fig. 3 c of its setting terminal of this control register 29 supplies s and keeps the permission operating state.
Initial value initialization circuit 30 becomes when allowing operating state, and the data that are input on this data terminal d are exported from lead-out terminal out.As mentioned above, be input on the SDA terminal and be input on the data terminal d by everybody the data terminal D by serial i/O circuit 13 of everybody subordinate address of latch cicuit 14 latched data when the forward position of each time clock of SCL terminal.Therefore, shown in Fig. 3 e, the output of latch cicuit 14 outputs on its lead-out terminal out, thereby all position orders of data output on the lead-out terminal OUT of serial i/O circuit 13.After device had passed through arbitration, during the affirmation signal of subordinate response device subordinate address output low level state, SDA became low level state.Like this, last, as among Fig. 3 by shown in the scope that ellipse surrounded, the state low level state of the SDA terminal when the forward position of the 9th of the time clock of SCL terminal just is set at the output initial value of the lead-out terminal OUT of serial i/O circuit 13.
When the subordinate device makes SDA become low level state after the transmission of having passed through arbitration and subordinate address finishes, CPU2 when the SCL terminal is high level for example in Fig. 3 the moment shown in the with dashed lines selector switch 6, selector switch 11, switch 8 are set at the state of appointment, two terminals of SCL, SDA are switched to serial i/O circuit on one side.Then, CPU2 carries out the transmission of data by control serial i/O circuit 13.Promptly, at this moment, because CPU2 controls SCL terminal and SDA terminal as serial i/O circuit, so, serial i/O circuit 13 is set at the permission operating state by control register 29, and initial value initialization circuit 30 becomes the prohibited acts state according to be input to the signal shown in Fig. 3 c that sets on the terminal s from control register 29.
When initial value initialization circuit 30 becomes the prohibited acts state, the data that are input on the input terminal in are exported from lead-out terminal out.Read in the transmission data that send shift register 28 from sending buffer register 27, sequential according to the tranmitting data register signal of sending controling circuit 22 output is input on this input terminal in serially, shown in Fig. 3 e, the output of this transmission shift register 28 outputs on the lead-out terminal OUT of serial i/O circuit 13 from the lead-out terminal out of initial value initialization circuit 30.Situation about having earlier is the same, the transmission of data is as having passed through arbitration when sending the subordinate address, then leading device just is himself, the processing and later data transmission does not need to arbitrate, so CPU2 can only control SCL terminal and SDA terminal and transmit desirable data by SDA as the terminal of serial i/O circuit.
In the moment shown in the with dashed lines in Fig. 3 a, 3b, SCL terminal and SDA terminal are switched to serial i/O circuit on one side from port I/O circuit.Before this, the data level of the SDA terminal when the output initial value of the lead-out terminal OUT of serial i/O circuit 13 is set at the forward position of the 9th of time clock of SCL terminal by initial value initialization circuit 30, so, thereby serial i/O circuit switches to action License Status I from the action illegal state
2The C bus interface circuit is as serial i/when the O circuit begins to move, initial value initialization circuit 30 is with the output of its lead-out terminal out thereby just the output of lead-out terminal OUT is remained low level state by above-mentioned initial value decision, shown in Fig. 3 b, the state of SDA terminal does not change.
Below, the situation that device moves as the subordinate device is described.The same when moving with the leading device of conduct, in the reception of the subordinate address of carrying out according to the detection of initial conditions, CPU2 controls two terminals of SCL, SDA as the terminal of port I/O circuit.On the other hand, after receiving the subordinate address and confirmation signal being returned, being about to low level writes output latch 12 and by the SDA terminal affirmation signal of low level state is outputed to after SDA goes up, CPU2 is by being set at selector switch 6, selector switch 11 and switch 8 state of appointment when the SCL terminal is high level, and SCL terminal and SDA terminal are switched to serial i/O circuit on one side from port I/O circuit.Then, CPU2 receives data or transmits data to leading device from leading device by control serial i/O circuit 13.
Here, SCL terminal and SDA terminal are switched to from port I/O circuit serial i/O circuit on one side before, the data level of the SDA terminal when initial value initialization circuit 30 is set at the initial value of the lead-out terminal OUT of serial i/O circuit 13 in the forward position of the 9th of time clock of SCL terminal, so, the same when moving with the leading device of conduct, at I
2The C bus interface circuit is as serial i/when the O circuit began to move, the state of SDA terminal did not change.
As mentioned above, the serial i of embodiment 1/O circuit can be the output initial value of its lead-out terminal of setting state of SDA terminal according to the data level of SDA terminal, so, comprise the I of this serial i/O circuit
2When the C bus interface circuit begins to move as serial i/O circuit, stop condition can not take place mistakenly.In addition, do not need special-purpose hardware,, just obtain to realize I with port I/O combination of circuits
2The serial i of C bus interface circuit/O circuit, thus can obtain that chip area is little, device such as low cost of manufacture, microcontroller that versatility is high, lcd driver.
Fig. 4 is the I that expression has the another embodiment of the present invention that comprises serial i/O circuit 13
2The block diagram of the device of C bus interface circuit.The interface circuit of present embodiment is set in interface circuit as serial i/output initial value of the lead-out terminal OUT of employed serial i/O circuit 13 when the O circuit begins to work by transmitting to the data terminal D of serial i/O circuit 13 from CPU2 output and by the output valve to the output of SDA terminal that output latch 12 latchs.Promptly, according to present embodiment, replace the level that is input to the data on the SDA terminal when using latch cicuit 14 shown in Figure 2 to be latched in the time clock forward position, utilize output latch 12 to latch, and output on the data terminal D of serial i/O circuit 13 to the output valve of SDA terminal transmission, the output initial value of setting lead-out terminal OUT becomes its output valve.About other parts among the figure, identical with the structure of the interface circuit part that is marked with same-sign of embodiment 1 shown in Figure 2, so illustrate and be omitted.
In addition, the same with embodiment 1, processing power height, the CPU of CPU2 that supposes the device of the interface circuit with present embodiment can control the I/O port and realize that arbitration handles.
Fig. 5 a, 5b are the sequential charts of action that is used to illustrate the device of the interface circuit with embodiment of the invention 2, Fig. 5 a represents the waveform of the SCL terminal of device shown in Figure 4, Fig. 5 b represents the waveform of the SDA terminal of this device, Fig. 5 c represents the waveform of setting terminal s of the initial value initialization circuit 30 of serial i shown in Figure 1/O circuit 13 that this device uses, Fig. 5 d represents the waveform of the data terminal d of this initial value initialization circuit 30, and Fig. 5 e represents the waveform of the lead-out terminal out of this initial value initialization circuit 30.
The same with the situation of the foregoing description 1, at I
2In the C bus, after initial conditions take place, begin to transmit the subordinate address, transmit data then.
At first, the situation that device moves as leading device is described.When SCL was high level, SDA descended, and initial conditions take place.From take place initial conditions to the subordinate address till SDA sends, the same with the situation of embodiment 1, by CPU2 SCL terminal and SDA terminal are controlled as port I/O circuit.For to I
21 device of C bus system is given the complexity arbitration of the authority that constitutes leading device and is handled the control that needs this CPU2 of utilization to carry out.
The same with embodiment 1, pass through I at device
2During the C bus output subordinate address, SCL terminal and SDA terminal can be controlled as port I/O circuit in order to make CPU2, serial i/O circuit 13 is set at the action illegal state by control register 29.At this moment, initial value initialization circuit 30 becomes the permission operating state according to being input to the signal shown in Fig. 5 c that sets on the terminal s.Here, CPU2 also is input on the data terminal d of this initial value initialization circuit 30 from output latch 12 by the output valve to the output of SDA terminal that data bus 3 writes output latch 12, so, the output of this output latch 12 just as with SCL terminal and SDA terminal from port I/O circuit switch to serial i/O circuit on one side the time serial i/O circuit 13 switch to the serial i/O circuit when allowing operating state lead-out terminal OUT the output initial value and read in.As a result, shown in Fig. 5 d, thereby during the forward position of the 9th of the time clock of the SCL terminal shown in Fig. 5 a the output of the high level state of output latch 12 as the initial value of lead-out terminal OUT to data terminal D to the data terminal d of initial value initialization circuit 30 input.This be because, because this device is leading device, so, for can be from the device input low level of subordinate, must be to SDA terminal output high level.
After having passed through that arbitration is handled, the transmission end of subordinate address and subordinate device be transferred to SDA with the affirmation signal of low level state, when the SCL terminal is high level, for example in the moment shown in the dotted line of Fig. 5 a, 5b, CPU2 switches to serial i/O circuit on one side with two terminals of SCL, SDA from port I/O circuit by selector switch 6, selector switch 11 and switch 8 being set at the state of appointment.And CPU2 is by control serial i/O circuit 13, and beginning sends the data of data or reception subordinate device to the subordinate device.At this moment, for CPU2 can control two terminals of SCL, SDA as the terminal of serial i/O circuit, serial i/O circuit 13 is the action License Status according to the content setting of control register 29.At this moment, initial value initialization circuit 30 is maintained the prohibited acts state according to supplying with the signal shown in Fig. 5 c that sets terminal s.
Become the initial value initialization circuit 30 of prohibited acts state, the output that will be input to the transmission shift register 28 on its input terminal in according to the sequential of tranmitting data register signal outputs on the lead-out terminal OUT of serial i/O circuit 13 from its lead-out terminal out.The same with embodiment 1, if the arbitration processing has been passed through in being transmitted in of data when sending the subordinate address, then leading device just is himself, for later data transmission, handled with regard to not needing to arbitrate, so CPU2 can only control SCL terminal and SDA terminal as the terminal of serial i/O circuit, thereby can transmit desirable data by SDA.
As mentioned above, in the moment shown in the dotted line of Fig. 5 a, 5b, two terminals of SCL, SDA switch to the terminal of serial i/O circuit from the terminal of port I/O circuit.Before this, the initial value of the lead-out terminal OUT of serial i/O circuit 13 is the high level that is added to the setting value on the SDA terminal by CPU2 by initial value initialization circuit 30 beginning to be set at during the 9th clock cycle that is input on the SCL terminal from address transmission action.On the other hand, in subordinate device one side, SCL be high level during in the affirmation signal of output low level always.Therefore, thus serial i/O circuit 13 switches to action License Status I from the action illegal state
2When the C bus interface circuit begins to move as serial i/O circuit, thereby initial value initialization circuit 30 just remains the high level state that is determined by above-mentioned initial value with the output of lead-out terminal OUT with the output of its lead-out terminal out, shown in Fig. 5 b, the state of SDA terminal does not change.
Below, the situation that device moves as the subordinate device is described.The same with the situation of moving as leading device, from detecting initial conditions to receiving the subordinate address, CPU2 controls two terminals of SCL, SDA as the terminal of port I/O circuit.After receiving the subordinate address and confirmation signal returned, after being about to low level and writing output latch 12 and output to the affirmation signal of low level state on the SDA terminal, when the SCL terminal is high level, CPU2 is by being set at the state of appointment with selector switch 6, selector switch 11 and switch 8, and SCL terminal and SDA terminal are switched to serial i/O circuit from port I/O circuit.And CPU2 receives the data of leading device or sends data to leading device by control serial i/O circuit 13.
Before two terminals of SCL, SDA were switched to the terminal of serial i/O circuit from the terminal of port I/O circuit, the output initial value of the lead-out terminal OUT of serial i/O circuit 13 was the low level that is added to the setting value on the SDA terminal by CPU2 by initial value initialization circuit 30 send from the address that action begins to be set at during the 9th clock cycle that is added on the SCL terminal.Therefore, the same when moving with the leading device of conduct, even I
2The C bus interface circuit begins the action as serial i/O circuit, and the level of SDA terminal does not change yet.
Like this, according to embodiment 2, owing to use the level that is added to the data on the SDA terminal by port I/O circuit to set the output initial value of the lead-out terminal of serial i/O circuit, so, stop condition can not take place mistakenly.In addition, in device, owing to do not need shown in Figure 2 latching the latch cicuit 14 that is input to the data level on the SDA terminal from the time clock forward position of SCL terminal input, so, can obtain further to dwindle the device of chip area.
As mentioned above, according to the 1st aspect of the present invention, the data terminal that the initial value initialization circuit of output initial value of lead-out terminal of setting serial i/O circuit and input are used for the data that this initial value sets is set, when this serial i/O circuit is set at the action illegal state, to send data from lead-out terminal to SDA output from the data of data terminal input, when this serial i/O circuit is set at the action License Status, output to the transmission data on the SDA from the output of its lead-out terminal from this serial i/O circuit, so, realize I with port I/O combination of circuits
2During the C bus interface circuit, can not make I thereby can obtain stop condition not to take place mistakenly in the moment that switches to serial i/O circuit from port I/O circuit
2The serial i that the C bus system can not set up/O circuit.
According to the 2nd aspect of the present invention, has clock generating circuit, switch, sending controling circuit, output buffer, reception control circuit, receive shift register, receive buffer register, send buffer register, send in the serial i/O circuit of shift register and control register, the initial value initialization circuit and the data terminal of importing the data that are used for this initial value setting of the output initial value of setting serial i/O circuit are set, when the setting terminal of this initial value initialization circuit is set at the permission action by control register, just will output on the lead-out terminal from initial value setting lead-out terminal from the value that data terminal is input on the initial value setting data terminal, if when being set at prohibited acts, just will output on the lead-out terminal from initial value setting lead-out terminal according to the sequential that is input to the tranmitting data register signal on the initial value setting clock terminal from the transmission data that the transmission shift register is input on initial value set input, so, can stop condition not take place in the moment of mistake, can obtain and can realize I with port I/O combination of circuits
2The serial i of C bus interface circuit/O circuit, thus can realize that chip area is little, low cost of manufacture, device that versatility is high.
According to the 3rd aspect of the present invention, the data level of SDA when changing owing to the clock with SCL is input to the data terminal that input is used for the data of initial value setting, so, carry out the setting of initial value according to the data level of SDA terminal, stop condition can not take place mistakenly, do not need special-purpose hardware, just can obtain and to realize I with port I/O combination of circuits
2The serial i of C bus interface circuit/O circuit, thus can obtain that chip area is little, low cost of manufacture, the high device of versatility simultaneously.
According to the 4th aspect of the present invention, as the data that initial value is set that are used for that are input on the data terminal, be that the data that output on the SDA when this serial i/O circuit is the action illegal state are input to the data terminal that input is used for the data of initial value setting, so, even in device, do not prepare to be latched in the latch cicuit that is input to the data level on the SDA terminal from the forward position of the time clock of SCL terminal input etc. in addition, also can be according to setting initial value to the output data of SDA terminal output, so, stop condition can not take place mistakenly, do not need special-purpose hardware, just can obtain and to realize I with port I/O combination of circuits
2The serial i of C bus interface circuit/O circuit, thus can obtain that chip area is little, cost is low, the high device of versatility simultaneously.
According to the 5th aspect of the present invention, the data terminal that the initial value initialization circuit of output initial value of lead-out terminal of setting serial i/O circuit and input are used for the data that this initial value sets is set in serial i/O circuit, when serial i/O circuit is set at the action illegal state, to export from the lead-out terminal that sends data to SDA output from the data of data terminal input, when being set at the action License Status, to export from this lead-out terminal from the transmission data that serial i/O circuit outputs on the SDA, so, can obtain I
2Thereby in the moment that switches to serial i/O circuit from port I/O circuit stop condition can taking place mistakenly, the C bus interface circuit can not make I
2The I that the C bus system can not set up
2The C bus interface circuit.
According to the 6th aspect of the present invention, has clock generating circuit, switch, sending controling circuit, output buffer, reception control circuit, receive shift register, receive buffer register, send buffer register, send in the serial i/O circuit of shift register and control register, the initial value initialization circuit and the data terminal of importing the data that are used for the initial value setting of the output initial value of setting serial i/O circuit are set, when the setting terminal of this initial value initialization circuit is set at the permission action by control register, to output on the lead-out terminal from initial value setting lead-out terminal from the value that data terminal is input on the initial value setting data terminal, when being set at prohibited acts, to output on the lead-out terminal from initial value setting lead-out terminal according to the sequential that is input to the tranmitting data register signal on the initial value setting clock terminal from the transmission data that the transmission shift register is input on initial value set input, so, can stop condition not take place in the moment of mistake, thereby can realize that chip area is little, low cost of manufacture, the device that versatility is high.
According to the 7th aspect of the present invention, the data level of SDA when changing by the clock of the latch circuit latches SCL of port I/O circuit, and be input to the data terminal that input is used for the data that initial value sets, so, carry out the setting of initial value according to the data level of SDA terminal, stop condition can not take place mistakenly, thereby can obtain that chip area is little, cost is low, the high device of versatility simultaneously.
According to the 8th aspect of the present invention, as the data that initial value is set that are used for that are input on the data terminal, be that the data that output on the SDA when this serial i/O circuit is the action illegal state are input to the data terminal that input is used for the data of initial value setting, so, even in device, do not prepare to be latched in the latch cicuit that is input to the data level on the SDA terminal from the time clock forward position of SCL terminal input etc. in addition, also can be according to setting initial value to the output data of SDA terminal output, so, stop condition can not take place mistakenly, thereby it is little to obtain chip area, cost is low, the high device of while versatility.
Claims (8)
1. the serial input/output circuit of a serial bus interface circuit that is made of with data circuit the clock line that utilizes pull-up resistor to draw on carrying out and realizes being connected with the bidirectional linked list bus that above-mentioned clock line and above-mentioned data circuit is all had open drain output is characterized in that: have the clock terminal that is used for transceiver clock signal that can be connected with the above-mentioned clock line of above-mentioned bidirectional linked list bus;
The input terminal that is used to receive the data on the above-mentioned data circuit that can be connected with the above-mentioned data circuit of above-mentioned bidirectional linked list bus;
What can be connected with above-mentioned data circuit is used for and will sends the lead-out terminal of data transmission to the above-mentioned data circuit;
Receive the data of supplying with, the data terminal that before this serial input/output circuit can move, is used for the output initial value of above-mentioned lead-out terminal is set at the value of above-mentioned data;
This serial input/output circuit remain the action illegal state during receive to supply with the data of above-mentioned data terminal and these data exported to above-mentioned lead-out terminal, switch to action at this serial input/output circuit from the action illegal state and the output of above-mentioned lead-out terminal remained during License Status state by above-mentioned initial value decision, this serial input/output circuit remain the action License Status during receive data that serial supplies with and these data outputed to initial value setting device on the above-mentioned data circuit by above-mentioned lead-out terminal serial;
When the internal clocking pattern, generate and send clock signal, externally receive the clock signal of supplying with above-mentioned clock terminal and the clock apparatus that sends this clock signal during clock module;
Respond the clock signal of above-mentioned clock apparatus and temporary transient storage should send on the above-mentioned data circuit data and with the dispensing device of this data serial ground to above-mentioned initial value setting device transmission;
Respond the clock signal of above-mentioned clock apparatus and the receiving trap of the data that temporary transient storage receives by above-mentioned input terminal and write and this serial input/output circuit is become to move or the control register of the data of prohibited acts.
2. by the described serial input/output circuit of claim 1, it is characterized in that: the clock generating circuit that clock signal takes place when being included in inner clock module above-mentioned clock apparatus with is connected with above-mentioned clock generating circuit select the clock signal of above-mentioned clock generating circuit when the internal clocking pattern, externally select the clock signal of above-mentioned clock terminal and the switch that selected clock signal is exported to above-mentioned dispensing device during clock module; Above-mentioned dispensing device comprises the clock signal that responds above-mentioned switch and the transmission buffer register of the data that the sending controling circuit that generates the tranmitting data register signal, temporary transient storage are supplied with and from above-mentioned transmission buffer register reading of data and the transmission shift register that these data transmitted to above-mentioned initial value setting device bit by bit with the tranmitting data register signal Synchronization ground of above-mentioned sending controling circuit; Above-mentioned receiving trap comprise the tranmitting data register signal that responds above-mentioned sending controling circuit and generate the reception shift register of the sending controling circuit, reception of receive clock signal and data that above-mentioned input terminal is supplied with on above-mentioned receive clock signal Synchronization ground by turn and temporary transient these data of storage and when all of above-mentioned data store in the above-mentioned reception shift register from the reception buffer register of above-mentioned reception shift register reading of data.
3. by claim 1 or 2 described serial input/output circuits, it is characterized in that: when this serial input/output circuit remains the action illegal state, in each pulse front edge of the clock signal of the clock line of above-mentioned universal serial bus or back along the time, latch the data on the data circuit of above-mentioned universal serial bus, the output initial value of above-mentioned lead-out terminal is set at the value of above-mentioned latched data.
4. by claim 1 or 2 described serial input/output circuits, it is characterized in that: when this serial input/output circuit remains the action illegal state, the data that are transferred on the above-mentioned data circuit by above-mentioned serial bus interface circuit are input on the above-mentioned data terminal of above-mentioned serial input/output circuit, and the output initial value of above-mentioned lead-out terminal is set at the value of above-mentioned data.
5. the serial bus interface circuit of carrying out that is connected by the bidirectional linked list bus with above-mentioned clock line and above-mentioned data circuit all being had open drain output of utilizing the clock line that draws on the pull-up resistor to constitute with data circuit and this bidirectional linked list bus interface is characterized in that: comprise having the clock terminal that is used for transceiver clock signal that is connected with the above-mentioned clock line of above-mentioned bidirectional linked list bus;
The input terminal that is used to receive the data on the above-mentioned data circuit that can be connected with the above-mentioned data circuit of above-mentioned bidirectional linked list bus;
What can be connected with above-mentioned data circuit is used for and will sends the lead-out terminal of data transmission to the above-mentioned data circuit;
The data of receive supplying with, this serial input/output circuit become can move before the output initial value of above-mentioned lead-out terminal be set at the data terminal of the value of above-mentioned data;
This serial input/output circuit remain the action illegal state during receive to supply with the data of above-mentioned data terminal and these data exported to above-mentioned lead-out terminal, switch to action at this serial input/output circuit from the action illegal state and the output of above-mentioned lead-out terminal remained during License Status state by above-mentioned initial value decision, this serial i/O circuit remain the action License Status during receive data that serial supplies with and these data outputed to initial value setting device on the above-mentioned data circuit by above-mentioned lead-out terminal serial;
When the internal clocking pattern, generate and send clock signal, externally receive the clock signal of supplying with above-mentioned clock terminal and the clock apparatus that sends this clock signal during clock module;
Respond the clock signal of above-mentioned clock apparatus and temporarily store data that send on the above-mentioned data circuit and the dispensing device that this data serial ground is sent to above-mentioned initial value setting device;
Respond the clock signal of above-mentioned clock apparatus and the receiving system of the data that temporary transient storage receives by above-mentioned input terminal and write and this serial input/output circuit is become to move or the serial input/output circuit of the control register of the data of prohibited acts and when serial input/output circuit is prohibited acts, receive data and the clock signal on the above-mentioned clock line on the above-mentioned data circuit or transfer data on the above-mentioned data circuit, clock signal is transferred to port imput output circuit on the clock line.
6. by the described serial bus interface circuit of claim 5, it is characterized in that: the clock generating circuit that clock signal takes place when being included in inner clock module above-mentioned clock apparatus with is connected with above-mentioned clock generating circuit select the clock signal of above-mentioned clock generating circuit when the internal clocking pattern, externally select the clock signal of above-mentioned clock terminal and the switch that selected clock signal is exported to above-mentioned dispensing device during clock module;
Above-mentioned dispensing device comprises the clock signal that responds above-mentioned switch and the transmission buffer register of the data that the sending controling circuit that generates the tranmitting data register signal, temporary transient storage are supplied with and from above-mentioned transmission buffer register reading of data and the transmission shift register that these data transmitted to above-mentioned initial value setting device bit by bit with the tranmitting data register signal Synchronization ground of above-mentioned sending controling circuit;
Above-mentioned receiving trap comprise the tranmitting data register signal that responds above-mentioned sending controling circuit and generate the reception shift register of the sending controling circuit, reception of receive clock signal and data that above-mentioned input terminal is supplied with on above-mentioned receive clock signal Synchronization ground by turn and temporary transient these data of storage and when all of above-mentioned data store in the above-mentioned reception shift register from the reception buffer register of above-mentioned reception shift register reading of data.
7. by claim 5 or 6 described serial bus interface circuits, it is characterized in that: above-mentioned port imput output circuit have in each pulse front edge of the clock signal of the clock line of above-mentioned universal serial bus or back along the time latch the latch cicuit of the data on the data circuit of above-mentioned universal serial bus, when above-mentioned serial input/output circuit remains the action illegal state, above-mentioned latch cicuit is with the data terminal output of latched data to above-mentioned serial input/output circuit, and the output initial value of above-mentioned lead-out terminal is set at the value of above-mentioned latched data.
8. by claim 5 or 6 described serial bus interface circuits, it is characterized in that: when above-mentioned serial input/output circuit remains the action illegal state, the data that outputed on the above-mentioned data circuit by above-mentioned serial interface circuit are input on the above-mentioned data terminal of above-mentioned serial input/output circuit, and the output initial value of above-mentioned lead-out terminal is set at the value of above-mentioned data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN97116197A CN1188281A (en) | 1997-01-17 | 1997-08-22 | Serial input/output circuit and serial bus interface circuit |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6653/97 | 1997-01-17 | ||
| CN97116197A CN1188281A (en) | 1997-01-17 | 1997-08-22 | Serial input/output circuit and serial bus interface circuit |
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| Publication Number | Publication Date |
|---|---|
| CN1188281A true CN1188281A (en) | 1998-07-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN97116197A Pending CN1188281A (en) | 1997-01-17 | 1997-08-22 | Serial input/output circuit and serial bus interface circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100428211C (en) * | 2005-11-03 | 2008-10-22 | 凌阳科技股份有限公司 | Circuits at sending end, circuits at receiving end, interface switching module, and interface switching method |
| CN102163180A (en) * | 2011-01-20 | 2011-08-24 | 电子科技大学 | I2C bus interface circuit module and control method thereof |
| CN101770443B (en) * | 2009-01-07 | 2012-05-23 | 成都市华为赛门铁克科技有限公司 | Time sequence adjusting method for internal IC (integrated circuit) bus, corresponding device and system thereof |
-
1997
- 1997-08-22 CN CN97116197A patent/CN1188281A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100428211C (en) * | 2005-11-03 | 2008-10-22 | 凌阳科技股份有限公司 | Circuits at sending end, circuits at receiving end, interface switching module, and interface switching method |
| CN101770443B (en) * | 2009-01-07 | 2012-05-23 | 成都市华为赛门铁克科技有限公司 | Time sequence adjusting method for internal IC (integrated circuit) bus, corresponding device and system thereof |
| CN102163180A (en) * | 2011-01-20 | 2011-08-24 | 电子科技大学 | I2C bus interface circuit module and control method thereof |
| CN102163180B (en) * | 2011-01-20 | 2013-02-13 | 电子科技大学 | I2C bus interface circuit module and control method thereof |
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