CN103500154B - A kind of serial bus interface chip, serial bus transmission system and method - Google Patents
A kind of serial bus interface chip, serial bus transmission system and method Download PDFInfo
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- CN103500154B CN103500154B CN201310414135.8A CN201310414135A CN103500154B CN 103500154 B CN103500154 B CN 103500154B CN 201310414135 A CN201310414135 A CN 201310414135A CN 103500154 B CN103500154 B CN 103500154B
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Abstract
The invention discloses a kind of serial bus interface chip, serial bus transmission system and method.This serial bus interface chip includes bus interface circuit and the logic processing circuit of electrical connection, bus interface circuit includes two data-interfaces and two clock interfaces, logic processing circuit overturns according to the level of said two data-interface or said two clock interface after the power-up and determines Serial Control direction, i.e., determine that each data-interface and clock interface are respectively input interface or output interface, subsequently into instruction waiting state；If logic processing circuit receives address and issues instruction, then receive address signal from input interface, and produce new address signal, and by described new address signal output.Implement technical scheme, it is possible to decrease the cost of serial bus transmission system.
Description
Technical field
The present invention relates to the serial bus technology field of communication, especially relate to a kind of serial bus interface core
Sheet, serial bus transmission system and method.
Background technology
In the communication system utilizing universal serial bus networking, generally comprise main control device and multiple from equipment.
When main control device with multiple communicate from equipment time, each must set unique address from equipment
Code, guarantee main control device identification some specifically from equipment.It is divided into string from the control bus of equipment
Row and parallel two big classes, the control line used in parallel bus is all more than 8, so this
Parallel bus seldom uses.Universal serial bus mainly has following three kinds of bus: SPI at present
Bus, I2C bus and 1W bus.These three bus is required for from the serial bus interface core of equipment
Sheet is addressed, and, it is impossible to judge that the series connection in whole communication system of the serial bus interface chip is suitable
Sequence.Therefore, in the urgent need to a kind of serial bus interface chip, it is not necessary to set from the address of equipment can
To identify the series sequence judging chip place wiring board, the one-tenth of serial communication system can also be reduced simultaneously
This.
Summary of the invention
The technical problem to be solved in the present invention is, for the defect that the above-mentioned cost of prior art is high, carries
A kind of serial bus interface chip, serial bus transmission system and method for low cost.
The technical solution adopted for the present invention to solve the technical problems is: a kind of serial bus interface core of structure
Sheet, is connected with from equipment controlled device, and described serial bus interface chip includes the EBI of electrical connection
Circuit and logic processing circuit, described bus interface circuit include two bi-directional data interfaces and respectively with often
Two bidirectional clock interfaces that individual data-interface is corresponding, and,
Described logic processing circuit is after the power-up according to said two data-interface or said two clock interface
Level upset determine Serial Control direction, i.e. determine that each data-interface and clock interface are the most defeated
Incoming interface or output interface, subsequently into instruction waiting state；
If described logic processing circuit receives address and issues instruction, then receive address signal from input interface,
And produce new address signal, and by described new address signal output.
In serial bus interface chip of the present invention, refer to if described logic processing circuit receives control
Order, then said two data-interface is according to control instruction conversion transmission direction, and said two clock interface exists
Keep clock transfer direction constant after determining Serial Control direction.
In serial bus interface chip of the present invention,
If described logic processing circuit receives reading instruction, then judge to read address and this serial bus interface core
Whether the address of sheet mates, if coupling, then enters reading state, and, in the state of reading, will instruction
Data Input Interface in waiting state is set to data output interface；If not mating, then enter and read service
State, and, reading service state, the Data Input Interface in instruction waiting state is being set to data
Output interface, is set to Data Input Interface by the data output interface in instruction waiting state.
In serial bus interface chip of the present invention,
If described logic processing circuit receives write command, then judge write address and this serial bus interface chip
Address whether mate, if coupling, then enter write state, and, at write state, by instruction etc.
Treat that the Data Input Interface in state is still set to Data Input Interface；If not mating, then enter and write clothes
Business state, and, writing service state, the Data Input Interface in instruction waiting state is still being arranged
For Data Input Interface, the data output interface in instruction waiting state is still set to data output and connects
Mouthful.
In serial bus interface chip of the present invention, described serial bus interface built-in chip type or outer
Connect memorizer.
The present invention also constructs a kind of serial bus transmission system, including main equipment and multiple from equipment, each
All include from equipment from equipment controlled device, described also include above-described serial bus interface from equipment
Chip, described serial bus interface chip is connected from equipment controlled device with described, and, if specific string
Belonging to row bus interface chip from equipment be non-first from equipment the most non-final one from equipment, then should
The of first data-interface of serial bus interface chip and the previous serial bus interface chip from equipment
Two data-interfaces are connected, the first clock interface of this serial bus interface chip and the previous string from equipment
The second clock interface of row bus interface chip is connected；If belonging to particular serial Bus Interface Chip from setting
For being first, from equipment, then the first data-interface of this serial bus interface chip is connected with main equipment,
First clock interface of this serial bus interface chip is connected with main equipment；If particular serial EBI core
Belonging to sheet from equipment be last from equipment, then the first data-interface of this serial bus interface chip
With previous from equipment the second data-interface of serial bus interface chip be connected, this universal serial bus connects
First clock interface of mouth chip and the second clock interface of the previous serial bus interface chip from equipment
Being connected, the second data-interface of this serial bus interface chip, second clock interface are unsettled.
The present invention also constructs a kind of serial bus transmission method, including:
A. from the logic processing circuit of equipment after the power-up according to said two data-interface or said two time
The level upset of clock interface determines Serial Control direction, i.e. determine that each data-interface and clock interface divide
Not Wei input interface or output interface, subsequently into instruction waiting state；
If the most described logic processing circuit receives address and issues instruction, then receive address signal from input interface,
And produce new address signal, and by described new address signal output.
In serial bus transmission method of the present invention, after described step A, also include:
If C. receiving control instruction from the logic processing circuit of equipment, then said two data-interface is according to control
Instruction map processed transmission direction, said two clock interface keeps clock to pass after determining Serial Control direction
Defeated direction is constant.
In serial bus transmission method of the present invention, described step C includes:
If C1. receiving reading instruction from the logic processing circuit of equipment, then judge to read address total with this serial
Whether the address of line interface chip mates, if coupling, then enters reading state, and, in the state of reading,
Data Input Interface in instruction waiting state is set to data output interface；If not mating, then enter
Read service state, and, reading service state, the Data Input Interface in instruction waiting state is being arranged
For data output interface, the data output interface in instruction waiting state is set to Data Input Interface.
In serial bus transmission method of the present invention, described step C includes:
If C2. receiving write command from the logic processing circuit of equipment, then judge write address and this universal serial bus
Whether the address of interface chip mates, if coupling, then enters write state, and, at write state,
Data Input Interface in instruction waiting state is still set to Data Input Interface；If not mating, then
Service state is write in entrance, and, writing service state, by the Data Input Interface in instruction waiting state
Still it is set to Data Input Interface, the data output interface in instruction waiting state is still set to number
According to output interface.
In serial bus transmission method of the present invention, described step A includes:
A1. it is in idle condition after the power-up from the logic processing circuit of equipment and clock count is reset；
A2. in idle condition, two data-interfaces are set and are input interface, monitor two clock interfaces
Clock signal and clock signal is counted respectively；
Judge whether clock count arrives setting threshold value the most respectively, the most then perform step A4；If it is not,
Then repeated execution of steps A3；
A4. determine Serial Control direction according to following methods: clock count is arrived first at set threshold value time
Data-interface corresponding to clock interface is as input interface, using another data-interface as output interface.
In serial bus transmission method of the present invention, described step B includes:
If the most described logic processing circuit receives address and issues instruction, then begin listening for clock signal；
If B2. after receiving i-th clock signal, the level of input interface converts, i be natural number and
With this serial bus interface chip in all sequence number phases of connecting from the serial bus interface chip of equipment
Close, it is determined that i is the address of this serial bus interface chip；
B3. according to the relation of next serial bus interface chip with sequence number of connecting, control output interface and exist
Output level conversion signal after corresponding clock signal.
Implement technical scheme, it is not necessary to set logical exclusively for each serial bus interface chip
Letter address, after determining Serial Control direction, so that it may realizes dynamic address coding, therefore from equipment originally
Body need not special address and arranges circuit, thus reduces the cost of serial bus transmission system.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the invention will be further described, in accompanying drawing:
Fig. 1 is the logic chart of serial bus transmission system embodiment one of the present invention；
Fig. 2 is the logic chart of serial bus interface chip embodiment one of the present invention；
Fig. 3 is the flow chart of serial bus transmission embodiment of the method one of the present invention；
Fig. 4 is the flow chart of serial bus transmission embodiment of the method two of the present invention；
Fig. 5 A-Fig. 5 G is the logic chart of seven kinds of states of serial bus transmission system of the present invention.
Detailed description of the invention
Fig. 1 is the logic chart of serial bus transmission system embodiment one of the present invention, this serial bus transmission system
System includes main equipment and multiple from equipment 1,2,3 (illustrate only three figure), each wraps from equipment
Include electrical connection from equipment controlled device and serial bus interface chip.Main equipment passes through two holding wire structures
The universal serial bus become has been connected multiple from equipment, and one is data signal line, and one is clock cable.
That is, main equipment is connected with the serial bus interface chip from equipment 1 by data signal line；From equipment 1
Serial bus interface chip is connected with the serial bus interface chip from equipment 2 by data signal line, depends on
Secondary analogize.Meanwhile, main equipment by clock cable for providing clock signal from equipment 1, each from
Equipment provides clock signal for what the next one was connected from equipment by clock cable.Each is from equipment
Serial bus interface chip Monitoring and Controlling order, in service state, according to the control command detected
Needs are the serial bus interface chip transparent left biography of offer from equipment of next series connection with it or right biography
Service.So, main equipment each necessary data from equipment can be written and read operation or to each from
Equipment controls accordingly and monitors.
Fig. 2 is the logic chart of serial bus interface chip embodiment one of the present invention, this serial bus interface core
Sheet includes bus interface circuit and the logic processing circuit of electrical connection, and wherein, bus interface circuit includes two
Individual bi-directional data interface and two corresponding with each data-interface respectively bidirectional clock interfaces, two numbers
Being respectively the first data-interface, the second data-interface according to interface, two clock interfaces are respectively the first clock
Interface, second clock interface.Multiple different between equipment, later is from the first data of equipment
Interface is connected with previous the second data-interface from equipment, first from the first data-interface of equipment with
Main equipment is connected, and last is unsettled from the second data-interface of equipment.It addition, multiple different from
Between equipment, later connects from the second clock interface of equipment with previous from the first clock interface of equipment
Connecing, first is connected with main equipment from the first clock interface of equipment, and last is when the second of equipment
Clock interface is unsettled.And, have only to a holding wire between the first data-interface and the second data-interface,
And it is all bidirectional interface.First data-interface and the second data-interface receive the control of logic processing circuit
Realize a left side pass on Gong can and the right side pass on Gong energy.A signal is only needed between first clock interface and second clock interface
Line, and be all bidirectional interface.First, second clock interface receives clock signal, so that logical process
Circuit can be from external reception clock signal.
Logic processing circuit overturns really according to the level of two data-interfaces or two clock interfaces after the power-up
Determine Serial Control direction, i.e. determine that each data-interface and clock interface are respectively input interface or output
Interface, subsequently into instruction waiting state.Such as, in one example, logic processing circuit is powering on
After be in idle condition and to clock count reset, and, in idle condition, two data-interfaces are set
It is input interface, monitors clock signal and basis determines Serial Control direction to the counting of clock signal,
That is, determine that each data-interface and clock interface are respectively input interface or output interface, can be by with lower section
Method determines Serial Control direction: clock count arrives first at the number corresponding to clock interface setting threshold value
According to interface as input interface, using another data-interface as output interface, with Data Input Interface phase
Corresponding clock interface is clock input interface, and the clock interface corresponding with data output interface is clock
Output interface.Determining Serial Control side back into instruction waiting state；Certainly, more than the most originally
One specific embodiment of invention, logic processing circuit the most also can be according to two data interface levels
Upset determines Serial Control direction, such as, first data-interface or the level upset time of level upset occurs
It is input interface that number reaches the data-interface of preset times, and another data-interface is output interface, then
Correspondingly determine the direction of two clock interfaces.
If described logic processing circuit receives address and issues instruction, then receive address signal from input interface,
And produce new address signal, it is unique that this new address signal ensures in serial bus transmission system,
And described new address signal is exported by output interface.Such as, in a specific embodiment, if
Described logic processing circuit receives address and issues instruction, then begin listening for clock signal, and, if receiving
After i-th clock signal, the level of input interface converts, and i is natural number and connects with this universal serial bus
Mouth chip is correlated with in all series connection sequence numbers from the serial bus interface chip of equipment, it is determined that i is this string
The address of row bus interface chip, meanwhile, according to next serial bus interface chip and sequence number of connecting
Relation, controls output interface output level conversion signal after corresponding clock signal.In one example,
Can set and be series connection sequence number from the address of the serial bus interface chip of equipment, now, first from setting
Standby serial bus interface chip after receiving the 1st clock signal, its input interface (such as, first
Data-interface) level convert (such as, by high level step-down level), now, it may be determined that this is years old
One address from the serial bus interface chip of equipment is 1.Then, first from the universal serial bus of equipment
The output interface (such as, the second data-interface) of interface chip under the control of its logic processing circuit,
Output level conversion signal (such as, by high level step-down level) after the 2nd clock signal, correspondingly,
Second from the serial bus interface chip of equipment after receiving the 2nd clock signal, its input interface (example
Such as the first data-interface, this first data-interface and first are connected from the second data-interface of equipment)
Level converts (such as, by high level step-down level), now, it may be determined that this second from equipment
The address of serial bus interface chip is 2, the like, the follow-up universal serial bus from equipment can be determined successively
The address of interface chip.Certainly, in other embodiments, from the ground of the serial bus interface chip of equipment
Location and the relation of the sequence number of connecting of this serial bus interface chip can be also linear function relation or other a pair
The relation of one.It should be noted that equally, be more than a specific embodiment of the present invention, certainly, string
The input interface of row bus interface chip also can directly receive address signal, and this address and this universal serial bus
Interface chip is uncorrelated in all series connection sequence numbers from the serial bus interface chip of equipment.
Implement above technical scheme, it is not necessary to set communicatedly exclusively for each serial bus interface chip
Location, after determining Serial Control direction, can according to each from the serial bus interface chip of equipment whole
Individual series connection sequence number from the serial bus interface chip of equipment, so that it may realize dynamic address coding, i.e.
" series sequence " of each serial bus interface chip is equivalent to mailing address, i.e. main control device be in strict accordance with
From the series sequence of equipment, carry out data read-write operation singly, therefore need not from equipment itself
Special address arranges circuit, thus reduces the cost of serial bus transmission system.
If logic processing circuit receives control instruction, then two data-interfaces are according to control instruction conversion transmission
Direction, two clock interfaces keep clock transfer direction constant after determining Serial Control direction.
Such as, if logic processing circuit receives reading instruction, then judge to read address and this serial bus interface
Whether the address of chip mates, if coupling, then enters reading state, and, in the state of reading, will refer to
Making the input interface in waiting state (such as, the first data-interface) be set to output interface, this is first years old
The local data that data-interface output reads, after reading some Bit datas continuously, entry instruction waits shape
State, in instruction waiting state, former input interface (the first data-interface) is still input interface, former defeated
Outgoing interface (the second data-interface) is still output interface, the data of output interface input and output interfaces,
Control command or data will be delivered to next serial bus interface chip by " right biography passage ".
If logic processing circuit receives reading instruction, and judges to read address and this serial bus interface chip
Address is not mated, then enter and read service state, and, reading service state, will instruct in waiting state
Input interface be set to output interface, by instruction waiting state in output interface be set to input interface,
Now, the data that this serial bus interface chip is responsible for next serial bus interface chip reads are passed through
Left biography passage is delivered to previous serial bus interface chip.
The most such as, if described logic processing circuit receives write command, then judge write address and this universal serial bus
Whether the address of interface chip mates, if coupling, then enters write state, and, at write state,
Input interface (such as, the first data-interface) in instruction waiting state is still set to input interface,
Start to write Bit data to this from equipment.Then, entry instruction waiting state, in instruction waiting state,
Former input interface (the first data-interface) is still input interface, former output interface (the second data-interface)
It is still output interface, the data of output interface input and output interfaces, will control command or data pass through
" right biography passage " is delivered to next serial bus interface chip.It addition, also, it should be noted above
It is one embodiment of the present of invention, in other embodiments, at write state, will instruct in waiting state
Input interface (such as, the first data-interface) be still set to input interface, waiting state will be instructed
In output interface (such as, the second data-interface) be set to output interface.
If described logic processing circuit receives write command, and judges write address and this serial bus interface chip
Address do not mate, then enter write service state, and, writing service state, waiting state will instructed
In input interface (the first data-interface) be still set to input interface, will instruction waiting state in
Output interface (the second data-interface) is still set to output interface, continues through right biography passage to next
The data that the transmission of individual serial bus interface chip is to be write.
The like, when have multiple serial bus interface chip or include serial bus interface chip from setting
Time standby, can be according to each serial bus interface chip of series sequence identification or include serial bus interface
Chip from equipment, and complete the read-write operation of data or the transmission of control instruction.
Finally, it should be noted that, logic processing circuit cannot receive specific quantity under any state
Clock signal be put into idle condition, or enter idle condition by receiving order.Read states, reading
Service state, write state, write service state and address issued state, be referred to as duty, in work
After state terminates, serial bus interface chip automatically returns to instruction waiting state.
Further, since Read-write Catrol interface is bi-directional signal interface, as locally stored or control system
Interface, can electrically connect with memorizer (such as PROM ROM etc.), completes chip functions extension, deposits
Reservoir can be as external memorizer access chip, it is possible to be encapsulated in serial bus interface chip as sheet
Upper storage.
Fig. 3 is the flow chart of serial bus transmission embodiment of the method one of the present invention, this serial bus transmission side
Method includes:
A. from the logic processing circuit of equipment after the power-up according to said two data-interface or said two time
The level upset of clock interface determines Serial Control direction, i.e. determine that each data-interface and clock interface divide
Not Wei input interface or output interface, subsequently into instruction waiting state；
If the most described logic processing circuit receives address and issues instruction, then receive address signal from input interface,
And produce new address signal, and by described new address signal output, this new address signal ensures
Unique in serial bus transmission system.
After step, also include:
If C. receiving control instruction from the logic processing circuit of equipment, then said two data-interface is according to control
Instruction map processed transmission direction, said two clock interface keeps clock to pass after determining Serial Control direction
Defeated direction is constant.Preferably, step A specifically includes:
A1. it is in idle condition after the power-up from the logic processing circuit of equipment and clock count is reset；
A2. in idle condition, two data-interfaces are set and are input interface, monitor two clock interfaces
Clock signal is also counted by clock signal respectively；
Judge whether clock count arrives setting threshold value the most respectively, the most then perform step A4；If it is not,
Then repeated execution of steps A3；
A4. Serial Control direction is determined according to following methods: arrived first at by clock count and set threshold value
Data-interface corresponding to clock interface is as input interface, using another data-interface as output interface.
Preferably, step B specifically includes:
If the most described logic processing circuit receives address and issues instruction, then begin listening for clock signal；
If B2. after receiving i-th clock signal, the level of input interface converts, i be natural number and
With this serial bus interface chip in all sequence number phases of connecting from the serial bus interface chip of equipment
Close, it is determined that i is the address of this serial bus interface chip；
B3. according to the relation of next serial bus interface chip with sequence number of connecting, control output interface and exist
Output level conversion signal after corresponding clock signal.
Fig. 4 is the flow chart of serial bus transmission embodiment of the method two of the present invention, first illustrates, patrols
The control command collecting process circuit reception includes: reading instruction (CMD_RD), write command (CMD_WR)
With distribution address command (CMD_ADD), and, logic processing circuit can realize following logic state
Control:
1) IDLE (idle condition): combine Fig. 5 A, the first data-interface is input state, the second data
Interface is input, and the first clock interface is input state, and second clock interface is input state, during wait
Clock counting determines Serial Control direction；
2) WAIT (instruction waiting state): combine Fig. 5 B, the first data-interface is input state, second
Data-interface is output state, and the first clock interface is input state, and second clock interface is output state,
Wait serial CMD_RD, CMD_WR or CMD_ADD order of the first data-interface；
3) READ (reading state): if the data of second serial bus interface chip need to be read, then tie
Closing Fig. 5 C, the first data-interface of this second serial bus interface chip is output state, the second data
Interface input state, the first clock interface is input state, and second clock interface is output state, every 1
The data that individual clock signal (CLK) output 1bit this locality reads；
4) WRITE (write state): if then need to tie to second serial bus interface chip write data
Closing Fig. 5 D, the first data-interface of this second serial bus interface chip is input state, the second data
Interface is output state, and the first clock interface is input state, and second clock interface is output state, every 1
The data of the local 1bit of individual clock signal (CLK) write；
5) RS (reading service state): if the data of second serial bus interface chip need to be read, then combine
Fig. 5 E, the first data-interface of other dual serial Bus Interface Chip is output state, and the second data connect
Mouth is input state, and the second data-interface is exported by the first data-interface, and the first clock interface is input
State, second clock interface is output state；
6) WS (writing service state): if then need to tie to second serial bus interface chip write data
Closing Fig. 5 F, the first data-interface of other dual serial Bus Interface Chip is input state, the second data
Interface is output state, and the first data-interface is exported by the second data-interface, and the first clock interface is defeated
Entering state, second clock interface is output state；
7) ADD (distribution address): combine Fig. 5 G, the first data-interface is input state, and the second data connect
Mouth is output state, and the first clock interface is input state, and second clock interface is output state, first
Data-interface is exported by the second data-interface, receives address command then this chip address at i-th clock
For n, and chip clockwise the second data-interface OPADD order when the next one, for next chip
Distribution address.
It is in idle condition after the power-up from the logic processing circuit of equipment and clock count is reset, at sky
Not busy state, waits that clock count judges Serial Control direction, and after direction determining is complete, entry instruction waits
State.
If receiving reading instruction in instruction waiting state, and address coupling then entering reading state, otherwise enters
Study in service state, entry instruction waiting state after read states or reading service state terminate.And, reading
Do well, the input interface in instruction waiting state is set to output interface.Reading service state, will
Input interface in instruction waiting state is set to output interface, by the output interface in instruction waiting state
It is set to input interface.
If receiving write command in instruction waiting state, and address coupling then entering write state, otherwise enters and writes
Service state, in write state or write entry instruction waiting state after service state terminates.And, at write shape
State, is still set to input interface by the input interface in instruction waiting state.Writing service state, will
Input interface in instruction waiting state is still set to input interface, by the output in instruction waiting state
Interface is still set to output interface.
If receiving address in instruction waiting state to issue instruction, then enter address issued state, issue in address
Return to after end instruct waiting state.In the issued state of address, if defeated after receiving i-th clock signal
The level of incoming interface converts, i be natural number and with this serial bus interface chip all from equipment
Series connection sequence number in serial bus interface chip is correlated with, it is determined that i is the ground of this serial bus interface chip
Location, meanwhile, according to the relation of next serial bus interface chip with sequence number of connecting, controls output interface
Output level conversion signal after corresponding clock signal.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for this
For the technical staff in field, the present invention can have various change, combines and change.All the present invention's
Within spirit and principle, any modification, equivalent substitution and improvement etc. made, should be included in the present invention
Right within.
Claims (8)
1. a serial bus interface chip, is connected with from equipment controlled device, it is characterised in that described serial bus interface chip bag
Including bus interface circuit and the logic processing circuit of electrical connection, described bus interface circuit includes two bi-directional data interfaces and difference
Two the bidirectional clock interfaces corresponding with each data-interface, and, described logic processing circuit is after the power-up according to described two
Individual data-interface or said two clock interface level upset determine Serial Control direction, i.e. determine each data-interface and time
Clock interface is respectively input interface or output interface, subsequently into instruction waiting state；
If described logic processing circuit receives address and issues instruction, then receive address signal from input interface, and produce new ground
Location signal, and by described new address signal output；
If described logic processing circuit receives control instruction, then said two data-interface is according to control instruction conversion transmission direction,
Said two clock interface keeps clock transfer direction constant, if described logic processing circuit receives after determining Serial Control direction
Reading instruction, then judge to read whether address mates with the address of this serial bus interface chip, if coupling, then enters reading state,
And, in the state of reading, the Data Input Interface in instruction waiting state is set to data output interface；If not mating, then
Enter and read service state, and, reading service state, the Data Input Interface in instruction waiting state is being set to data output
Interface, is set to Data Input Interface by the data output interface in instruction waiting state.
2. a serial bus interface chip, is connected with from equipment controlled device, it is characterised in that described serial bus interface chip bag
Including bus interface circuit and the logic processing circuit of electrical connection, described bus interface circuit includes two bi-directional data interfaces and difference
Two the bidirectional clock interfaces corresponding with each data-interface, and, described logic processing circuit is after the power-up according to described two
Individual data-interface or said two clock interface level upset determine Serial Control direction, i.e. determine each data-interface and time
Clock interface is respectively input interface or output interface, subsequently into instruction waiting state；
If described logic processing circuit receives address and issues instruction, then receive address signal from input interface, and produce new ground
Location signal, and by described new address signal output；
If described logic processing circuit receives control instruction, then said two data-interface is according to control instruction conversion transmission direction,
Said two clock interface keeps clock transfer direction constant, if described logic processing circuit receives after determining Serial Control direction
Write command, then judge whether write address mates with the address of this serial bus interface chip, if coupling, then enters write state,
And, at write state, the Data Input Interface in instruction waiting state is still set to Data Input Interface；If not mating,
Then enter and write service state, and, writing service state, the Data Input Interface in instruction waiting state is still being set to number
According to input interface, the data output interface in instruction waiting state is still set to data output interface.
Serial bus interface chip the most according to claim 1 and 2, it is characterised in that described serial bus interface built-in chip type
Or external memorizer.
4. a serial bus transmission system, including main equipment and multiple from equipment, each all includes from equipment from equipment controlled device,
It is characterized in that, the described serial bus interface chip also included from equipment described in any one of claim 1-3, described serial is total
Line interface chip is connected from equipment controlled device with described, and, if being non-from equipment belonging to particular serial Bus Interface Chip
First from equipment the most non-final one from equipment, then the first data-interface of this serial bus interface chip with previous from equipment
Serial bus interface chip the second data-interface be connected, the first clock interface of this serial bus interface chip with previous from
The second clock interface of the serial bus interface chip of equipment is connected；If belonging to particular serial Bus Interface Chip from equipment be
One from equipment, then the first data-interface of this serial bus interface chip is connected with main equipment, this serial bus interface chip
First clock interface is connected with main equipment；If belonging to particular serial Bus Interface Chip from equipment be last from equipment, then
Second data-interface phase of the first data-interface of this serial bus interface chip and the previous serial bus interface chip from equipment
Even, the first clock interface of this serial bus interface chip connects with the second clock of the previous serial bus interface chip from equipment
Mouth is connected, and the second data-interface of this serial bus interface chip, second clock interface are unsettled.
5. a serial bus transmission method, it is characterised in that including:
A. overturn according to the level of two data-interfaces or two clock interfaces after the power-up from the logic processing circuit of equipment and determine string
Row control direction, i.e. determine that each data-interface and clock interface are respectively input interface or output interface, subsequently into instruction
Waiting state；
If the most described logic processing circuit receives address and issues instruction, then receive address signal from input interface, and produce new
Address signal, and by described new address signal output；
If C. receiving control instruction from the logic processing circuit of equipment, then said two data-interface is according to control instruction conversion transmission
Direction, said two clock interface keeps clock transfer direction constant, if at the logic of equipment after determining Serial Control direction
Reason circuit receives reading instruction, then judge to read whether address mates with the address of this serial bus interface chip, if coupling, then enters
Study in and do well, and, in the state of reading, the Data Input Interface in instruction waiting state is set to data output interface；
If not mating, then enter and read service state, and, reading service state, the Data Input Interface in instruction waiting state is being set
It is set to data output interface, the data output interface in instruction waiting state is set to Data Input Interface.
6. a serial bus transmission method, it is characterised in that including:
A. overturn according to the level of two data-interfaces or two clock interfaces after the power-up from the logic processing circuit of equipment and determine string
Row control direction, i.e. determine that each data-interface and clock interface are respectively input interface or output interface, subsequently into instruction
Waiting state；
If the most described logic processing circuit receives address and issues instruction, then receive address signal from input interface, and produce new
Address signal, and by described new address signal output；
If C. receiving control instruction from the logic processing circuit of equipment, then said two data-interface is according to control instruction conversion transmission
Direction, said two clock interface keeps clock transfer direction constant, if at the logic of equipment after determining Serial Control direction
Reason circuit receives write command, then judge whether write address mates with the address of this serial bus interface chip, if coupling, then enters
Write state, and, at write state, the Data Input Interface in instruction waiting state is still set to Data Input Interface；
If not mating, then enter and write service state, and, writing service state, the Data Input Interface in instruction waiting state is being depended on
So it is set to Data Input Interface, the data output interface in instruction waiting state is still set to data output interface.
7. according to the serial bus transmission method described in claim 5 or 6, it is characterised in that described step A includes:
A1. it is in idle condition after the power-up from the logic processing circuit of equipment and clock count is reset；
A2. in idle condition, two data-interfaces are set and are input interface, monitor two clock interfaces clock signal and pair time
Clock signal counts respectively；
Judge whether clock count arrives setting threshold value the most respectively, the most then perform step A4；If it is not, then repeat step
Rapid A3；
A4. Serial Control direction is determined according to following methods: arrived first at by clock count corresponding to the clock interface of setting threshold value
Data-interface is as input interface, using another data-interface as output interface.
8. according to the serial bus transmission method described in claim 5 or 6, it is characterised in that described step B includes:
If the most described logic processing circuit receives address and issues instruction, then begin listening for clock signal；
If B2. after receiving i-th clock signal, the level of input interface converts, i is natural number and connects with this universal serial bus
Mouth chip is correlated with in all series connection sequence numbers from the serial bus interface chip of equipment, it is determined that i is this serial bus interface core
The address of sheet；
B3. according to the relation of next serial bus interface chip with sequence number of connecting, output interface is controlled after corresponding clock signal
Output level conversion signal.
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| CN104881382A (en) * | 2015-06-15 | 2015-09-02 | 刘晓辉 | Master and slave equipment connection device and address recognition method thereof |
| US9990316B2 (en) * | 2015-09-21 | 2018-06-05 | Qualcomm Incorporated | Enhanced serial peripheral interface |
| CN107256198A (en) * | 2017-05-26 | 2017-10-17 | 郑州云海信息技术有限公司 | Server and the method for server hard disc board distribution I2C addresses |
| CN108270883B (en) * | 2018-02-02 | 2019-11-15 | 深圳曼顿科技有限公司 | Can automatic dispensing device address code method, breaker and storage medium |
| CN109218152A (en) * | 2018-07-19 | 2019-01-15 | 精华隆智慧感知科技（深圳）股份有限公司 | A kind of equipment automatic recognition system |
| CN110059030A (en) * | 2019-04-23 | 2019-07-26 | 南京天数智芯科技有限公司 | A kind of data transmission system and method based on UART serial loop network |
| CN112965926B (en) * | 2021-03-05 | 2024-04-30 | 张玉禄 | SPI interface safety chip and SPI interface electronic device |
| CN117331882B (en) * | 2023-12-01 | 2024-03-29 | 深圳比特微电子科技有限公司 | Chip configuration method and device of chip board, server, electronic equipment and medium |
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