CN103500154A - Serial bus interface chip, serial bus transmission system and method - Google Patents
Serial bus interface chip, serial bus transmission system and method Download PDFInfo
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- CN103500154A CN103500154A CN201310414135.8A CN201310414135A CN103500154A CN 103500154 A CN103500154 A CN 103500154A CN 201310414135 A CN201310414135 A CN 201310414135A CN 103500154 A CN103500154 A CN 103500154A
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Abstract
The invention discloses a serial bus interface chip and a serial bus transmission system and method. The serial bus interface chip comprises a bus interface circuit and a logic processing circuit, the bus interface circuit and the logic processing circuit are electrically connected, the bus interface circuit comprises two data interfaces and two clock interfaces, and after the logic processing circuit is powered on, the serial control direction is determined according to the overturning of the electrical level of the two data interfaces or the two clock interfaces, namely, the fact that each data interface and each clock interface are an input interface or an output interface is determined, then each data interface and each clock interface are in the command waiting state; if the logic processing circuit receives the address issuing command, an address signal is received from the input interface, a new address signal is generated, and the new address signal is output. According to the technical scheme, the cost of the serial bus transmission system is reduced.
Description
Technical field
The present invention relates to the serial bus technology field of communication, especially relate to a kind of serial bus interface chip, serial bus transmission system and method.
Background technology
In the communication system of utilizing the universal serial bus networking, generally comprise main control equipment and a plurality of from equipment.When main control equipment and a plurality of during from devices communicating, each sets unique address code from equipment is essential, and the identification of guarantee main control equipment is some specifically from equipment.Be divided into serial and parallel two large classes from the control bus of equipment, due to parallel bus control line used all more than 8, so in the seldom employing in some applications of this parallel bus.Universal serial bus mainly contains following three kinds of buses at present: spi bus, I2C bus and 1W bus.These three kinds of buses all need the serial bus interface chip from equipment is carried out to addressing, and, can't judge the series sequence of serial bus interface chip in whole communication system.Therefore, in the urgent need to a kind of serial bus interface chip, do not need to set the series sequence that also can identify judgement chip place wiring board from the address of equipment, can reduce the cost of serial communication system yet simultaneously.
Summary of the invention
The technical problem to be solved in the present invention is, the high defect for the above-mentioned cost of prior art, provide serial bus interface chip, serial bus transmission system and method that a kind of cost is low.
The technical solution adopted for the present invention to solve the technical problems is: construct a kind of serial bus interface chip, with from the equipment controlled device, be connected, described serial bus interface chip comprises bus interface circuit and the logic processing circuit of electrical connection, described bus interface circuit comprises two bi-directional data interfaces and two bidirectional clock interfaces corresponding with each data-interface respectively, and
The Serial Control direction is determined in the level upset according to described two data interfaces or described two clock interfaces after powering on of described logic processing circuit,, determine that each data-interface and clock interface are respectively input interface or output interface, then entry instruction waiting status;
If described logic processing circuit is received the address issuing command, from input interface receiver address signal, and produce new address signal, and by described new address signal output.
In serial bus interface chip of the present invention, if described logic processing circuit is received steering order, described two data interfaces convert transmission direction according to steering order, and described two clock interfaces keep the clock transfer direction constant after definite Serial Control direction.
In serial bus interface chip of the present invention,
Read instruction if described logic processing circuit is received, judge whether the address of reading address and this serial bus interface chip mates, if coupling, enter the state of reading, and, reading state, the Data Input Interface in the instruction waiting status is set to data output interface; If do not mate, enter and read service state, and, reading service state, the Data Input Interface in the instruction waiting status is set to data output interface, and the data output interface in the instruction waiting status is set to Data Input Interface.
In serial bus interface chip of the present invention,
If described logic processing circuit is received write command, judge whether the address of write address and this serial bus interface chip mates, if coupling, enter write state, and, at write state, the Data Input Interface in the instruction waiting status still is set to Data Input Interface; If do not mate, enter and write service state, and, writing service state, the Data Input Interface in the instruction waiting status still is set to Data Input Interface, the data output interface in the instruction waiting status still is set to data output interface.
In serial bus interface chip of the present invention, described serial bus interface built-in chip type or external memorizer.
The present invention also constructs a kind of serial bus transmission system, comprise main equipment and a plurality of from equipment, each includes from the equipment controlled device from equipment, describedly from equipment, also comprise above-described serial bus interface chip, described serial bus interface chip is connected from the equipment controlled device with described, and, if under the particular serial Bus Interface Chip from equipment be non-first from equipment also non-last from equipment, the first data-interface of this serial bus interface chip is connected with the second data-interface of the previous chip of the serial bus interface from equipment, the first clock interface of this serial bus interface chip is connected with the second clock interface of the previous chip of the serial bus interface from equipment, if under the particular serial Bus Interface Chip from equipment be first from equipment, the first data-interface of this serial bus interface chip is connected with main equipment, the first clock interface of this serial bus interface chip is connected with main equipment, if under the particular serial Bus Interface Chip is that last is from equipment from equipment, the first data-interface of this serial bus interface chip with previous from equipment the second data-interface of serial bus interface chip be connected, the first clock interface of this serial bus interface chip is connected with the second clock interface of the previous chip of the serial bus interface from equipment, and the second data-interface, the second clock interface of this serial bus interface chip are unsettled.
The present invention also constructs a kind of universal serial bus transmission method, comprising:
A. determine the Serial Control direction from logic processing circuit level upset according to described two data interfaces or described two clock interfaces powering on of equipment,, determine that each data-interface and clock interface are respectively input interface or output interface, then entry instruction waiting status;
If B. described logic processing circuit is received the address issuing command, from input interface receiver address signal, and produce new address signal, and by described new address signal output.
In universal serial bus transmission method of the present invention, after described steps A, also comprise:
If C. from the logic processing circuit of equipment, receive steering order, described two data interfaces convert transmission direction according to steering order, and described two clock interfaces keep the clock transfer direction constant after definite Serial Control direction.
In universal serial bus transmission method of the present invention, described step C comprises:
If C1. from the logic processing circuit of equipment, receive and read instruction, judge whether the address of reading address and this serial bus interface chip mates, if coupling, enter the state of reading, and, reading state, the Data Input Interface in the instruction waiting status is set to data output interface; If do not mate, enter and read service state, and, reading service state, the Data Input Interface in the instruction waiting status is set to data output interface, and the data output interface in the instruction waiting status is set to Data Input Interface.
In universal serial bus transmission method of the present invention, described step C comprises:
If C2. from the logic processing circuit of equipment, receive write command, judge whether the address of write address and this serial bus interface chip mates, if coupling, enter write state, and, at write state, the Data Input Interface in the instruction waiting status still is set to Data Input Interface; If do not mate, enter and write service state, and, writing service state, the Data Input Interface in the instruction waiting status still is set to Data Input Interface, the data output interface in the instruction waiting status still is set to data output interface.
In universal serial bus transmission method of the present invention, described steps A comprises:
A1. from the logic processing circuit of equipment powering in idle condition and to the clock count zero clearing;
A2. in idle condition, two data interfaces are set and are input interface, monitor the clock signal of two clock interfaces and clock signal is counted respectively;
A3. judge respectively whether clock count arrives setting threshold, if perform step A4; If not, repeated execution of steps A3;
A4. determine the Serial Control direction according to following methods: at first clock count is arrived to the corresponding data-interface of clock interface of setting threshold as input interface, using another data-interface as output interface.
In universal serial bus transmission method of the present invention, described step B comprises:
If B1. described logic processing circuit is received the address issuing command, start to monitor clock signal;
If B2. after receiving i clock signal, the level of input interface converts, i be natural number and to this serial bus interface chip all the series connection sequence number from the serial bus interface chip of equipment is relevant, determine the address that i is this serial bus interface chip;
B3. the relation with the sequence number of connecting according to next serial bus interface chip, control output interface output level figure signal after corresponding clock signal.
Implement technical scheme of the present invention, do not need to set mailing address for each serial bus interface chip specially, after having determined the Serial Control direction, just can realize the dynamic address coding, therefore from equipment itself, do not need special address that circuit is set, thereby reduced the cost of serial bus transmission system.
The accompanying drawing explanation
Below in conjunction with drawings and Examples, the invention will be further described, in accompanying drawing:
Fig. 1 is the logical diagram of serial bus transmission system embodiment mono-of the present invention;
Fig. 2 is the logical diagram of serial bus interface chip embodiment mono-of the present invention;
Fig. 3 is the process flow diagram of universal serial bus transmission method embodiment mono-of the present invention;
Fig. 4 is the process flow diagram of universal serial bus transmission method embodiment bis-of the present invention;
The logical diagram of seven kinds of states that Fig. 5 A-Fig. 5 G is serial bus transmission system of the present invention.
Embodiment
Fig. 1 is the logical diagram of serial bus transmission system embodiment mono-of the present invention, this serial bus transmission system comprises main equipment and a plurality of from equipment 1,2,3 (only showing three figure), each from equipment comprise electrical connection from equipment controlled device and serial bus interface chip.The universal serial bus that main equipment forms by two signal wires has been connected a plurality of from equipment, and one is data signal line, and one is clock cable.That is, main equipment is connected with the serial bus interface chip from equipment 1 by data signal line; From the serial bus interface chip of equipment 1, by data signal line, with the serial bus interface chip from equipment 2, be connected, the like.Simultaneously, main equipment is by clock cable for from equipment 1, providing clock signal, and each provides clock signal for what the next one was connected from equipment from equipment by clock cable.Each chip of the serial bus interface from equipment Monitoring and Controlling order, in service state, need to provide for the chip of the serial bus interface from equipment of next series connection with it the service of transparent left biography or right biography according to detected control command.Like this, main equipment can carry out read-write operation or each is controlled accordingly and monitor from equipment each data from necessity of equipment.
Fig. 2 is the logical diagram of serial bus interface chip embodiment mono-of the present invention, this serial bus interface chip comprises bus interface circuit and the logic processing circuit of electrical connection, wherein, bus interface circuit comprises two bi-directional data interfaces and two bidirectional clock interfaces corresponding with each data-interface respectively, two data interfaces are respectively the first data-interface, the second data-interface, and two clock interfaces are respectively the first clock interface, second clock interface.A plurality of different between equipment, rear first data-interface from equipment is connected with previous the second data-interface from equipment, and first first data-interface from equipment is connected with main equipment, and last is unsettled from the second data-interface of equipment.In addition, a plurality of different between equipment, rear first clock interface from equipment is connected with the previous interface of the second clock from equipment, and first first clock interface from equipment is connected with main equipment, and last interface of the second clock from equipment is unsettled.And, only need a signal wire between the first data-interface and the second data-interface, and be all bidirectional interface.The control of the first data-interface and the second data-interface receive logic treatment circuit realize a left side pass on Gong can and the right side energy of passing on Gong.Only need a signal wire between the first clock interface and second clock interface, and be all bidirectional interface.First, second clock interface receive clock signal, so that logic processing circuit can be from outside receive clock signal.
The Serial Control direction is determined in logic processing circuit level upset according to two data interfaces or two clock interfaces after powering on, and, determines that each data-interface and clock interface are respectively input interface or output interface, then entry instruction waiting status that is.For example, in an example, logic processing circuit after powering in idle condition and to the clock count zero clearing, and, in idle condition, two data interfaces are set and are input interface, monitor clock signal also according to the counting of clock signal is determined to the Serial Control direction, , determine that each data-interface and clock interface are respectively input interface or output interface, can determine by the following method the Serial Control direction: at first clock count is arrived to the corresponding data-interface of clock interface of setting threshold as input interface, using another data-interface as output interface, the clock interface corresponding with Data Input Interface is the clock input interface, the clock interface corresponding with data output interface is the clock output interface.Entry instruction waiting status after having determined the Serial Control direction; Certainly, it is more than a specific embodiment of the present invention, logic processing circuit also can be determined the Serial Control direction according to two data interface level upsets after powering on, for example, at first the data-interface of level upset or data-interface that level upset number of times reaches preset times occur is input interface, another data-interface is output interface, then correspondingly determines the direction of two clock interfaces.
If described logic processing circuit is received the address issuing command, from input interface receiver address signal, and producing new address signal, this new address signal guarantees unique in serial bus transmission system, and described new address signal is exported by output interface.For example, in a specific embodiment, if described logic processing circuit is received the address issuing command, start to monitor clock signal, and, if the level of input interface converts after receiving i clock signal, i be natural number and to this serial bus interface chip all the series connection sequence number from the serial bus interface chip of equipment is relevant, determine the address that i is this serial bus interface chip, simultaneously, relation according to next serial bus interface chip with the sequence number of connecting, control output interface output level figure signal after corresponding clock signal.In an example, can set from the address of the serial bus interface chip of equipment and be the series connection sequence number, now, first chip of serial bus interface from equipment is receiving the 1st clock signal, the level of its input interface (for example, the first data-interface) converts (for example,, by high level step-down level), now, can determine that this first be 1 from the address of the serial bus interface chip of equipment.Then, the output interface of first chip of serial bus interface from equipment (for example, the second data-interface) under the control of its logic processing circuit, after the 2nd clock signal, the output level figure signal (for example, by high level step-down level), correspondingly, second chip of the serial bus interface from equipment is receiving the 2nd clock signal, its input interface (the first data-interface for example, this first data-interface is connected with first second data-interface from equipment) level (for example convert, by high level step-down level), now, the address that can determine this second chip of the serial bus interface from equipment is 2, the like, can determine successively the address of the follow-up chip of the serial bus interface from equipment.Certainly, in other embodiments, from the address of the serial bus interface chip of equipment, with the relation of the sequence number of connecting of this serial bus interface chip, also can be linear function relation or other man-to-man relation.It should be noted that equally, it is more than a specific embodiment of the present invention, certainly, the input interface of serial bus interface chip is direct receiver address signal also, and this address and this serial bus interface chip are all the sequence number of connecting from the serial bus interface chip of equipment is uncorrelated.
Implement above technical scheme, do not need to set mailing address for each serial bus interface chip specially, after having determined the Serial Control direction, can be according to each chip of the serial bus interface from equipment the series connection sequence number the whole chip of the serial bus interface from equipment, just can realize the dynamic address coding, , " series sequence " of each serial bus interface chip is equivalent to mailing address, be that main control equipment is in strict accordance with the series sequence from equipment, carry out singly data read-write operation, therefore from equipment itself, do not need special address that circuit is set, thereby reduced the cost of serial bus transmission system.
If logic processing circuit is received steering order, two data interfaces convert transmission direction according to steering order, and two clock interfaces keep the clock transfer direction constant after definite Serial Control direction.
For example, if receiving, logic processing circuit reads instruction, whether mate the address that judges reading address and this serial bus interface chip, if coupling, enter the state of reading, and, reading state, by the input interface in the instruction waiting status (for example, the first data-interface) be set to output interface, the local data that this first data-interface output is read, entry instruction waiting status after reading continuously some Bit datas, in the instruction waiting status, former input interface (the first data-interface) is still input interface, former output interface (the second data-interface) is still output interface, the data of output interface input and output interfaces, be about to control command or data and be delivered to next serial bus interface chip by " right biography passage ".
If receiving, logic processing circuit reads instruction, and does not mate the address of judgement reading address and this serial bus interface chip, enter and read service state, and, reading service state, the input interface in the instruction waiting status is set to output interface, and the output interface in the instruction waiting status is set to input interface, now, the data that this serial bus interface chip is responsible for next serial bus interface chip is read are delivered to previous serial bus interface chip by left biography passage.
Again for example, if described logic processing circuit is received write command, whether mate the address that judges write address and this serial bus interface chip, if coupling, enter write state, and, at write state, input interface in the instruction waiting status (for example, the first data-interface) still is set to input interface, starts to write Bit data to this from equipment.Then, the entry instruction waiting status, in the instruction waiting status, former input interface (the first data-interface) is still input interface, former output interface (the second data-interface) is still output interface, the data of output interface input and output interfaces, be about to control command or data and be delivered to next serial bus interface chip by " right biography passage ".In addition, also it should be noted that, be more than one embodiment of the present of invention, in other embodiments, at write state, the input interface in the instruction waiting status (for example, the first data-interface) still is set to input interface, output interface in the instruction waiting status (for example, the second data-interface) is set to output interface.
If described logic processing circuit is received write command, and does not mate the address of judgement write address and this serial bus interface chip, enter and write service state, and, writing service state, input interface in the instruction waiting status (the first data-interface) still is set to input interface, the output interface in the instruction waiting status (the second data-interface) still is set to output interface, continue the data that will write to the transmission of next serial bus interface chip by right biography passage.
The like, when a plurality of serial bus interface chips are arranged or comprise the serial bus interface chip from equipment the time, can according to series sequence identify each serial bus interface chip or comprise the serial bus interface chip from equipment, and complete the read-write operation of data or the transmission of steering order.
Finally, also it should be noted that, the clock signal that logic processing circuit can't receive specific quantity under any state just enters idle condition, or enters idle condition by the reception order.Read states, read service state, write state, write service state and address issued state, be referred to as duty, after finishing in working order, the serial bus interface chip is got back to the instruction waiting status automatically.
In addition, because the read-write control interface is bi-directional signal interface, interface as this locality storage or control system, can with storer (such as PROM ROM etc.) be electrically connected to, complete the chip functions expansion, storer can be used as the external memorizer access chip, also can be encapsulated in the serial bus interface chip as storing on sheet.
Fig. 3 is the process flow diagram of universal serial bus transmission method embodiment mono-of the present invention, and this universal serial bus transmission method comprises:
A. determine the Serial Control direction from logic processing circuit level upset according to described two data interfaces or described two clock interfaces powering on of equipment,, determine that each data-interface and clock interface are respectively input interface or output interface, then entry instruction waiting status;
If B. described logic processing circuit is received the address issuing command, from input interface receiver address signal, and produce new address signal, and by the output of described new address signal, this new address signal guarantees unique in serial bus transmission system.
After steps A, also comprise:
If C. from the logic processing circuit of equipment, receive steering order, described two data interfaces convert transmission direction according to steering order, and described two clock interfaces keep the clock transfer direction constant after definite Serial Control direction.Preferably, steps A specifically comprises:
A1. from the logic processing circuit of equipment powering in idle condition and to the clock count zero clearing;
A2. in idle condition, two data interfaces are set and are input interface, monitor the clock signal of two clock interfaces and clock signal is counted respectively;
A3. judge respectively whether clock count arrives setting threshold, if perform step A4; If not, repeated execution of steps A3;
A4. determine the Serial Control direction according to following methods: at first clock count is arrived to the corresponding data-interface of clock interface of setting threshold as input interface, using another data-interface as output interface.
Preferably, step B specifically comprises:
If B1. described logic processing circuit is received the address issuing command, start to monitor clock signal;
If B2. after receiving i clock signal, the level of input interface converts, i be natural number and to this serial bus interface chip all the series connection sequence number from the serial bus interface chip of equipment is relevant, determine the address that i is this serial bus interface chip;
B3. the relation with the sequence number of connecting according to next serial bus interface chip, control output interface output level figure signal after corresponding clock signal.
Fig. 4 is the process flow diagram of universal serial bus transmission method embodiment bis-of the present invention, at first explanation is, the control command that logic processing circuit receives comprises: read instruction (CMD_RD), write command (CMD_WR) and distribute address command (CMD_ADD), and logic processing circuit can be realized the control of following logic state:
1) IDLE (idle condition): in conjunction with Fig. 5 A, the first data-interface is input state, and the second data-interface is input, and the first clock interface is input state, and the second clock interface is input state, and the wait clock count is determined the Serial Control direction;
2) WAIT (instruction waiting status): in conjunction with Fig. 5 B, the first data-interface is input state, the second data-interface is output state, the first clock interface is input state, the second clock interface is output state, waits for serial CMD_RD, CMD_WR or the CMD_ADD order of the first data-interface;
3) READ (reading state): if need read the data of second serial bus interface chip, in conjunction with Fig. 5 C, the first data-interface of this second serial bus interface chip is output state, the second data-interface input state, the first clock interface is input state, the second clock interface is output state,, the data that read every 1 clock signal (CLK) output 1bit this locality;
4) WRITE (write state): if need be to second serial bus interface chip data writing, in conjunction with Fig. 5 D, the first data-interface of this second serial bus interface chip is input state, the second data-interface is output state, the first clock interface is input state, the second clock interface is output state, and every 1 clock signal (CLK) writes the data of local 1bit;
5) RS (reading service state): if need read the data of second serial bus interface chip, in conjunction with Fig. 5 E, the first data-interface of other dual serial Bus Interface Chip is output state, the second data-interface is input state, the second data-interface is by the first data-interface output, the first clock interface is input state, and the second clock interface is output state;
6) WS (writing service state): if need be to second serial bus interface chip data writing, in conjunction with Fig. 5 F, the first data-interface of other dual serial Bus Interface Chip is input state, the second data-interface is output state, the first data-interface is by the second data-interface output, the first clock interface is input state, and the second clock interface is output state;
7) ADD (distribution address): in conjunction with Fig. 5 G, the first data-interface is input state, the second data-interface is output state, the first clock interface is input state, the second clock interface is output state, and the first data-interface is by the second data-interface output, i clock receive address command this chip address be n, and chip is clockwise the second data-interface OPADD order when the next one, for next chip distributes address.
From the logic processing circuit of equipment powering in idle condition and to the clock count zero clearing, in idle condition, wait for that clock count judges the Serial Control direction, entry instruction waiting state after direction determining is complete.
If receive and read instruction in the instruction waiting state, and matching addresses enters the state of reading, otherwise enter, reads service state, entry instruction waiting state at read states or after reading service state and finishing.And, reading state, the input interface in the instruction waiting status is set to output interface.Reading service state, the input interface in the instruction waiting status is set to output interface, and the output interface in the instruction waiting status is set to input interface.
If receive write command in the instruction waiting state, and matching addresses enters the state of writing, otherwise enter, writes service state, writing state or writing service state finish after the entry instruction waiting state.And, at write state, the input interface in the instruction waiting status still is set to input interface.Writing service state, the input interface in the instruction waiting status still is being set to input interface, the output interface in the instruction waiting status still is being set to output interface.
If receive the address issuing command in the instruction waiting state, enter the address issued state, after finishing, the address issue gets back to the instruction waiting status.In the issued state of address, if the level of input interface converts after receiving i clock signal, i be natural number and to this serial bus interface chip all the series connection sequence number from the serial bus interface chip of equipment is relevant, determine the address that i is this serial bus interface chip, simultaneously, relation according to next serial bus interface chip with the sequence number of connecting, control output interface output level figure signal after corresponding clock signal.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various changes, combination and variation.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in claim scope of the present invention.
Claims (12)
1. a serial bus interface chip, with from the equipment controlled device, be connected, it is characterized in that, described serial bus interface chip comprises bus interface circuit and the logic processing circuit of electrical connection, described bus interface circuit comprises two bi-directional data interfaces and two bidirectional clock interfaces corresponding with each data-interface respectively, and
The Serial Control direction is determined in the level upset according to described two data interfaces or described two clock interfaces after powering on of described logic processing circuit,, determine that each data-interface and clock interface are respectively input interface or output interface, then entry instruction waiting status;
If described logic processing circuit is received the address issuing command, from input interface receiver address signal, and produce new address signal, and by described new address signal output.
2. serial bus interface chip according to claim 1, it is characterized in that, if described logic processing circuit is received steering order, described two data interfaces convert transmission direction according to steering order, and described two clock interfaces keep the clock transfer direction constant after definite Serial Control direction.
3. serial bus interface chip according to claim 2, is characterized in that,
Read instruction if described logic processing circuit is received, judge whether the address of reading address and this serial bus interface chip mates, if coupling, enter the state of reading, and, reading state, the Data Input Interface in the instruction waiting status is set to data output interface; If do not mate, enter and read service state, and, reading service state, the Data Input Interface in the instruction waiting status is set to data output interface, and the data output interface in the instruction waiting status is set to Data Input Interface.
4. serial bus interface chip according to claim 2, is characterized in that,
If described logic processing circuit is received write command, judge whether the address of write address and this serial bus interface chip mates, if coupling, enter write state, and, at write state, the Data Input Interface in the instruction waiting status still is set to Data Input Interface; If do not mate, enter and write service state, and, writing service state, the Data Input Interface in the instruction waiting status still is set to Data Input Interface, the data output interface in the instruction waiting status still is set to data output interface.
5. serial bus interface chip according to claim 1, is characterized in that, described serial bus interface built-in chip type or external memorizer.
6. a serial bus transmission system, comprise main equipment and a plurality of from equipment, each includes from the equipment controlled device from equipment, it is characterized in that, describedly from equipment, also comprise the described serial bus interface chip of claim 1-5 any one, described serial bus interface chip is connected from the equipment controlled device with described, and, if under the particular serial Bus Interface Chip from equipment be non-first from equipment also non-last from equipment, the first data-interface of this serial bus interface chip is connected with the second data-interface of the previous chip of the serial bus interface from equipment, the first clock interface of this serial bus interface chip is connected with the second clock interface of the previous chip of the serial bus interface from equipment, if under the particular serial Bus Interface Chip from equipment be first from equipment, the first data-interface of this serial bus interface chip is connected with main equipment, the first clock interface of this serial bus interface chip is connected with main equipment, if under the particular serial Bus Interface Chip is that last is from equipment from equipment, the first data-interface of this serial bus interface chip is connected with the second data-interface of the previous chip of the serial bus interface from equipment, the first clock interface of this serial bus interface chip is connected with the second clock interface of the previous chip of the serial bus interface from equipment, and the second data-interface, the second clock interface of this serial bus interface chip are unsettled.
7. a universal serial bus transmission method, is characterized in that, comprising:
A. determine the Serial Control direction from logic processing circuit level upset according to described two data interfaces or described two clock interfaces powering on of equipment,, determine that each data-interface and clock interface are respectively input interface or output interface, then entry instruction waiting status;
If B. described logic processing circuit is received the address issuing command, from input interface receiver address signal, and produce new address signal, and by described new address signal output.
8. universal serial bus transmission method according to claim 7, is characterized in that, after described steps A, also comprises:
If C. from the logic processing circuit of equipment, receive steering order, described two data interfaces convert transmission direction according to steering order, and described two clock interfaces keep the clock transfer direction constant after definite Serial Control direction.
9. universal serial bus transmission method according to claim 8, is characterized in that, described step C comprises:
If C1. from the logic processing circuit of equipment, receive and read instruction, judge whether the address of reading address and this serial bus interface chip mates, if coupling, enter the state of reading, and, reading state, the Data Input Interface in the instruction waiting status is set to data output interface; If do not mate, enter and read service state, and, reading service state, the Data Input Interface in the instruction waiting status is set to data output interface, and the data output interface in the instruction waiting status is set to Data Input Interface.
10. universal serial bus transmission method according to claim 6, is characterized in that, described step C comprises:
If C2. from the logic processing circuit of equipment, receive write command, judge whether the address of write address and this serial bus interface chip mates, if coupling, enter write state, and, at write state, the Data Input Interface in the instruction waiting status still is set to Data Input Interface; If do not mate, enter and write service state, and, writing service state, the Data Input Interface in the instruction waiting status still is set to Data Input Interface, the data output interface in the instruction waiting status still is set to data output interface.
11. universal serial bus transmission method according to claim 6, is characterized in that, described steps A comprises:
A1. from the logic processing circuit of equipment powering in idle condition and to the clock count zero clearing;
A2. in idle condition, two data interfaces are set and are input interface, monitor the clock signal of two clock interfaces and clock signal is counted respectively;
A3. judge respectively whether clock count arrives setting threshold, if perform step A4; If not, repeated execution of steps A3;
A4. determine the Serial Control direction according to following methods: at first clock count is arrived to the corresponding data-interface of clock interface of setting threshold as input interface, using another data-interface as output interface.
12. universal serial bus transmission method according to claim 7, is characterized in that, described step B comprises:
If B1. described logic processing circuit is received the address issuing command, start to monitor clock signal;
If B2. after receiving i clock signal, the level of input interface converts, i be natural number and to this serial bus interface chip all the series connection sequence number from the serial bus interface chip of equipment is relevant, determine the address that i is this serial bus interface chip;
B3. the relation with the sequence number of connecting according to next serial bus interface chip, control output interface output level figure signal after corresponding clock signal.
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| CN201310414135.8A CN103500154B (en) | 2013-09-11 | 2013-09-11 | A kind of serial bus interface chip, serial bus transmission system and method |
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| CN104834618A (en) * | 2015-04-03 | 2015-08-12 | 深圳市美贝壳科技有限公司 | Multi-equipment scanning method based on RS485 bus communication and power electronic system |
| CN104881382A (en) * | 2015-06-15 | 2015-09-02 | 刘晓辉 | Master and slave equipment connection device and address recognition method thereof |
| CN106210389A (en) * | 2015-05-29 | 2016-12-07 | 佳能株式会社 | Messaging device and control method thereof |
| CN107256198A (en) * | 2017-05-26 | 2017-10-17 | 郑州云海信息技术有限公司 | Server and the method for server hard disc board distribution I2C addresses |
| CN108027797A (en) * | 2015-09-21 | 2018-05-11 | 高通股份有限公司 | Enhanced serial peripheral interface |
| CN108270883A (en) * | 2018-02-02 | 2018-07-10 | 深圳曼顿科技有限公司 | Can automatic dispensing device address code method, breaker and storage medium |
| CN109218152A (en) * | 2018-07-19 | 2019-01-15 | 精华隆智慧感知科技（深圳）股份有限公司 | A kind of equipment automatic recognition system |
| CN110059030A (en) * | 2019-04-23 | 2019-07-26 | 南京天数智芯科技有限公司 | A kind of data transmission system and method based on UART serial loop network |
| CN112965926A (en) * | 2021-03-05 | 2021-06-15 | 张玉禄 | SPI interface safety chip and SPI interface electron device |
| CN117331882A (en) * | 2023-12-01 | 2024-01-02 | 深圳比特微电子科技有限公司 | Chip configuration method and device of chip board, server, electronic equipment and medium |
| CN112965926B (en) * | 2021-03-05 | 2024-04-30 | 张玉禄 | SPI interface safety chip and SPI interface electronic device |
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| CN108270883A (en) * | 2018-02-02 | 2018-07-10 | 深圳曼顿科技有限公司 | Can automatic dispensing device address code method, breaker and storage medium |
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| CN109218152A (en) * | 2018-07-19 | 2019-01-15 | 精华隆智慧感知科技（深圳）股份有限公司 | A kind of equipment automatic recognition system |
| CN110059030A (en) * | 2019-04-23 | 2019-07-26 | 南京天数智芯科技有限公司 | A kind of data transmission system and method based on UART serial loop network |
| CN112965926A (en) * | 2021-03-05 | 2021-06-15 | 张玉禄 | SPI interface safety chip and SPI interface electron device |
| CN112965926B (en) * | 2021-03-05 | 2024-04-30 | 张玉禄 | SPI interface safety chip and SPI interface electronic device |
| CN117331882A (en) * | 2023-12-01 | 2024-01-02 | 深圳比特微电子科技有限公司 | Chip configuration method and device of chip board, server, electronic equipment and medium |
| CN117331882B (en) * | 2023-12-01 | 2024-03-29 | 深圳比特微电子科技有限公司 | Chip configuration method and device of chip board, server, electronic equipment and medium |
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