CN113075904A

CN113075904A - PLC extension system, PLC system communication method and storage medium

Info

Publication number: CN113075904A
Application number: CN202110303370.2A
Authority: CN
Inventors: 曾红勇; 刘涛
Original assignee: Shenzhen Invt Electric Co Ltd
Current assignee: Shenzhen Invt Electric Co Ltd
Priority date: 2021-03-22
Filing date: 2021-03-22
Publication date: 2021-07-06

Abstract

The embodiment of the invention provides a PLC expansion system, a PLC system communication method and a storage medium, which are used for realizing the expansion of a PLC system, reducing the circuit complexity and saving the hardware cost. The PLC extension system in the embodiment of the invention comprises: the main module and at least one CPLD complex programmable logic device; the main module and the at least one CPLD are cascaded by adopting an expansion bus; the main module comprises a microprocessor and a programmable logic gate array device; the programmable logic gate array device is used for loading programming data and realizing the logic function corresponding to the programming data; the microprocessor is used for outputting an addressing signal and controlling the main module to communicate with the at least one CPLD; the at least one CPLD receives the addressing signals in sequence based on the expansion bus; after receiving the addressing signal, each CPLD behind the first-stage CPLD increases a preset numerical value on the address of the last-stage CPLD to generate the address of the CPLD.

Description

PLC extension system, PLC system communication method and storage medium

Technical Field

The invention relates to the technical field of automation control, in particular to a PLC (programmable logic controller) expansion system, a PLC system communication method and a storage medium.

Background

A PLC (Programmable Logic Controller) plays an important role in the entire system as a control layer of an industrial automation device. With the increase of control objects and the increasing complexity of the process, the realization of such a plurality of control tasks by only depending on the small-sized PLC body is difficult to realize, so the development of the PLC extension module is particularly important.

In the existing PLC extension scheme, a hardware decoding circuit needs to be provided for each extension module, each extension module is connected to the hardware decoding circuit through an address line, and an address of each extension module is allocated through at least one hardware decoding circuit. Therefore, the existing PLC extension scheme needs to provide at least one hardware decoding circuit, which increases circuit complexity and hardware cost.

Disclosure of Invention

The embodiment of the invention provides a PLC expansion system, a PLC system communication method and a storage medium, which are used for realizing the expansion of a PLC system, reducing the circuit complexity and saving the hardware cost.

A first aspect of an embodiment of the present invention provides a PLC extension system, which may include:

the main module and at least one CPLD complex programmable logic device; wherein the content of the first and second substances,

the main module and the at least one CPLD are connected in a cascade mode through an expansion bus;

the main module comprises a microprocessor and a programmable logic gate array device;

the programmable logic gate array device is used for loading programming data and realizing the logic function corresponding to the programming data;

the microprocessor is used for outputting an addressing signal and controlling the main module to communicate with the at least one CPLD;

the at least one CPLD receives the addressing signals in sequence based on the expansion bus;

after receiving the addressing signal, each CPLD behind the first-stage CPLD increases a preset numerical value on the address of the last-stage CPLD to generate the address of the CPLD.

Optionally, as a possible implementation manner, in an embodiment of the present application, the programmable gate array device is an FPGA field programmable gate array.

Optionally, as a possible implementation manner, in the embodiment of the present application, the programmable gate array device includes two cascaded CPLDs.

A second aspect of an embodiment of the present invention provides a PLC system communication method, which may include:

outputting a communication request signal containing a destination address so that the CPLD receiving the communication request signal determines a target CPLD consistent with the destination address;

and reading a response signal of the target CPLD to the communication request signal.

Optionally, as a possible implementation manner, in an embodiment of the present invention, outputting a communication request signal including a destination address includes:

and outputting a communication request signal containing the destination address as an I/O port configuration inquiry signal so as to acquire the I/O port configuration information of the target CPLD.

the communication request signal including the destination address is output as a data write signal to write data into the target CPLD.

Optionally, as a possible implementation manner, in the embodiment of the present invention, reading a response signal of the target CPLD to the communication request signal includes:

when the state of the first class port of the target CPLD is detected to be in a response state, reading a state value of a second class port of the target CPLD based on an expansion bus, and generating response data according to the state value of the second class port; the first port is a data port for controlling signal transmission, and the second port is a data port for communication data transmission.

Optionally, as a possible implementation manner, in the embodiment of the present invention, the number of the first type ports is one or more.

Optionally, as a possible implementation manner, in an embodiment of the present invention, the number of the second type ports is one or more.

A third aspect of embodiments of the present invention provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps in any one of the possible implementations of the first aspect and the first aspect.

According to the technical scheme, the embodiment of the invention has the following advantages:

according to the PLC expansion system, each expanded CPLD can sequentially receive an addressing signal based on an expansion bus, then the address of the previous CPLD is obtained, and a preset numerical value is added to the address of the previous CPLD to generate the address of the expanded CPLD. Compared with the prior art, the method and the device have the advantages that the independent hardware decoding circuit connection and address lines are not needed, the circuit complexity is reduced, and the hardware cost is saved.

Drawings

Fig. 1 is a schematic diagram of an embodiment of a PLC extension system according to an embodiment of the present invention;

fig. 2 is a schematic diagram of an embodiment of a PLC system communication method according to an embodiment of the present invention;

fig. 3 is a schematic diagram of an embodiment of a PLC expansion system according to an embodiment of the present invention.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments described herein are capable of operation in other sequences than described or illustrated herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

For convenience of understanding, a specific flow in the embodiment of the present invention is described below, and referring to fig. 1, an embodiment of a PLC extension system in the embodiment of the present invention may include: a main module 10 and at least one CPLD (complex programmable logic device); wherein the content of the first and second substances,

the main module 10 and the at least one CPLD are connected in cascade by using an expansion bus;

the main module 10 includes a microprocessor 101 and a programmable gate array device 102;

the programmable gate array device 102 is configured to load programming data and implement a logic function corresponding to the programming data;

and the microprocessor 101 is used for outputting an addressing signal and controlling the main module to communicate with each CPLD.

After the PLC extension system is powered on, the microprocessor can execute a preset program to output an addressing signal. Each CPLD cascaded with the master module may receive the addressing signal in turn based on the expansion bus and respond to the addressing signal. Specifically, after each CPLD behind the first CPLD receives the addressing signal, the address of the last CPLD may be obtained, and a preset value is added to the address of the last CPLD to generate its own address. The first-stage CPLD is the CPLD electrically connected with the microprocessor and nearest, and the other expanded CPLDs are cascaded with the first-stage CPLD in sequence. The address of the first stage CPLD may be received directly from the master module.

Optionally, as a possible implementation manner, the programmable gate array device 102 in this application may be an FPGA (field programmable gate array), or may be a device formed by cascading two or more CPLDs, and is not limited herein.

Referring to fig. 2, a communication process between the main module and each CPLD in the PLC expansion system will be described. An embodiment of a PLC system communication method in the present application may include:

s201, controlling the microprocessor to output a communication request signal containing a destination address, so that the CPLD receiving the communication request signal determines a target CPLD consistent with the destination address;

in the PLC extended system in the embodiment shown in fig. 1, the microprocessor may run a preset computer program to output a communication request signal including a destination address. The communication request signal may be transmitted on the expansion bus, and the CPLD that receives the communication request signal may compare whether its own address coincides with the destination address, and if so, may determine that it is the target CPLD, and respond to the communication request signal. And if the two CPLDs are not consistent, the communication request signal is not responded, and the communication request signal is continuously transmitted to the CPLD of the subsequent cascade.

Optionally, as a possible implementation manner, the communication request signal output by the microprocessor and containing the destination address may be an I/O port configuration query signal to obtain the I/O port configuration information of the target CPLD.

Alternatively, as a possible implementation, the communication request signal output by the microprocessor and containing the destination address may be a data write signal to write data into the target CPLD.

S202, receives a response signal of the target CPLD to the communication request signal.

After receiving the communication request signal, the target CPLD may process the communication request signal according to a preset service processing logic to generate a response signal, or read the response signal from the outside, and transmit the response signal to the microprocessor through the expansion bus.

Optionally, as a possible implementation manner, after the target CPLD acquires the reply signal, the state of the port where the target CPLD is connected to the expansion bus may be set to be a reply state, so as to instruct the microprocessor to read data; and when the state of the first class port of the target CPLD is detected to be in a response state, reading the state value of the second class port of the target CPLD based on the expansion bus, and generating response data according to the state value of the second class port. The first type of port is a data port for controlling signal transmission, and the second type of port is a data port for communication data transmission. The number of the first type of ports and the second type of ports is one or more, for example, when the expansion bus is a bidirectional 8-bit data line, an 8-bit data port, a 5-bit control signal port, a reset signal port, and a power supply port may be set, and the specific number of the first type of ports and the second type of ports may be reasonably set according to actual requirements, which is not limited herein.

The communication between the expansion module and the main CPU in the embodiment adopts the parallel two-phase data bus and the control signal combination logic matching and communication mode, compared with the traditional SPI (serial peripheral interface) master-slave time sequence communication architecture, the access polling rate is obviously increased, the data verification fault tolerance is enhanced, and the cost of the whole hardware circuit is reduced. Because the communication between the expansion modules only relates to the communication between the adjacent expansion modules, the interference of impedance matching, high-power cable coupling, radiation and the like caused by overlong signal lines is avoided.

For ease of understanding, referring to fig. 3, a PLC system communication method in the present application will be described with reference to a specific application example.

As shown in fig. 3, in the PLC expansion system, each expansion module (CPLD) is provided with two bus interfaces, a bus interface 1 is connected to a bus interface 2 of a previous expansion module or a CPU module, and the bus interface 2 is connected to a bus interface 1 of a next expansion module, so as to form a one-by-one cascaded bus mode.

The bus in this embodiment is an 8-bit bidirectional DATA bus, and the bus interface includes DATA ports AD (0) to AD (7) on the DATA line, control signal lines (S1, S2, S3, S4, ACK), a power line, and a reset signal line (RST). Under the action of the control signal line, the on-off state of the input points of each expansion module or the analog signal value can be collected based on the bus and sent to a microprocessor (CPU), and meanwhile, the processing result (the state of the expansion output point and the analog output) of the main program in the microprocessor is sent back to the post-stage expansion module.

The communication transactions of the CPU and the CPLD in this embodiment are divided into three types: the CPU controls the CPLD to carry out addressing operation; the CPU inquires the I/O point configuration information of the common CPLD; the CPU writes the output information into the output port of the common CPLD and the special analog expansion, and reads the input port state of the common CPLD and the special analog expansion sampling value. Three communication transactions will be described separately below.

Firstly, a CPU controls a CPLD to carry out addressing operation;

after the PLC extension system is powered on, the CPU can execute the module addressing function. The CPU controls three signal lines of RESET, S2 and S3 to be simultaneously set to be high level, and S1 is set to be low level. After each CPLD after the first stage CPLD receives the addressing signal, the DATA [0:7] signal line DATA (address of the last stage CPLD) input by the previous CPLD can be acquired, and a preset value is added (for example, increased by 1) to the address of the last stage CPLD to generate the address of the CPLD. Then, the address of the CPLD is output to the port of the expansion bus output side of the CPLD, and the CPLD at the next stage also performs the same operation until all the CPLDs obtain different address data. When the S2 signal changes from high to low, each CPLD latches its own address data. In the subsequent communication, the CPLD serving as the expansion module responds only to the information addressed to the same address as the local address, and the remaining information does not respond.

Secondly, the CPU inquires the I/O point configuration information of the common CPLD;

1) and only after the addressing operation of the CPLD is finished, normal query configuration operation can be carried out, otherwise, the CPLD cannot respond.

2) During query operation, signal lines such as RST and S2 should be ensured to be low level, and for a common expansion module, a signal line of S1 is low level; for the particular expansion block, the S1 signal line is high.

3) The rising edge of the signal from low to high, S3, indicates the start of the information frame, and the CPLD makes a decision on the signal on the DATA line as the information frame DATA byte at each falling edge of the signal S4. The meaning of each data byte in the information frame is shown in table 1 below. The data of bytes No. 1 and No. 2 are fixed flag data, for example, AAH and 55H, respectively, and the data of byte No. 3 is address data. After reading the information frame, the CPLD serving as the expansion module needs to check whether the data of the byte 1 and the byte 2 are the preset flag data, after the check is passed, it is determined whether the address data in the information frame is consistent with the address data stored locally, and if so, the subsequent processing is performed.

4) And the data CMD with the number 4 byte is a command byte, the data 4H is the query configuration of a common module, the data 8H is the I/O read-write of the common module, and if the data is illegal command information, the subsequent information frame is stopped to be received.

5) And the data 'CHKSUM' of the No. 5 byte is a check byte, and the byte is '0 BFH' when the configuration is inquired by adopting an exclusive or check method; data of byte No. 6 is represented as receiving-transmitting switching transition byte, and is an invalid field; ". x" is an end mark field.

6) And the falling edge of the S3 signal from high to low indicates that the CPU information frame is sent completely, and the CPU gives the control right of the data bus to the CPLD and waits for the response of the CPLD.

7) And adjusting time for the CPLD DATA bus direction in the first clock period when the selected target CPLD obtains the control right, switching the output port of the DATA line into the input port, and switching the original input port into the output port, thereby avoiding the short circuit of the DATA line ports between the cascaded CPLDs.

8) And the target CPLD pulls the ACK signal line low to indicate that response is started, simultaneously puts the configuration information CONFIG of the response on the DATA bus, maintains the state of the DATA bus, waits for the CPU to read the DATA on the DATA DATA line, and analyzes the CONFIG DATA according to a preset rule to obtain the response DATA of the target CPLD.

9) And when the target CPLD obtains the third rising edge moment of S4 of the control right, releasing the ACK response line to become high level, indicating that the response is finished and the query operation is finished.

10) And the CPU performs inquiry operation on one CPLD each time, and the inquiry operation is performed in sequence until the inquiry on all the chips is completed.

TABLE 1

And thirdly, the CPU writes the output information into an output port of the common CPLD and reads the state of an input port of the common CPLD.

1) Normal I/O read-write operation can be carried out only after the addressing operation of the CPLD is finished, otherwise, the CPLD cannot respond;

2) when the I/O port is read and written, signal lines such as RST, S2 and the like are ensured to be at low level, and for a common expansion module, a signal line of S1 is at low level;

3) the rising edge of the S3 signal from low to high indicates the start of the information frame, and the CPLD reads the signal on the DATA line as the information frame at the falling edge of each S4 signal, with the meaning of the individual DATA bytes in the information frame as shown in table 1 below. And (3) checking whether the data of the byte No. 1 and the byte No. 2 are preset mark data, judging whether the address data in the information frame is consistent with the locally stored address data after the data of the byte No. 1 and the byte No. 2 pass the checking, and performing subsequent processing if the address data in the information frame is consistent with the locally stored address data.

4) And the fourth data CMD of the information frame is a command byte, (for the common expansion module, "4H" is query configuration, "8H" is I/O read-write), and if the command byte is illegal command information, the subsequent information frame is stopped to be received.

5) And the fifth byte and the sixth byte of the information frame are CPU output data sections, are data written to an output port, have 16 port states, sequentially correspond to output ports 0-15 of the CPLD from low level to high level, if the number N of the output ports of the CPLD is less than 16, the first N data bits of the data sections are taken, and the rest data bits are discarded.

6) "CHKSUM" is check byte, and is the one-by-one exclusive or cumulative value of "CMD" and 2 bytes of data; the CPLD compares the byte with the accumulated value after receiving the byte, judges the correctness of the data frame, stops receiving if the byte is wrong, and does not respond in advance;

7) the falling edge of the S3 signal from high to low indicates that the CPU information frame is sent, the data master control right is handed to the target CPLD of the specified address, and the response is waited;

8) adjusting the buffer time for the direction of the bidirectional expansion data line in the first S4 period when the target CPLD obtains the control right;

9) when the target CPLD obtains the second S4 rising edge of the control right, the selected CPLD pulls the ACK signal line low to indicate that the response is started, and simultaneously, the state DATA0 of the responded input port 0 is put on the DATA line and maintained to wait for the reading of the main CPU;

10) at the third rising edge time of S4 when the C target PLD obtains the control right, putting the response DATA input port state DATA1 on the DATA line and maintaining the state, and waiting for the main CPU to read; sequentially placing data2, data3 and RCHKSUM data on the extended data bus at the subsequent 3S 4 descending edges; wherein RCHKSUM is data0 XOR data1 XOR data2 XOR data 3.

10) And releasing the ACK response signal line at the rising edge of the seventh S4 when the target CPLD obtains the control right, and indicating that the response is finished and the communication is finished.

Firstly, in the PLC expansion system of the present application, each expanded CPLD may sequentially receive an addressing signal based on an expansion bus, then obtain an address of a previous CPLD, and add a preset value to the address of the previous CPLD to generate its own address. Compared with the prior art, the method and the device have the advantages that the independent hardware decoding circuit connection and address lines are not needed, the circuit complexity is reduced, and the hardware cost is saved. And secondly, the communication between the expansion module and the main CPU adopts the parallel two-phase data bus and the control signal combination logic matching and communication mode, compared with the traditional SPI (serial peripheral interface) master-slave time sequence communication architecture, the access polling rate is obviously accelerated, the data verification fault tolerance is enhanced, and the whole hardware circuit is simple and the cost is reduced. Finally, the anti-interference capability of the long-distance communication of the multiple expansion modules is obviously superior to that of an SPI mode, because the communication between the modules only involves the communication between the adjacent modules, the interference of impedance matching, high-power cable coupling, radiation and the like caused by overlong signal lines is avoided.

The present application also provides a computer readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the steps in the PLC system communication method embodiment shown in fig. 2, such as steps 201 to 202 shown in fig. 2, can be implemented.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A PLC extension system, comprising: the main module and at least one CPLD complex programmable logic device; wherein the content of the first and second substances,

2. The PLC expansion system of claim 1, wherein the programmable gate array device is an FPGA field programmable gate array.

3. The PLC expansion system of claim 1, wherein the programmable gate array device comprises two cascaded CPLDs.

4. A PLC system communication method applied to the PLC extension system according to any one of claims 1 to 3, the method comprising:

5. The method of claim 4, wherein outputting a communication request signal containing a destination address comprises:

6. The method of claim 4, wherein outputting a communication request signal containing a destination address comprises:

7. The method according to any one of claims 4 to 6, wherein reading the reply signal of the target CPLD to the communication request signal comprises:

8. The method of claim 7, wherein the number of the first type of ports is one or more.

9. The method of claim 8, wherein the number of the second type of ports is one or more.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that: the computer program when executed by a processor implementing the steps of the method according to any one of claims 4 to 7.