Summary of the invention
Existing above-mentioned defective when in the prior art expansion module that connects step by step in the PLC being addressed, the invention provides a kind of programmable logic controller (PLC) and hard ware extension method thereof, primary module can directly conduct interviews to expansion module by simple addressing, finishes functions such as configuration querying, input and output read-write.
The technical solution adopted for the present invention to solve the technical problems is: a kind of programmable logic controller (PLC) expansion module, comprise key control unit, also comprise the address transfer unit, described address transfer unit is used for and will continues to transmit backward along the expansion bus after according to certain rule transformation from the address signal of expansion bus; At least a portion of described address signal also is sent to described key control unit by signal wire.
Expansion module of the present invention also can further comprise the Address Recognition unit, be connected in series between the input end and key control unit of described address transfer unit, be used at least a portion of described address signal is discerned, the output gating signal is to described key control unit when the described address signal of judgement is the selected signal of described expansion module.
As one embodiment of the present invention, described address transfer unit can comprise N bar input addressed line and the N bar output addressed line that is connected in series on the expansion bus, N 〉=2; Wherein, M bar input addressed line links to each other 2≤M≤N with M-1 bar output addressed line; Article 1, the input addressed line links to each other with described key control unit, is used for described address signal is sent to described key control unit.
As one embodiment of the present invention, described address transfer unit and Address Recognition unit are made of gate circuit or are integrated in CPLD or the programmable gate array, or described address transfer unit, Address Recognition unit and key control unit are integrated in CPLD or the programmable gate array.
The present invention also provides a kind of programmable logic controller (PLC) based on above-mentioned expansion module, comprises primary module, expansion bus and L the described expansion module that is connected step by step by described expansion bus and described primary module, L 〉=2; Wherein, the address signal X of described primary module output
1At least a portion output to the key control unit of first order expansion module, address signal X through the address signal line
1Address transfer unit in described first order expansion module is transformed to address signal X simultaneously
2After output to second level expansion module; When L 〉=3, the address signal X of described (h+1) level expansion module output
H+2The key control unit of at least a portion to the (h+2) level expansion module, address signal X
H+2Address transfer unit in described (h+2) level expansion module is transformed to address signal X simultaneously
(h+3)After output to (h+3) level expansion module; Wherein, 1≤h≤(L-3).
Further, also comprise the input end that is connected in series in described address transfer unit and the Address Recognition unit between the key control unit in the described expansion module, be used for described address signal X
lAt least a portion discern, when judging described address signal X
lThe output gating signal is to described key control unit during for the selected signal of described expansion module; Wherein, 1≤l≤L.
The present invention also provides a kind of hard ware extension method based on above-mentioned programmable logic controller (PLC), and this method may further comprise the steps: A1, construct a binary code sequence (q
1..., q
n, q
N+1... q
p), comprise p element that does not repeat mutually in the described sequence; A2, formation rule R makes R (q
n)=q
N+1, and R (q
p)=q
p, n≤p-1; A3 constructs described address transfer unit according to described regular R, makes that the input signal of working as described address transfer unit is q
nThe time, its output signal is q
N+1, and when its input signal be q
pThe time its output signal also be q
pDescribed address transfer unit is made of gate circuit or is integrated in CPLD or the programmable gate array.
The inventive method further comprises: construct an Address Recognition unit, make that the input signal of working as described identification circuit is q
P-1The time, scale-of-two gating signal of its output is to the key control unit of corresponding expansion module, when its input signal is non-q
P-1The time, scale-of-two shutdown signal of its output is to described key control unit; Described Address Recognition unit is made of gate circuit or is integrated in CPLD or the programmable gate array.
The inventive method further comprises: further comprise: construct a primary module output signal with by the corresponding lists of the expansion module of gating, be stored in the described primary module, be used to indicate the corresponding expansion module of described primary module gating; Wherein, first order expansion module corresponding address signal is q
P-1, n level expansion module corresponding address signal is q
P-n, L level expansion module corresponding address signal is q
1, 1<n<L.
The present invention also provides a kind of programmable logic controller (PLC), comprise primary module, communication bus and L the described expansion module that is connected step by step by described communication bus and described primary module, L 〉=2 is characterized in that: also comprise L and described expansion module address transfer unit and Address Recognition unit one to one; Described address transfer unit is used for the address signal that receives is exported after according to certain rule transformation; Described Address Recognition unit is used for described address signal is discerned, and the output gating signal is to the key control unit of corresponding expansion module when the described address signal of judgement is the selected signal of described expansion module; The input end of the described first address transfer unit links to each other with described primary module, links to each other with the key control unit of first order expansion module by the first Address Recognition unit simultaneously; The input end of described k address transfer unit links to each other with the output terminal of k-1 address transfer unit, links to each other with the key control unit of k level expansion module by k Address Recognition unit simultaneously; Wherein, 2≤k≤L.
The invention has the beneficial effects as follows: 1. can be implemented in exempting from the PLC module that links to each other step by step and address design, can support the direct visit of primary module expansion module; 2. the expansion module information processing is convenient, address signal can be used as chip selection signal and use, and can remove link immediately after address signal is cancelled; 3. primary module can be cancelled address signal at any time according to self needs, starts new link or rebuilds link, supports the real-time of expansion module visit effectively.
Embodiment
The present invention is further elaborated with specific embodiment with reference to the accompanying drawings below.
As shown in Figure 2, a kind of programmable logic controller (PLC) of the present invention (PLC) mainly comprises primary module BU, expansion bus and at least two expansion modules 1 (supposing to comprise L expansion module, L 〉=2).Wherein, expansion module 1 is connected with connected mode step by step by expansion bus and primary module BU.That piece expansion module 1 that this paper definition links to each other with primary module BU is first order expansion module, and the expansion module 1 that links to each other with described first order expansion module is second level expansion module, and the rest may be inferred.Primary module BU is responsible for the issued transaction of PLC and the execution of user program, it is by certain expansion module 1 of address signal line 14 gatings in the expansion bus, by the corresponding expansion module 1 of 15 visits of the communication bus in the expansion bus, read and write the input/output port of corresponding expansion module 1 again.
Each expansion module 1 all comprises key control unit 12, also comprises address transfer unit 11.Key control unit 12 is used to handle the order that PLC primary module BU issues, and the imput output circuit of administration extensions module self.Among the present invention, for convenience, key control unit 12 and address transfer unit 11 in the corresponding i level expansion module 1 are called i key control unit and i address transfer unit.L≥i。
As shown in Figure 2, the input end of the first address transfer unit links to each other with the output terminal of primary module BU by address signal line 14, and its input end also links to each other with the input end of first key control unit simultaneously.The output terminal of the first address transfer unit links to each other by the input end of the second address transfer unit in address signal line 14 and the second level expansion module 1 and the input end of second key control unit.The rest may be inferred, the input end of (i+1) address transfer unit of (i+1) level expansion module 1 links to each other with the output terminal of i address transfer unit and the input end of (i+1) key control unit, and its output terminal links to each other with the input end of (i+2) address transfer unit and the input end of (i+2) key control unit.Among the present invention, the address signal that address transfer unit 11 is used for autonomous module BU in the future or upper level expansion module outputs to the next stage expansion module after according to certain rule transformation.And come at least a portion in the address signal of autonomous module BU or upper level expansion module to be directly inputted to the key control unit of this module, be used for the gating key control unit, when key control unit just can be received the instruction (communication frame) of autonomous module BU and carry out respective handling by gating from communication bus 15.
Among the present invention, " master-slave communication " mode is adopted in the primary module BU of PLC and the message exchange between each expansion module 1: when primary module BU carries out read or write operation to the information in certain expansion module 1, can send address signal by address signal line 14 to the expansion module 1 of appointment earlier, send communication frames by communication bus 15 then; Each expansion module 1 judges according to the address signal that receives whether oneself is selected, and selected expansion module 1 carries out respective handling according to the content of communication frames.Whole communication process is initiated by primary module BU, and hardware address signal and bus communication signal are provided, and expansion module 1 can not initiatively send data.
In order to realize in the PLC between the primary module BU and each expansion module 1 that reliably logic is connected efficiently, the embodiment of the invention has defined the processing rule of address transfer unit 11 to its address signal that receives:
1. at first define finite aggregate S={X
1..., X
L, X
L+1, and comprise the sequence X of (L+1) individual element
1..., X
L, X
L+1Wherein, the element in the sequence belongs to S, and each element in the sequence all is the binary code of identical figure place, and does not repeat.
2. definition rule R is a kind of set of conversion, R={ (X
1, X
2), (X
2, X
3) ..., (X
I-1, X
i) ..., (X
L, X
L+1), (X
L+1, X
L+1).That is: each element in the above-mentioned sequence all can form an element that sorts in the sequence after leaning on according to regular R, can remember and make R (X
I-1)=X
i, and R (X
L)=X
L+1, R (X
L+1)=X
L+1Wherein, i≤L.
3. the element X in the regular R specified sequence
mAs expansion module 1 selection marker, wherein, m≤L.When each expansion module 1 transmits address number backward according to rule, also receive the address signal that sends, and make respective reaction.If key control unit 12 receives corresponding gating signal X
m, then just set up communication link between primary module BU and the respective stages expansion module 1, the signal of receiving when key control unit 12 is not gating signal X
mThe time, described communication link is cancelled.At this moment, can be used as preceding m binary code in the sequence geocoding of expansion module, when m=L, the scope maximum of geocoding.In the preferred embodiment of the present invention, definition m=L promptly specifies X
LAs expansion module 1 selection marker.
4. the element X in the regular R specified sequence
L+1Idle marker as expansion module 1.Rule definition: each expansion module 1 is received idle marker X
L+1The time, its address number that transmits backward just is this idle marker X always
L+1Like this, primary module BU powers on afterwards, sets up link and need provide idle marker X before and after the dismounting link
L+1, the key control unit 12 that makes all expansion modules 1 all no longer handles the communication data of autonomous module BU, and the communication buffer district is emptied.
5. construct a data list, be stored among the described primary module BU, be used to indicate described primary module BU
The corresponding expansion module of gating:
Table one:
Expansion module progression |
The primary module output signal |
First order expansion module |
X
L |
Second level expansion module |
X
L-1 |
_ |
_ |
L level expansion module |
X
1 |
Like this, obtain selection marker X in the PLC
LExpansion module 1 be unique.Enter idle condition after expansion module powers on, set up link and show that expansion module is selected afterwards, will be configured operations such as inquiry, input and output read-write according to the order of primary module BU, otherwise will keep idle condition.Primary module BU sets up after the link, will remove link when finishing visit or access exception, and this moment, expansion module 1 came back to idle condition, waits for communication next time.
According to the regular R of above-mentioned definition, primary module BU prepares will provide address number X when i level expansion module initiates to connect
L-i+1First order expansion module obtains address number X
L-i+1The back forms X according to regular R
L-i+2Transmit backward, by that analogy, i level expansion module will obtain address number X
LAnd according to regular R formation X
L+1Transmit backward, then the level expansion module will obtain signal X always
L+1Like this, has only i level expansion module in the expansion module by gating.
In the preferred embodiment of the present invention, according to the definable finite aggregate S={1000 of rule, 0100,0010,0001,0000}, and sequence 1000,0100,0010,0001,0000.Element in the sequence all is 4 binary codes, and does not have repeat element in the sequence.Set according to a kind of conversion of rule definition is: R={ (1000,0100), (0100,0010), (0010,0001), (0001,0000), (0000,0000) }.We specify 0001 selection marker as expansion module 1, specify 0000 idle marker as expansion module 1.
Construct a circuit as address transfer unit 11 (as shown in Figure 3) according to above-mentioned rule.Hypothesis key control unit 12 is the rising edge gating in this preferred embodiment.Wherein, address transfer unit 11 all comprises 4 input addressed line and 4 the output addressed line that are connected in series on the expansion bus.M bar input addressed line links to each other 2≤M≤4 with (M-1) bar output addressed line; Article 1, the input addressed line links to each other with the interrupting input end of described key control unit 12.And the 1st in the corresponding sequence of the signal of Input Address line input first of binary code.As can be known, available " right-shift operation " comes description rule R.
According to above-mentioned definition, as shown in Figure 3, like this, when the input end of the address of expansion module transfer unit was input as 0001, the input of the interrupting input end of its key control unit just was 1, thus the expansion module of gating correspondence.When the address signal of primary module BU output was 0000, the key control unit of all expansion modules all no longer handled the communication data of autonomous module BU, and the communication buffer district is emptied, and primary module BU is removed to the link of expansion module.The corresponding tables of the address signal of exporting when table two is depicted as expansion module and primary module BU addressing.By tabling look-up, primary module BU just can provide the address according to requirements for access.
Table two:
The expansion module numbering |
The address that should provide during the primary module addressing |
1 |
0001 |
2 |
0010 |
3 |
0100 |
4 |
1000 |
When idle |
0000 |
According to last table, when primary module BU need visit third level expansion module, just need provide address 0100.At this moment, first order expansion module obtains 0100, and second level expansion module obtains 0010, and third level expansion module obtains 0001, and fourth stage expansion module obtains 0000.According to previous definition, third level expansion module is chosen by primary module BU.
In other embodiments of the invention, can on the basis of Fig. 3 circuit, adopt other finite aggregate S and sequence to realize the present invention's control.Its principle is same as described above.In other embodiments of the invention, also shift transformation codings such as definable " figure place that moves to right is greater than 1 ", " shift left operation " are realized the present invention.Under " bit manipulation moves to left " rule, address transfer unit 11 can all comprise 4 Input Address lines and 4 OPADD lines.Wherein, M bar Input Address line links to each other with (M+1) bar OPADD line, 1≤M≤3; Article 4, the Input Address line links to each other with the interrupting input end of key control unit 12.And the 4th in the corresponding sequence of the signal of Input Address line input the 4th of binary code.Certainly, go back the definable figure place that moves to left and realize the present invention greater than 1 rule, wherein the circuit structure of address transfer unit 11 is similar to foregoing circuit.Therefore, can not limit protection scope of the present invention with the concrete definition of regular R and the fixedly connected mode of address transfer unit 11 middle connecting terminals.
As shown in Figure 4, in another preferred embodiment of the present invention, also comprise in the expansion module 1 being connected in series in Address Recognition unit 13 between input port and the key control unit 12, be used for the address signal of input is discerned, make that the input signal of working as described identification circuit is selection marker X
mThe time, m≤L, its scale-of-two gating signal of output (0 or 1) is to the key control unit of corresponding expansion module, when its input signal is idle marker X
L+1The time, its scale-of-two shutdown signal of output (1 or 0) is to described key control unit.Define m=L in this preferred embodiment, promptly specify X
LAs selection marker.
Among the present invention, address transfer unit 11 and Address Recognition unit 13 can be made of gate circuit, also can be integrated among CPLD (CPLD) or the FPGA (field programmable gate array), also can be integrated into address transfer unit 11 and Address Recognition unit 13 jointly among gate circuit or CPLD or the FPGA with other functional module.In other embodiments of the invention, address transfer unit 11, Address Recognition unit 13 and key control unit 12 can be integrated in a gate circuit or CPLD or the programmable gate array and realize.
We define finite aggregate S={000 earlier, and 001,010,011,100,101,110,111}, and sequence 000,001,010,011,100,101,110,111.Definition rule R is a kind of set of conversion, R={ (000,001), (001,010), (010,011), (011,100), (100,101), (101,110), (110,111), (111,111) }.Available " adding 1 operation " comes description rule R.We specify 110 selection markers as expansion module 1, specify 111 idle markers as expansion module 1.
As shown in Figure 5, the circuit of the
address transfer unit 11 that relates to according to above-mentioned rule by four with door, four not gates, four or form.Hypothesis
key control unit 12 is the negative edge gating in this preferred embodiment.Definition F[2..0] as the front end address signal of expansion module, R[2..0] be the rear end address signal of expansion module, in 2 to 0 corresponding S set of difference of these two signals 2 to 0 of the element binary code.Wherein, the interrupting input end of the
key control unit 12 in nINT and the
corresponding expansion module 1 links to each other, and also can be handled by hardware logic by CPLD or FPGA.Two not gates that link to each other with the nINT signal, two have constituted Address Recognition of the
present invention unit 13 with door.With R
0To R
2Signal and F
0To F
2Signal link to each other all with door, not gate and or door constituted address of the present invention transfer unit 11.As seen from the figure, R
2=F
2+ F
0F
1,
Meet the definition of above-mentioned rule.
According to above-mentioned definition, when the input end of the address of expansion module transfer unit was input as 110, the input signal nINT of the interrupting input end of its key control unit just was 0, thus the expansion module of gating correspondence.When the address signal of primary module BU output was 111, nINT was 1, and the key control unit of expansion module all no longer handles the communication data of autonomous module BU, and the communication buffer district is emptied, and primary module BU is removed to the link of expansion module.The corresponding tables of the address signal of exporting when table three is depicted as expansion module and primary module addressing.By tabling look-up, primary module BU just can provide the address according to requirements for access.Circuit shown in Fig. 5 promptly can be realized with separating component, also can use CPLD (CPLD) or the integrated realization of FPGA (field programmable gate array).
Table three:
The expansion module numbering |
The address that should provide during the primary module addressing |
1 |
110 |
2 |
101 |
3 |
100 |
4 |
011 |
5 |
010 |
6 |
001 |
7 |
000 |
When idle |
111 |
According to last table, when primary module BU need visit third level expansion module, just need provide address 100.At this moment, first order expansion module obtains 100, and second level expansion module obtains 101, and third level expansion module obtains 110, the four to the 7th grades of expansion modules and obtains 111.According to previous definition, third level expansion module is chosen by primary module BU.
In other embodiments of the invention, can adopt other finite aggregate S and sequence, or the binary code of a binary code and fixed value summation, or the binary code of binary code and a fixed value ask poor, 8421 yards, the realization of computer codes such as binary-coded decimal rule the present invention control.Its principle is to above-mentioned similar.Can select corresponding gate circuit to be achieved according to the rule of correspondence.Therefore, can not limit protection scope of the present invention with the specific implementation of the gate circuit of the concrete definition of regular R and address transfer unit and Address Recognition unit.
Among the present invention, can directly connect between each expansion module, also can connect through RC network.Described RC network is used for filtering.
In other embodiments of the invention, described address transfer unit and Address Recognition unit can not be encapsulated in the expansion module, address transfer unit and Address Recognition unit can be encapsulated as a module separately, or be encapsulated as module respectively, linking to each other with expansion module and primary module by the expansion bus in use gets final product.
In sum, the present invention has realized the addressing design of exempting to expansion module, and primary module can directly conduct interviews to expansion module by simple addressing.