CN109359073B - Inter-device communication method and device based on SPI bus - Google Patents
Inter-device communication method and device based on SPI bus Download PDFInfo
- Publication number
- CN109359073B CN109359073B CN201811086477.0A CN201811086477A CN109359073B CN 109359073 B CN109359073 B CN 109359073B CN 201811086477 A CN201811086477 A CN 201811086477A CN 109359073 B CN109359073 B CN 109359073B
- Authority
- CN
- China
- Prior art keywords
- slave
- master
- local address
- signal line
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 235000015429 Mirabilis expansa Nutrition 0.000 claims abstract 3
- 240000006116 Mirabilis expansa Species 0.000 claims abstract 3
- 235000013536 miso Nutrition 0.000 claims abstract 3
- 238000005516 engineering process Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 2
- 206010069794 Device issue Diseases 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006011 modification reaction Methods 0.000 description 1
- 230000002093 peripheral Effects 0.000 description 1
- 230000001360 synchronised Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
Abstract
The invention discloses an inter-equipment communication method and an equipment topological structure based on an SPI bus, wherein the method comprises the steps of adopting an SCLK signal line, an MOSI signal line and an MISO signal line to sequentially connect a master device and a plurality of slave devices in series; the master device controls each slave device to set a local address; when data is read or written, the master device sends an instruction containing address information and data information to all slave devices, the slave devices judge whether the address information is matched with the local address, if so, data reading or writing is carried out, otherwise, the slave devices analyze the data information and are in a bypass state. The invention realizes the determination of the slave equipment and the reading and writing of data by the equipment address addressing mode, simultaneously leads the master equipment to be capable of accessing any slave equipment in one period by the bypass technology and accessing all the slave equipment at the same time by the broadcasting mode, saves chip selection signal lines, reduces the occupied wiring space and ensures the access speed.
Description
Technical Field
The invention relates to the technical field of communication, in particular to an inter-device communication method and device based on an SPI bus.
Background
SPI (Serial Peripheral Interface) is a high-speed, full-duplex, synchronous Serial communication bus. SPI is a serial interface protocol that uses 4 signal lines for communication, including master/slave modes, typically a master device and one or more slave devices, where the 4 signal lines are an SCLK signal line (serial clock signal line), an MOSI signal line (master data output, slave data input signal line), a MISO signal line (master data input, slave data output signal line), and a CS signal line (chip select signal line), respectively.
The SPI bus only occupies four wires on the pins of the chip, when the master device is connected with one slave device, the pins of the chip can be saved, and the space of a PCB (printed circuit board) is saved during wiring. However, as the number of slave devices increases, the number of signal lines increases, and each time a slave device is added, a CS signal line needs to be added, which increases the wiring space and increases the cost.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides an inter-device communication method and device based on an SPI bus, which reduce the occupied wiring space.
In order to achieve the purpose, the invention provides the following technical scheme: an inter-device communication method based on an SPI bus comprises the following steps:
step S1, sequentially connecting a master device and a plurality of slave devices in series by adopting an SPI bus, wherein the SPI bus comprises an SCLK signal line, an MOSI signal line and a MISO signal line;
step S2, the master device controls each slave device to set a local address;
step S3, the master device reads data from the slave device or writes data into the slave device, and the master device sends an instruction containing address information and data information to all the slave devices;
step S4, the slave device judges whether the address information matches with the local address, if yes, step S5 is executed, otherwise, the slave device analyzes the data information in the instruction and makes the data information in the instruction in a bypass state;
in step S5, the slave device reads data and transmits the data to the master device or writes the data to the slave device.
Preferably, in step S2, the slave device setting the local address includes the steps of:
s201, the master device sends a command for setting the body address to the slave device;
s202, the slave device waits for receiving a non-zero value when receiving the command for setting the local address, takes the non-zero value as the local address, and adds one to the non-zero value and sends the non-zero value to the next-stage slave device.
Preferably, the slave device continuously sends zero to the next slave device when the slave device does not receive the non-zero value.
The invention also discloses a device based on the SPI bus, which comprises a master device and a plurality of slave devices, wherein the master device and the plurality of slave devices are sequentially connected in series through the SPI bus, and the SPI bus only comprises an SCLK signal line, an MOSI signal line and an MISO signal line.
Preferably, each slave device is provided with a local address, and the master device sets the local address by sending a set local address command to the slave device.
Preferably, each slave device is connected to an auxiliary device, each slave device being configured as an SPI bridge between the master device and the auxiliary device.
Preferably, when the SPI bridge function of the slave device is disabled, the slave device transmits the received address information directly to the next-stage slave device.
The invention has the beneficial effects that:
the communication method and the device between the devices based on the SPI bus only adopt an SCLK signal line, an MOSI signal line and an MISO signal line to connect the main device and a plurality of slave devices in series in sequence, and realize the determination of the slave devices and the data reading and writing in a device address addressing mode, simultaneously, the main device can access any slave device in a link in one period through a bypass technology, and can access all the slave devices at the same time through a broadcasting mode, thereby omitting a chip selection signal line, reducing the occupation of wiring space and simultaneously ensuring the access speed.
Drawings
FIG. 1 is a flow chart diagram of the method of inter-device communication of the present invention;
fig. 2 is a block diagram illustrating the structure of the present invention.
Detailed Description
The technical solution of the embodiment of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention.
The invention discloses a method and a device for communication among equipment based on an SPI bus, which only adopt an SCLK (Serial clock) signal line, an MOSI (Master Output/Slave Input ) signal line and an MISO (Master Input/Slave Output, Master data Input/Slave Output) signal line to connect the Master equipment and a plurality of Slave equipment in series in sequence, and realize the determination of the Slave equipment and the reading and writing of data through an equipment address addressing mode, thereby omitting a chip selection signal line and further reducing the occupation of wiring space.
As shown in fig. 1, an SPI bus based inter-device communication method includes the following steps:
step S1, sequentially connecting a master device and a plurality of slave devices in series by adopting an SPI bus, wherein the SPI bus comprises an SCLK signal line, an MOSI signal line and a MISO signal line;
specifically, in order to save the wiring space, in the present invention, the SPI bus only occupies three signal lines, namely, an SCLK signal line, an MOSI signal line, and a MISO signal line, on the pin of the Chip, and the master device and the plurality of slave devices are sequentially connected in series through the SCLK signal line, the MOSI signal line, and the MISO signal line, so that a CS (Chip Select) signal line (i.e., a Chip Select signal line) is omitted, and the problem that one CS signal line is correspondingly added for each device added in the prior art is avoided, thereby saving the wiring space and saving the cost. Wherein, the SCLK signal line is a serial clock signal line, and the serial clock signal is generated by the master device; MOSI signal line is the data output of the main equipment, the slave equipment data input signal line; the MISO signal line is the master data input, and the slave data output signal line.
The SPI buses are ultimately connected in series to form the topology shown in fig. 2. The master device and the first slave device, the first slave device and the second slave device, and so on, the N-1 th slave device and the nth slave device are all connected through the SCLK signal line, the MOSI signal line and the MISO signal line.
Step S2, the master device controls each slave device to set a local address;
in particular, since the CS signal line is omitted, when the slave device is determined, the slave device is determined by the device address addressing mode. Each slave device has a device address, hereinafter referred to as a local address, which can be set by the master device.
When a local address is set for each slave device, the master device can set a local address for each slave device through the command of setting the body address, wherein the format of the command of setting the local address is as follows:
0xA0- > n 0x00- >0xMM, MM being address data.
When the slave device receives a command for setting the local address, the slave device waits for receiving a non-zero value, takes the non-zero value as the local address, and adds one to the non-zero value and outputs the non-zero value to the next-stage slave device. When the slave device does not receive the non-zero value, the slave device always outputs zero to the next slave device.
Take the topology shown in fig. 2 as an example. When the master device sends a command for setting a local address, the first slave device first receives the command and waits for receiving a non-zero value, and if the received non-zero value is 2, the non-zero value 2 is used as the local address of the first slave device. Meanwhile, the first slave device adds one to the non-zero value 2 and outputs the value to the second slave device, that is, 3 is output to the second slave device, the second slave device takes the non-zero value 3 as a local address, adds one to the non-zero value 3 and outputs the value to the third slave device, and so on, the non-zero value received by the nth slave device is N +1, and therefore, the local address of the nth slave device is N + 1. In specific implementation, the local address is expressed by a 16-ary number.
Step S3, the master device reads data from the slave device or writes data into the slave device, and the master device sends an instruction containing address information and data information to all the slave devices;
step S4, the slave device judges whether the address information matches with the local address, if yes, step S5 is executed, otherwise, the slave device analyzes the data information in the instruction and makes the data information in the instruction in a bypass state;
in step S5, the slave device reads data and transmits the data to the master device or writes the data to the slave device.
Specifically, when the master device reads data from the slave devices, the master device has determined from which slave device the data is to be read, and the master device generates an instruction containing address information and data information to all the slave devices. As shown in fig. 2, the topology structure adopts a serial connection manner, and in a default case, the slave devices are in a Bypass (Bypass) state, and in one clock cycle, all the slave devices can receive the instruction sent by the master device, and the slave devices determine whether address information in the instruction matches the local address, and if not, continue to analyze data information in the instruction and continue to maintain the Bypass state. When the slave device judges that the address information matches the local address, the slave device does not continue to maintain the bypass state, and the slave device acquires data from the memory and transmits the data to the master device.
Similarly, when the master device writes data to the slave device, the master device has already determined which slave device to read the data to, and the master device generates an instruction containing address information and data information to the slave device. And if the address information in the instruction is not matched with the local address, continuously analyzing the data information in the instruction and continuously keeping the Bypass state. When the slave device judges that the address information matches the local address, the slave device is not continuing to maintain the bypass state, and the slave device writes data into the memory.
In this embodiment, when a slave device is in the bypass state, the instruction received by the slave device is directly transferred to the next slave device.
In specific implementation, the master device may send the following instructions to read data in the slave device:
0xAF- > local address- > register address- > register data, wherein localadress is a local address of slave equipment of data to be read, namely address information; the register address is an address for storing data to be read in the memory; the register data is data to be read, i.e., data information.
Likewise, the master may send a command to write data to the slave as follows:
0xAF- > local address- > register address- > register data, wherein localadress is a local address of slave equipment to be written with data, namely address information; register address is the memory address where the data to be written is stored; the register data is data to be written, i.e., data information.
As shown in fig. 2, the present invention further discloses an SPI bus-based device, which comprises a master device and a plurality of slave devices, wherein the master device and the plurality of slave devices are sequentially connected in series through an SPI bus, and the SPI bus comprises an SCLK signal line, an MOSI signal line, and a MISO signal line.
Specifically, the SPI bus only occupies three signal lines, namely, an SCLK signal line, an MOSI signal line and a MISO signal line, on the pin of the chip, and the master device and the plurality of slave devices are sequentially connected in series through the SCLK signal line, the MOSI signal line and the MISO signal line, thereby omitting a CS signal line, avoiding the problem that one CS signal line is correspondingly added for each device in the prior art, further saving the space for wiring, and saving the cost.
Further, each slave device has a device address, hereinafter referred to as a local address, which can be set by the following command:
0xA0- > n 0x00- >0xMM, MM being address data.
When the slave device receives a command for setting the local address, the slave device waits for receiving a non-zero value, takes the non-zero value as the local address, and adds one to the non-zero value and outputs the non-zero value to the next-stage slave device. When the slave device does not receive the non-zero value, the slave device always outputs zero to the next slave device.
As shown in fig. 2, after the master device issues the command for setting the local address, the first slave device first receives the command, and waits for receiving a non-zero value, and if the received non-zero value is 1, the non-zero value 1 is used as the local address of the first slave device. Meanwhile, the first slave device adds one to the non-zero value 1 and outputs the value to the second slave device, that is, 2 is output to the second slave device, the second slave device takes the non-zero value 2 as a local address, adds one to the non-zero value 2 and outputs the value to the third slave device, and so on, the non-zero value received by the nth slave device is N, and therefore, the local address of the nth slave device is N. In specific implementation, the local address is expressed by a 16-ary number.
Further, the invention carries out the determination of the slave device and the reading or writing of the data in a device address addressing mode. As shown in fig. 2, when the master device reads data from or writes data to the slave device, the master device generates an instruction containing address information and data information and transmits the instruction to the slave device. As shown in fig. 2, the topology structure adopts a serial connection manner, and in a default case, the slave devices are in a Bypass (Bypass) state, and in one clock cycle, all the slave devices can receive the instruction sent by the master device, and the slave devices determine whether address information in the instruction matches the local address, and if not, continue to analyze data information in the instruction and continue to maintain the Bypass state. When the slave device judges that the address information matches the local address, the slave device does not continue to maintain the bypass state, and the slave device performs reading or writing of data.
Further, each slave device may also communicate with an auxiliary device individually, in which case each slave device acts as an SPI bridge between the master device and the auxiliary device. When the SPI bridge function of a certain slave device is not enabled, the slave device does not match the received address information with the local information and directly sends the address information to the next-stage slave device.
In specific implementation, the master device may enable the SPI bridge function of a slave device by the following command:
0xA5- > local address- > open time, wherein the local address is a local address of a slave device of which the SPI bridge function is to be started; open time is the on-time, where the on-time is calculated in bytes. When local address is 0, the SPI bridge function of all slave devices is enabled. When the SPI bridge function of a slave is enabled, the master device may perform data interaction with the auxiliary device to which the slave device is connected.
Therefore, the scope of the present invention should not be limited to the disclosure of the embodiments, but includes various alternatives and modifications without departing from the scope of the present invention, which is defined by the claims of the present patent application.
Claims (5)
1. An inter-device communication method based on an SPI bus is characterized by comprising the following steps:
step S1, sequentially connecting a master device and a plurality of slave devices in series by using an SPI bus, where the SPI bus includes an SCLK signal line, an MOSI signal line, and a MISO signal line, each slave device is connected to an auxiliary device, each slave device is configured as an SPI bridge between the master device and the auxiliary device, and the SPI bridge function of the slave device is enabled by the following commands:
0xA5- > local address- > open time, wherein the local address is a local address of slave equipment of the SPI bridge function to be started, and the open time is the starting time;
step S2, the master device controls each slave device to set a local address;
step S3, the master device reads data from the slave device or writes data into the slave device, the master device sends an instruction containing address information and data information to all the slave devices, and when the SPI bridge function of the slave device is not enabled, the slave device directly sends the received address information to the next level of slave device;
step S4, the slave device judges whether the address information matches with the local address, if yes, step S5 is executed, otherwise, the slave device analyzes the data information in the instruction and is in a bypass state;
in step S5, the slave device reads data and transmits the data to the master device or writes the data to the slave device.
2. The method according to claim 1, wherein in step S2, the slave device setting the local address comprises the following steps:
s201, the master device sends a command for setting the body address to the slave device;
s202, the slave device waits for receiving a non-zero value when receiving a command for setting a local address, takes the non-zero value as the local address, and adds one to the non-zero value and sends the non-zero value to the next-stage slave device.
3. The method of claim 2, wherein the slave device continues to send zeros to the next slave device when it does not receive a non-zero value.
4. An apparatus based on SPI bus, characterized in that, including master device and several slave devices, said master device and several slave devices are connected in series in turn through SPI bus, said SPI bus includes SCLK signal line, MOSI signal line and MISO signal line, each slave device is connected with an auxiliary device, each slave device is configured as SPI bridge between master device and auxiliary device, SPI bridge function of slave device is enabled by following command:
0xA5- > local address- > open time, wherein the local address is a local address of slave equipment of the SPI bridge function to be started, and the open time is the starting time;
when the SPI bridge function of the slave device is not enabled, the slave device directly sends the received address information to the next-stage slave device.
5. The apparatus of claim 4, wherein each slave device is provided with a local address, and wherein the master device sets the local address by sending a set local address command to the slave device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811086477.0A CN109359073B (en) | 2018-09-18 | 2018-09-18 | Inter-device communication method and device based on SPI bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811086477.0A CN109359073B (en) | 2018-09-18 | 2018-09-18 | Inter-device communication method and device based on SPI bus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109359073A CN109359073A (en) | 2019-02-19 |
| CN109359073B true CN109359073B (en) | 2020-10-20 |
Family
ID=65351181
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811086477.0A Active CN109359073B (en) | 2018-09-18 | 2018-09-18 | Inter-device communication method and device based on SPI bus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109359073B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112965927B (en) * | 2021-03-18 | 2021-11-30 | 深圳市航顺芯片技术研发有限公司 | Signal driving system and method based on SPI equipment |
| CN114002994B (en) * | 2021-12-30 | 2022-04-22 | 菲尼克斯(南京)智能制造技术工程有限公司 | PLC-based system and networking and communication method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108255768A (en) * | 2017-12-01 | 2018-07-06 | 广东高云半导体科技股份有限公司 | A kind of link bridge circuit, communication system and method based on I3C |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7228373B2 (en) * | 2004-03-24 | 2007-06-05 | Analog Devices, Inc. | Serial digital communication system and method |
| CN201060487Y (en) * | 2007-05-29 | 2008-05-14 | 山东大学 | High speed configurable extension SPI bus |
| CN101067804B (en) * | 2007-05-29 | 2010-04-14 | 山东大学 | A high-speed configurable extended SPI bus and working method thereof |
| CN101146088A (en) * | 2007-10-25 | 2008-03-19 | 中山市晶威电子科技有限公司 | A data bus structure and data transmission method using this structure |
| DE102010041427A1 (en) * | 2010-09-27 | 2012-03-29 | Robert Bosch Gmbh | Method for transmitting data |
| CN107562666B (en) * | 2017-09-26 | 2020-10-23 | 威创集团股份有限公司 | Method, system and related device for communication between devices based on SPI bus |
-
2018
- 2018-09-18 CN CN201811086477.0A patent/CN109359073B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108255768A (en) * | 2017-12-01 | 2018-07-06 | 广东高云半导体科技股份有限公司 | A kind of link bridge circuit, communication system and method based on I3C |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109359073A (en) | 2019-02-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20210240355A1 (en) | Memory card and host device thereof | |
| US9798684B2 (en) | Bus communications with multi-device messaging | |
| US20070294440A1 (en) | Sd (Secure Digital) Card and Host Controller | |
| CN109359073B (en) | Inter-device communication method and device based on SPI bus | |
| CN107066746B (en) | Method for realizing PCA9555 function through CPLD based on I2C interface | |
| CN104834620A (en) | SPI (serial peripheral interface) bus circuit, realization method and electronic equipment | |
| US8495268B2 (en) | Card host LSI and set device including the same | |
| KR100787054B1 (en) | Control System for Same Address Device Using I2C Protocol | |
| JP4490837B2 (en) | Mobile device | |
| CN103577356B (en) | Realize the Apparatus and method for of IIC interface IP address extension | |
| CN103488600A (en) | Universal auxiliary machine synchronous serial interface circuit | |
| CN103064817A (en) | Simplified two-line serial data bus transport method | |
| US20140229641A1 (en) | Method and apparatus for latency reduction | |
| CN212229628U (en) | Slave device | |
| JP3477306B2 (en) | Extended input / output interface | |
| US20210297283A1 (en) | Master slave communication system capable of reducing manufacturing cost, electronic device, control method for master slave communication system, and control method for electronic device | |
| CN110990310B (en) | Device side SD controller, control method and electronic device | |
| CN114064554A (en) | Slave equipment and method for configuring MIPI (Mobile industry processor interface) line sequence thereof | |
| KR100295683B1 (en) | General call acknowledge apparatus and method for inter-integrated circuit | |
| CN113722261A (en) | Method for expanding chip selection number and enhancing flexibility of read-write response time by SPI | |
| CN111309665A (en) | Parallel write operation and read operation control system and method | |
| US6901472B2 (en) | Data-processing unit with a circuit arrangement for connecting a first communications bus with a second communications bus | |
| CN114124609A (en) | Communication device and communication method based on 1553B bus | |
| CN112783071A (en) | SDIO controller, FPGA board card and SDIO test system | |
| CN110795373A (en) | Method for converting I2C bus into parallel bus, terminal and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 518000 a1102, Shenzhen national engineering laboratory building, No. 20, Gaoxin South seventh Road, high tech Zone community, Yuehai street, Nanshan District, Shenzhen, Guangdong Patentee after: Howell touch and display technology (Shenzhen) Co.,Ltd. Address before: 518000 Room 601, east block, Haibin City, Wenxin 5th Road, Yuehai street, Nanshan District, Shenzhen City, Guangdong Province Patentee before: GIGADISPLAY SEMICONDUCTOR Co.,Ltd. |
|
| CP03 | Change of name, title or address | ||
| CP02 | Change in the address of a patent holder |
Address after: 2405, yuemeite building, No. 1, Gaoxin South seventh Road, high tech Zone community, Yuehai street, Nanshan District, Shenzhen, Guangdong 518000 Patentee after: Howell touch and display technology (Shenzhen) Co.,Ltd. Address before: 518000 a1102, Shenzhen national engineering laboratory building, No. 20, Gaoxin South seventh Road, high tech Zone community, Yuehai street, Nanshan District, Shenzhen, Guangdong Patentee before: Howell touch and display technology (Shenzhen) Co.,Ltd. |
|
| CP02 | Change in the address of a patent holder |