CN106326155B - A kind of multibus data record and playback reproducer and method - Google Patents
A kind of multibus data record and playback reproducer and method Download PDFInfo
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- CN106326155B CN106326155B CN201610697536.2A CN201610697536A CN106326155B CN 106326155 B CN106326155 B CN 106326155B CN 201610697536 A CN201610697536 A CN 201610697536A CN 106326155 B CN106326155 B CN 106326155B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F2003/0697—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers device management, e.g. handlers, drivers, I/O schedulers
Abstract
The invention discloses a kind of multibus data records and playback reproducer and method, the device is divided into digital data recording system and data playback system two parts, digital data recording system includes bus data input/output module, data processing module, data memory module, power module and indicating circuit, and data playback system includes data recording equipment and host computer.The data that wherein data processing module acquires bus data input/output module are handled, and comply with the format of storage agreement, and data are transmitted to next stage；Data memory module includes storage control and memory, completes the functions such as the data storage in record stage and the data retrieval of playback phase.The present invention supports RS485 bus, CAN bus, the independent data record or multibus of four kinds of bus systems of industry ethernet and FlexRay bus to record simultaneously, and it can realize the playback of recorded data, with the advantages that at low cost, the development cycle is short, high reliability and high efficiency.
Description
Technical field
The present invention relates to data record and playback technology field, especially a kind of multibus data record and playback reproducer and
Method.
Background technique
With the rapid development of electronic technology, the complexity of embedded system is higher and higher, and data traffic constantly increases
Greatly, bus type is also no longer single, meanwhile, the data information in bus is most important to the normal operation of system, by total
The analysis of line number evidence can very easily grasp the operation conditions of system.The record analysis to bus data is carried out, it will be in system
Debugging, fault diagnosis, fault location, shortening maintenance time etc. have a very big significance, especially in fault location, shortening dimension
Time etc. is repaired, is had important practical significance.On the other hand, system will appear various failures, but certain in development phase
The frequency of occurrences of a little failures is very low, if waiting these fault recurrences, needs long time, can greatly increase troubleshooting when
Between, but if the data of record can be played back, so that it may the artificial reproduction of the failure for the stage of record occur increases row
Except the probability of failure, shorten the development cycle.Therefore, the data record and playback for solving all kinds of buses become key technology.
Currently, domestic most of digital data recording system is designed for single bus, but have in same system
There are many case where different bus system to become increasingly common, since the agreement of different data bus use, interface, transmission are situated between
Matter is not quite similar, and single bus system is no longer satisfied to the bus data progress of same system while wanting for record
It asks.And bus recorder at this stage generally uses the high-cost solution such as FPGA and DSP, these high-cost solution party
Case is not suitable for the lower system of development cost.If in original solution only by core processor be changed to cost compared with
Low, the small processor of development difficulty does not adapt to the requirement of existing bus system data record then, especially remembers in a data
In the situation recorded simultaneously in recording system containing multiple bus, this solution is worthless.With bus data amount
Increase, the increase of bus data transfer speed, each link of single processor is likely to become the bottleneck of digital data recording system.
Summary of the invention
The purpose of the present invention is to provide a kind of multibus numbers at low cost, the development cycle is short, highly reliable and high-efficient
According to record and playback reproducer and method, to record RS485 bus, CAN bus, industry ethernet and FlexRay bus well
Data in four kinds of bus systems, and played back.
The technical solution for realizing the aim of the invention is as follows: a kind of multibus data record and playback reproducer, including data
Record system and data playback system, wherein digital data recording system include bus data input/output module, data processing module,
Data memory module, power module and indicating circuit, data playback system include data recording equipment and host computer；Wherein data
The data that processing module acquires bus data input/output module are handled, the data fit storage agreement that makes that treated
Format, and data are transmitted to next stage；Data memory module includes storage control and memory, completes the data in record stage
The data retrieval function of storage and playback phase；
Data recording stage, data storage carry out the reception and storage of data, entire mistake in the way of snakelike storage
Journey is controlled by data processing module, and data processing module will need the data stored to be sent to the currently active data storage mould
Block, data memory module receive and keep in data in memory, when data processing module is sent to data memory module
After data reach 2k byte, next storage control is activated, a upper storage control being activated starts data from depositing
It reads, and is stored in the corresponding page of Flash in reservoir, the currently active storage control starts to receive temporal data；
In the data readback stage, data processing and control module receives the information of host computer, and notification data memory module carries out
Meeting the retrieval of the data of feature, the load point respectively retrieved is returned to data processing module by data memory module,
Data processing module carries out the judgement of data starting point, and notifies the correct data starting point of each storage control, data storage
Module starts the transmission that data are carried out according to the sequence of regulation, and final data processing module will meet according to the original temporal of bus
The initial data of bus data feature is played back.
Further, the master controller of the data processing module selects 32 arm processor STM32F407ZET6.
Further, the bus data input/output module includes: 10M/100M Ethernet input output module, CAN
Bus input/output module, RS485 bus input/output module and FlexRay bus input/output module；Wherein 10M/100M
Ethernet input output module passes through RMII interface using physical chip LAN8720A and master controller STM32F407ZET6
It is connected, Ethernet interface selects the RJ45 interface of included network transformer；CAN bus input/output module is received using CAN bus
Hair device chip SN65HVD230DR is connected with the CAN1 of master controller STM32F407ZET6 mouth；RS485 bus module uses electricity
Flat conversion chip SP3485EN is connected with the USART3 interface of master controller STM32F407ZET6；Other bus ends in addition to network interface
Mouth is picked out using 20 needle connecting terminals, and every road bus pin is picked out using two terminals simultaneously.
Further, the data memory module is stored using 4 independent data storage cells, wherein each depositing
Storage unit has respective storage control chip STM32F407VET6, and primary storage medium is Nand Flash chip
K9WAG08U1A, capacity are 2G byte, and Data Buffer Memory selects ferroelectric memory FM25V02, capacity 256Kb；Respectively deposit
It stores up and is connected between module and master controller chip by parallel port, wherein data line is public, and control line, condition line are independent；Every number
According to the reserved serial ports all the way of memory module as standby port, the data of storage can directly be read from serial ports.
Further, the FlexRay bus input/output module is using the 16 of included two-way FlexRay bus control unit
Bit microprocessor MC9S12XF512 is extended by FlexRay bus transceiving chip TJA1080, wherein chip MC9S12XF512
It is connected with the USART6 of master controller chip STM32F407ZET6, carries out data exchange.
A kind of multibus data record and back method, steps are as follows:
Step 1, according to system task, divide multiple processors: data receiver is separate processor, is responsible for the reception of data
With encapsulation, and by packaged data transmission to data memory module, multiple storage controls of data memory module are controlled respectively
Make different storage regions；
Step 2, the determination of the data transfer mode between multiprocessor: according to processor division result, using two-way different
Walk buffering and transmission that FIFO carries out data；
Step 3, each bus receives the determination of mode when data receiver: the reception of multibus data uses DMA transfer mode
Cooperate with reception mode is interrupted；
Step 4, the determination of storage method when data store: according to the division of data memory module multiprocessor, snake is selected
The mode of shape storage, the i.e. reception and storage of two storage controls alternately data；
Step 5, data recording stage, data storage carry out the reception and storage of data in the way of snakelike storage,
Whole process is controlled by data processing module, and data processing module will need the data that store to be sent to the currently active data to deposit
Module is stored up, data memory module receives and keeps in data in memory, when data processing module is sent to data storage mould
After the data of block reach 2k byte, next storage control is activated, a upper storage control being activated starts data
It reads, and is stored in the corresponding page of Flash from memory, the currently active storage control starts to receive temporal data；
Step 6, the data readback stage, data processing and control module receives the information of host computer, and notification data stores mould
Block carries out the retrieval for meeting the data of feature, and the load point respectively retrieved is returned to data processing by data memory module
Module, data processing module carry out the judgement of data starting point, and notify the correct data starting point of each storage control, data
Memory module starts the transmission that data are carried out according to the sequence of regulation, and final data processing module will according to the original temporal of bus
The initial data for meeting bus data feature is played back.
Further, the determination of storage method when data described in step 4 store, specific as follows:
Data storage controller is divided into two storage controls, controls two memory spaces respectively, and the storage of data uses
The mode of snakelike storage；Wherein the first storage control receives the data of data receiver controller transmission, and data are temporarily stored in and are deposited
In reservoir, after data receiving processor transmits one page byte data, start to transmit data to the second storage control, the second storage
Controller starts to receive data and keep in, while paid-in data are written in Flash the first storage control.
Further, data memory module described in step 5 receives and keeps in data in memory, using maximum virtual
The method of frame, specific as follows: since one variable FrameLenMax of setting record the maximum frame length powering on, and controls to storage
When device processed sends data, when the sum of the data word joint number sent and FrameLenMax are more than or equal to Flash one page byte, recognize
It will appear truncation phenomenon for lower frame, stop transmitting data to the storage control, send and stop transportation protocol, turn to next deposit
Store up controller；As the data deficiencies 2K that storage control receives, but have been received by stop transportation protocol when, supply 2K byte with 0x00
Current page is written in data.
Compared with prior art, the present invention its remarkable advantage are as follows: (1) master controller uses at the ARM of Cortex-M4 core
Device is managed, dominant frequency 168MHz, each clock cycle is 5.95ns, therefore can provide higher bus data acquisition speed, is fitted
Answer the bus of higher speed；(2) multiple bus record system concentrates the field avoided on one system in multibus while record
Close use multiple and different bus data recording devices, have many advantages, such as it is small in size, it is easy for installation；(3) have FlexRay total
The data recording function of line, has stronger perspective, prepares for the universal of FlexRay network, is also existing
FlexRay network system provides the solution of bus data record and playback；(4) there is the playback function of bus data,
It can be conducive to the R&D cycle of shortening system with the fault point of quick positioning system；(5) relatively conventional arm processor is used,
With the features such as at low cost, research and development difficulty is small, and the R&D cycle is short, it is not only applicable to high-cost big system development, is also applied for
In lower-cost system, very big overhead can't be caused to original system, can promoted on a large scale；(6) multibus
Data record uses different controllers from playback reproducer data receiver and data storage controller, and two operating process can be true
Positive parallel processing improves the speed and reliability of whole system.
Present invention is further described in detail with reference to the accompanying drawing.
Detailed description of the invention
Fig. 1 is the overall system architecture of multibus data record and playback reproducer of the present invention.
Fig. 2 is the logic chart of bus of the present invention reception and data processing circuit.
Fig. 3 is the wiring diagram of bus input and output terminal of the invention.
Fig. 4 is that FlexRay bus data of the invention receives A channel circuit diagram.
Fig. 5 is single channel storage unit logic chart of the invention.
Fig. 6 is the connection circuit diagram of memory and storage control of the invention.
Fig. 7 is FlexRay bus control unit program flow diagram.
Fig. 8 is main data processor program flow chart.
Fig. 9 is that Data Integration and data are sent to storage control program flow diagram.
Figure 10 is data storage controller program flow diagram.
Specific embodiment
Multibus data record of the present invention and playback reproducer, including digital data recording system and data playback system, wherein counting
It include bus data input/output module, data processing module, data memory module, power module and instruction electricity according to record system
Road, data playback system include data recording equipment and host computer；Wherein data processing module is to bus data input and output mould
The data of block acquisition are handled, the format for the data fit storage agreement that makes that treated, and data are transmitted to next stage；Data
Memory module includes storage control and memory, completes the data retrieval function of the data storage and playback phase in record stage
Energy；
Data recording stage, data storage carry out the reception and storage of data, entire mistake in the way of snakelike storage
Journey is controlled by data processing module, and data processing module will need the data stored to be sent to the currently active data storage mould
Block, data memory module receive and keep in data in memory, when data processing module is sent to data memory module
After data reach 2k byte, next storage control is activated, a upper storage control being activated starts data from depositing
It reads, and is stored in the corresponding page of Flash in reservoir, the currently active storage control starts to receive temporal data；
In the data readback stage, data processing and control module receives the information of host computer, and notification data memory module carries out
Meeting the retrieval of the data of feature, the load point respectively retrieved is returned to data processing module by data memory module,
Data processing module carries out the judgement of data starting point, and notifies the correct data starting point of each storage control, data storage
Module starts the transmission that data are carried out according to the sequence of regulation, and final data processing module will meet according to the original temporal of bus
The initial data of bus data feature is played back.
Further, the master controller of the data processing module selects 32 arm processor STM32F407ZET6.
Further, the bus data input/output module includes: 10M/100M Ethernet input output module, CAN
Bus input/output module, RS485 bus input/output module and FlexRay bus input/output module；Wherein 10M/100M
Ethernet input output module passes through RMII interface using physical chip LAN8720A and master controller STM32F407ZET6
It is connected, Ethernet interface selects the RJ45 interface of included network transformer；CAN bus input/output module is received using CAN bus
Hair device chip SN65HVD230DR is connected with the CAN1 of master controller STM32F407ZET6 mouth；RS485 bus module uses electricity
Flat conversion chip SP3485EN is connected with the USART3 interface of master controller STM32F407ZET6；Other bus ends in addition to network interface
Mouth is picked out using 20 needle connecting terminals, and every road bus pin is picked out using two terminals simultaneously.
Further, the data memory module is stored using 4 independent data storage cells, wherein each depositing
Storage unit has respective storage control chip STM32F407VET6, and primary storage medium is Nand Flash chip
K9WAG08U1A, capacity are 2G byte, and Data Buffer Memory selects ferroelectric memory FM25V02, capacity 256Kb；Respectively deposit
It stores up and is connected between module and master controller chip by parallel port, wherein data line is public, and control line, condition line are independent；Every number
According to the reserved serial ports all the way of memory module as standby port, the data of storage can directly be read from serial ports.
Further, the FlexRay bus input/output module is using the 16 of included two-way FlexRay bus control unit
Bit microprocessor MC9S12XF512 is extended by FlexRay bus transceiving chip TJA1080, wherein chip MC9S12XF512
It is connected with the USART6 of master controller chip STM32F407ZET6, carries out data exchange.
A kind of multibus data record and back method, steps are as follows:
Step 1, according to system task, divide multiple processors: data receiver is separate processor, is responsible for the reception of data
With encapsulation, and by packaged data transmission to data memory module, multiple storage controls of data memory module are controlled respectively
Make different storage regions；
The main task of data logger includes the reception of bus data, the storage of bus data, but when uniprocessor, and two
A task can only be executed serially, constrain the speed of entire data logger significantly.The multiple tasks of data logger are given
Different processors can increase the speed of data logger, especially can obviously subtract in multibus data receiver with storage system
The leakage frame of small bus data frame.In this method, data receiver is separate processor, is responsible for the reception and encapsulation of data, and will envelope
The data transmission installed gives data storage processing device, and data storage is divided into two data storage controllers, controls two respectively not
Same storage region；
Data are received as individual processor, are responsible for the reception of bus data and the data transmission of data playback phase,
Bus data receives processor and reads in data from bus port, then by initial data frame storage frame structure as requested into
Row encapsulation, is eventually transferred to data storage controller.In view of the matching of speed between cost and each processor, and the system of programming
One property, processor select the same same series processors of producer.
Step 2, the determination of the data transfer mode between multiprocessor: according to processor division result, using two-way different
Walk buffering and transmission that FIFO carries out data；
This method uses two-way asynchronous FIFO chip between data receiving processor and data storage processor
IDT72V85 is as the data buffering between two processors.IDT72V85 supports the processor at both ends to operate the chip simultaneously,
And there is sky, half-full, full three kinds of status signals, when carrying out the transmission between data, data sending processing device only need to be by data
It is written in FIFO, data can be read until the free time by receiving processor, and send and receive to carry out simultaneously, increase
The program of processor runs independence.And IDT72V85 is high speed FIFO, is equivalent to SRAM, write-in and the speed read will not
Influence the operation of other programs.
Step 3, each bus receives the determination of mode when data receiver: the reception of multibus data uses DMA transfer mode
Cooperate with reception mode is interrupted；
For the uncertainty of bus data arrival time, this method selection is received mutually matched using DMA and interruption
Mode.The bus interface of no DMA function is set as interrupting receiving, and received interrupting by the DMA function of making full use of processor
Bus interface be set as highest priority response；
Step 4, the determination of storage method when data store: according to the division of data memory module multiprocessor, snake is selected
The mode of shape storage, the i.e. reception and storage of two storage controls alternately data；
Data storage controller is divided into two storage controls, controls two memory spaces respectively, and the storage of data uses
The mode of snakelike storage；Wherein the first storage control receives the data of data receiver controller transmission, and data are temporarily stored in and are deposited
In reservoir, after data receiving processor transmits one page byte data, start to transmit data to the second storage control, the second storage
Controller starts to receive data and keep in, while paid-in data are written in Flash the first storage control.Memory module
In two storage controls data receiver and data write-in Flash carry out simultaneously, solve current data recorder Flash and write
Enter slow bottleneck problem.
Step 5, data recording stage, data storage carry out the reception and storage of data in the way of snakelike storage,
Whole process is controlled by data processing module, and data processing module will need the data that store to be sent to the currently active data to deposit
Module is stored up, data memory module receives and keeps in data in memory, when data processing module is sent to data storage mould
After the data of block reach 2k byte, next storage control is activated, a upper storage control being activated starts data
It reads, and is stored in the corresponding page of Flash from memory, the currently active storage control starts to receive temporal data；
The data memory module receives and keeps in data in memory, in order to avoid there is the truncation of data frame,
I.e. same frame data are stored in the tail portion of a storage chip one page and the stem of next storage chip one page, using maximum empty
The method of quasi- frame, specific as follows: since one variable FrameLenMax of setting record the maximum frame length powering on, to storage
When controller sends data, when the sum of the data word joint number sent and FrameLenMax are more than or equal to Flash one page byte,
Think that lower frame will appear truncation phenomenon, stops transmitting data to the storage control, send and stop transportation protocol, turn to next
Storage control；As the data deficiencies 2K that storage control receives, but have been received by stop transportation protocol when, supply 2K word with 0x00
Current page is written in joint number evidence.
Step 6, the data readback stage, data processing and control module receives the information of host computer, and notification data stores mould
Block carries out the retrieval for meeting the data of feature, and the load point respectively retrieved is returned to data processing by data memory module
Module, data processing module carry out the judgement of data starting point, and notify the correct data starting point of each storage control, data
Memory module starts the transmission that data are carried out according to the sequence of regulation, and final data processing module will according to the original temporal of bus
The initial data for meeting bus data feature is played back.
The master-plan of multibus data logger of the present invention, specific as follows:
Using the multibus data logger of present method invention, bus interface includes RS485 bus, CAN bus,
FlexRay bus and Etherent bus, four kinds of buses are directly connected in bus and receive processor in addition to FlexRay bus
STM32F407ZET6, FlexRay bus use 16 high-performance arm processors for carrying two-way FlexRay bus control unit
MC9S12XF512 and bus are received and are connected between controller by spi bus, constitute the receiving module of whole system, are completed total
The reception of line number evidence and the transmission of playback phase data；Storage processor is STM32F407VET6, passes through the two-way FIFO of two panels
It is connected with data receiving processor, while manages two storages for respectively having two panels Nand Flash chip K9WAG08U1A to constitute
Space completes bus and receives the storage of data and the retrieval and transmission of playback phase data；The communication of system and host computer passes through
Ethernet is communicated with data receiving processor；When whole system is powered on by data receiving processor read GPS signal into
Row time service, and accurate time scale information is added to each initial data frame；The software of system uses modular design method, to not
Same processor, different functions are programmed respectively.
Embodiment 1
In conjunction with Fig. 1, multibus data record of the present invention and playback reproducer, digital data recording system and data playback system,
Middle digital data recording system includes bus data input/output module, data processing module, data memory module, power module and refers to
Show that circuit, data playback system include data recording equipment and host computer.Wherein data processing module inputs bus data defeated
The data of module acquisition are handled out, comply with the format of storage agreement, and the information such as markers are added in initial data,
It prepares for the retrieval and playback of data, data is finally transmitted to next stage.Data memory module includes storage control and deposits
Reservoir two parts complete the functions such as the data storage in record stage and the data retrieval of playback phase.Device does not add additionally
Battery give RTC circuit power supply, but read GPS signal when by powering on and give whole system time service, and record current geography
The information such as position coordinates.
Data recording stage, data storage carry out the reception and storage of data, entire mistake in the way of snakelike storage
Journey is controlled by data processing module, and data processing module will need the data stored to be sent to the currently active memory module, is deposited
Storage module receives and data is temporarily stored in ferroelectric memory, when the data that data processing module is sent to data memory module reach
To after 2k byte, next storage control is activated, a upper data storage controller being activated starts data from ferroelectricity
It reads, and is stored in Flash in corresponding page in memory, the currently active data storage controller starts to receive temporary number
According to.
In the data readback stage, data processing and control module receives the information of host computer, and notification data memory module carries out
Meeting the retrieval of the data of feature, the load point respectively retrieved is returned to data processing module by data memory module,
Data processing module carries out the judgement of data starting point, and notifies the correct data starting point of each storage control, and 4 data are deposited
Storage unit starts the transmission that data are carried out according to the sequence of regulation, and final data processing unit will be accorded with according to the original temporal of bus
The initial data for closing bus data feature is played back.
The master controller of the data processing module selects 32 arm processor STM32F407ZET6, the number of buses of system
According to input/output module and data processing module using the STM32F407ZET6 of STMicw Electronics as core, it is Cortex-M4
32 high-performance arm processors of core, dominant frequency reach as high as 168MHz, have been internally integrated serial ports, CAN, and Ethernet etc. is abundant
Numerous resources such as interface circuit and high-resolution timer.Data recording stage, it is defeated that STM32F407ZET6 controls data input
The data receiver of module out adds current time scale information in initial data, after addition stores required extra data information,
It is transmitted to data memory module controller.Data readback stage, STM32F407ZET6 receive the command information of host computer, and notify
Data storage controller starts the data that retrieval meets feature, judges the data start of data memory module passback, will be true
Positive initial position is transmitted to corresponding data storage controller, and data storage controller, which starts to transmit to data processing controller, to be believed
Breath, data processing controller start for data to be played back in corresponding bus according to the format that bus is arranged.
Configuration circuit is made of one six toggle switch and three keys, and wherein toggle switch is total for arranging data
The type that line currently needs to record indicates that FlexRay bus needs to record if first dial-up is 1；If second dial-up
Switch is 1, indicates that RS485 bus needs to record；If third position toggle switch is 1, indicate that CAN bus needs to record；If
4th dial-up is 1, indicates that industry ethernet needs to record.4-bit DIP switch can be any combination in addition to 0000,
5th toggle switch is that data receiver and data readback select dial-up, when being 0 for the 5th, system currently power on after for data
Otherwise the reception stage is the data readback stage.6th dial-up does not define temporarily, and the extension as program function is spare.It presses
Key 1 is defined as command key, if Nand Flash has expired when in use or has confirmed that the data being previously recorded are not used,
Nand Flash can be emptied, when Programmable detection is pressed to this key, start to remove all Nand Flash and deposit
Storage unit, device not can be carried out other work at this time.Key 2 is defined as starting to play back key, after data retrieval is completed, phase
The indicator light answered can light, and at this moment need this manually actuated key, and device just starts to bus playback of data.Key 3 is temporary
It does not define, the extension as program function is spare.
In conjunction with Fig. 2,3, bus data is received to be completed by the interface circuit of each bus of correspondence.The part is handled by bus data
Each bus interface of device connects corresponding electrical level transferring chip and constitutes, and wherein the data receiver introduction of FlexRay bus sees below section.
In order to facilitate wiring, the terminal of each bus there are two identical incoming end, only needed when connecting corresponding bus in this way by
Bus is divided into two sections in centre, is respectively connected in connecting terminal, avoids two buses of connection in a terminal hole, increases
The firmness of bus access, makes the present invention be suitable for severe working environment.
In conjunction with Fig. 4, since master controller STM32F407ZET6 does not integrate FlexRay bus control unit, the present invention is selected
16 high-performance arm processor MC9S12XF512 of the included two-way FlexRay bus control unit of Freescale company, with
FlexRay bus transceiver TJA1080 forms binary channels FlexRay and receives circuit.The circuit module is only completed the reception of data
And sending function, data are not handled, is communicated by serial ports with data processing unit controller, by data processing
Cell controller is unified to handle each bus data.
Master controller STM32F407ZET6 is internally integrated the ethernet medium access control (MAC) with DMA function Nei
Core is arranged to the address filtering of mixed mode, to transmit all frames.Physical chip LAN8720A is selected to pass through in the present invention
RMII interface is connect with main control chip, completes the monitoring of industry ethernet data.
It is only integrated with ethernet mac all the way inside master controller STM32F407VET6, the network interface needs communicated with host computer
Extension, the present invention select the devices at full hardware ICP/IP protocol stack network chips W 5500 for supporting SPI interface, and the network interface is for entirely filling
It sets and is communicated with host computer, the instruction including transmitting recorded data and reception host computer to host computer.
In conjunction with Fig. 5,6, data memory module is mainly by data storage controller, memory and data temporary storage location composition.
Storage unit of the invention is made of 4 Nand Flash K9WAG08U1A, and total capacity is 8G byte, and the storage of 8G byte is held
Amount is respectively by 4 storage control management.Multi-controller management increases the storage speed and data retrieval speed of this system,
And when data volume is less, the corresponding storage control unit of a bus can be stored separately, be conducive to data
Management.K9WAG08U1A is worked with page programming mode, that is, a piece of page area when receiving 2K byte in write-once Flash
Domain uses ferroelectric memory FM25V02 progress data buffer storage, preservation in the present invention to prevent unexpected power down from causing loss of data
The data in write-in Flash are had not enough time to when power down, increase the reliability of system.The reserved serial ports all the way of each data memory module
As standby port, the data of storage can not directly be read from outlet by master controller.
The 23rd foot PA0 of the 1st foot connection chip STM32F407VET6 of data buffer storage chip FM25V02, and pass through 10K
Pull-up resistor is connected to 3.3V power supply, and the 2nd foot is connected to the 31st foot of chip STM32F407VET6, the i.e. MISO of SPI1, and the 3rd
Foot connects the 24th foot PA1 of chip STM32F407VET6, and is connected to 3.3V power supply by 10K pull-up resistor, and the 4th foot is grounded,
The 32nd foot of 5th foot chip STM32F407VET6, the i.e. MOSI of SPI1, the 6th foot connect the 30 of chip STM32F407VET6
Foot, the i.e. SCK of SPI1, the 7th foot connects the 29th foot PA4 of chip STM32F407VET6, and is connected to by 5.1K pull-up resistor
3.3V power supply, the 8th foot connect 3.3V power supply.
By simultaneously port transmission between bus data processing module and data memory module, four storage controls share parallel port
Data line, but each storage control is connected by respective control line and condition line with master controller.Parallel port increases data
The speed of transmission.
In conjunction with Fig. 7, FlexRay data receiving processor only receives bus data in the bus data reception stage, and will count
According to master data processing controller is sent to, it is equivalent to a data acquisition controller；In playback phase, returning for primary processor is received
After putting order, starts to receive the data to be sent that master data processor is sent, simultaneously controlling bus data are received, in the corresponding time
Data to be sent are sent to bus.Playback and two stages of reception due to bus data will not be carried out in the same time,
The order of master controller is received in program in the incipient stage, and enters the corresponding stage, change data is such as needed to receive and play back
Stage then needs that system is placed in another stage to system electrification again.
In conjunction with Fig. 8,9, master data processor is the core of whole system, and entire program can be divided into two parts, and one is
The reception of data, one be data playback.Wherein the reception of data is that master data processor receives each number of buses in interruption
According to, the integration of progress data in major cycle, and transmit data to the storage control being currently active.Send data it
Before, the maximum frame length of current frame length and record can be compared, if the frame length of the frame is most than the data that have currently recorded
Big frame length is big, then the frame length of the frame is recorded as current maximum frame length.After transmitting received data, judges and be currently active
One page remaining space of memory whether be less than current maximum frame length, if grown up than current largest frames, then it is assumed that may under
Frame can cannot have same one page of memory and be truncated, and when this happens, system can the next storage control of activated in advance
It is supplied with 0xff in the space of device processed, current storage control deficiency one page.The playback of data is upon power-up of the system, to detect
Toggle switch is to prepare the order for receiving host computer after playback is arranged, will after receiving the playback feature frame of host computer transmission
The information is sent to each storage control by agreement, and storage control retrieves the memory space of oneself, meets what is retrieved
First frame data of feature are transferred to master data processor, and main process task judges that the first frame which storage control retrieves is true
Positive first frame, and the storage control where guiding the frame starts the data that transmission meets playback feature, master data processor
Bus data is received and received, is needing the time played back that the playback of data is completed in data readback to bus.
In conjunction with Figure 10, data storage controller writes data into Flash when receiving data expires 2k byte；In data
Playback phase retrieves the data for meeting feature of this storage region, and data are returned to main number by the guidance of master data processor
According to processor.
In conclusion multibus data record of the present invention and playback reproducer can recorde RS485 bus, CAN bus, ether
Data in four kinds of bus systems of network bus and FlexRay bus support the data record and multiple bus of single bus system
It is recorded while combination, and can realize the playback of recorded data under the cooperation of upper computer software, facilitate the failure of system fast
Speed positioning.
Claims (8)
1. a kind of multibus data record and playback reproducer, which is characterized in that including digital data recording system and data playback system,
Wherein digital data recording system include bus data input/output module, data processing module, data memory module, power module and
Indicating circuit, data playback system include data recording equipment and host computer；Wherein data processing module inputs bus data
The data of output module acquisition are handled, the format for the data fit storage agreement that makes that treated, and data are transmitted to next
Grade；Data memory module includes storage control and memory, completes the data of the data storage and playback phase in record stage
Search function；
Data recording stage, data memory module carry out the reception and storage of data, whole process in the way of snakelike storage
It being controlled by data processing module, data processing module will need the data stored to be sent to the currently active data memory module,
Data memory module receives and keeps in data in memory, when data processing module is sent to the data of data memory module
After reaching 2k byte, next storage control is activated, a upper storage control being activated starts data from memory
Middle reading, and be stored in the corresponding page of Flash, the currently active storage control starts to receive temporal data；
In the data readback stage, data processing module receives the information of host computer, and notification data memory module carries out meeting feature
Data retrieval, the load point respectively retrieved returns to data processing module, data processing by data memory module
Module carries out the judgement of data starting point, and notifies the correct data starting point of each storage control, and data memory module starts
The transmission of data is carried out according to the sequence of regulation, final data processing module will meet bus data according to the original temporal of bus
The initial data of feature is played back.
2. multibus data record according to claim 1 and playback reproducer, which is characterized in that the data processing module
Master controller select 32 arm processor STM32F407ZET6.
3. multibus data record according to claim 1 and playback reproducer, which is characterized in that the bus data input
Output module includes: 10M/100M Ethernet input output module, CAN bus input/output module, RS485 bus input and output
Module and FlexRay bus input/output module；Wherein 10M/100M Ethernet input output module uses physical chip
LAN8720A is connected with master controller STM32F407ZET6 by RMII interface, and Ethernet interface selects included network transformer
RJ45 interface；CAN bus input/output module uses CAN bus transponder chip SN65HVD230DR and master controller
The CAN1 mouth of STM32F407ZET6 is connected；RS485 bus module uses electrical level transferring chip SP3485EN and master controller
The USART3 interface of STM32F407ZET6 is connected；Other bus ports are picked out using 20 needle connecting terminals in addition to network interface, and every road is total
Wire pin is picked out using two terminals simultaneously.
4. multibus data record according to claim 1 and playback reproducer, which is characterized in that the data memory module
It is stored using 4 independent data storage cells, wherein each data storage cell has respective storage control core
Piece STM32F407VET6, primary storage medium are Nand Flash chip K9WAG08U1A, and capacity is 2G byte, and data buffering is deposited
Reservoir selects ferroelectric memory FM25V02, capacity 256Kb；By simultaneously between each data memory module and master controller chip
Mouth connection, wherein data line is public, and control line, condition line are independent；The reserved serial ports all the way of each data memory module is as spare
The data of port, storage can directly be read from serial ports.
5. multibus data record according to claim 3 and playback reproducer, which is characterized in that the FlexRay bus
Input/output module passes through FlexRay using the microprocessor of 16 bit MC9S12XF512 of included two-way FlexRay bus control unit
Bus transceiving chip TJA1080 extension, wherein chip MC9S12XF512 and master controller chip STM32F407ZET6
USART6 is connected, and carries out data exchange.
6. a kind of multibus data record and back method, which is characterized in that steps are as follows:
Step 1, according to system task, divide multiple processors: data receiver is separate processor, is responsible for the reception and envelope of data
Dress, and by packaged data transmission to data memory module, multiple storage controls of data memory module control not respectively
Same storage region；
Step 2, the determination of the data transfer mode between multiprocessor: according to processor division result, using two-way asynchronous
The buffering and transmission of FIFO progress data；
Step 3, each bus receives the determination of mode when data receiver: the reception of multibus data is using DMA transfer mode in
The cooperation of disconnecting debit's formula；
Step 4, the determination of storage method when data store: according to the division of data memory module multiprocessor, snakelike deposit is selected
The mode of storage, the i.e. reception and storage of two storage controls alternately data；
Step 5, data recording stage, data memory module carries out the reception and storage of data in the way of snakelike storage, whole
A process is controlled by data processing module, and data processing module will need the data stored to be sent to the currently active data storage
Module, data memory module receive and keep in data in memory, when data processing module is sent to data memory module
Data reach 2k byte after, activate next storage control, a upper storage control being activated start by data from
It reads, and is stored in the corresponding page of Flash in memory, the currently active storage control starts to receive temporal data；
Step 6, the data readback stage, data processing module receives the information of host computer, and notification data memory module is accorded with
The retrieval of the data of feature is closed, the load point respectively retrieved is returned to data processing module by data memory module, number
The judgement of data starting point is carried out according to processing module, and notifies the correct data starting point of each storage control, and data store mould
BOB(beginning of block) carries out the transmission of data according to the sequence of regulation, and final data processing module will meet always according to the original temporal of bus
The initial data of line data characteristics is played back.
7. multibus data record according to claim 6 and back method, which is characterized in that data described in step 4 are deposited
The determination of storage method when storage, specific as follows:
Data storage controller is divided into two storage controls, controls two memory spaces respectively, the storage of data is using snakelike
The mode of storage；Wherein the first storage control receives the data of data receiver controller transmission, and data are temporarily stored in memory
In, after data receiving processor transmits one page byte data, start to transmit data to the second storage control, the second storage control
Device starts to receive data and keep in, while paid-in data are written in Flash the first storage control.
8. multibus data record according to claim 6 and back method, which is characterized in that data described in step 5 are deposited
Module is stored up to receive and keep in data in memory, it is specific as follows using the method for maximum virtual frames: one variable of setting
Since FrameLenMax record maximum frame length powering on, when sending data to storage control, the data byte that has sent
When the sum of several and FrameLenMax is more than or equal to Flash one page byte, it is believed that lower frame will appear truncation phenomenon, stop depositing to this
It stores up controller and transmits data, send and stop transportation protocol, turn to next storage control；When the data that storage control receives
It less than 2K, but has been received by when stopping transportation protocol, supplies 2K byte data with 0x00, current page is written.
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| CN107239418B (en) * | 2017-06-02 | 2021-06-18 | 中国航发南方工业有限公司 | Data storage module read-write device and I2C communication method |
| CN107526704A (en) * | 2017-08-15 | 2017-12-29 | 成都普诺科技有限公司 | Motion platform contextual data gathers playback system |
| CN109955239B (en) * | 2017-12-22 | 2021-04-16 | 合肥欣奕华智能机器有限公司 | Distributed control system and robot equipment |
| CN109960183B (en) * | 2017-12-22 | 2020-10-23 | 合肥欣奕华智能机器有限公司 | Distributed control system and robot equipment |
| US10564858B2 (en) * | 2018-05-02 | 2020-02-18 | Nyquist Semiconductor Limited | Data storage device with selective connection to non-volatile memories |
| CN109582232A (en) * | 2018-11-21 | 2019-04-05 | 中国船舶重工集团公司第七0七研究所 | A kind of sequence read-write multi-disc Flash system and method based on FPGA |
| CN110321300A (en) * | 2019-05-20 | 2019-10-11 | 中国船舶重工集团公司第七一五研究所 | A kind of implementation method of signal processing data high-speed record and playback module |
| CN110996031B (en) * | 2019-11-22 | 2021-11-16 | 天津津航计算技术研究所 | Data recording and playback device based on Ethernet and SRIO |
| CN110996032B (en) * | 2019-11-22 | 2021-11-16 | 天津津航计算技术研究所 | Data recording and playback method based on Ethernet and SRIO |
| CN111324567B (en) * | 2020-02-10 | 2022-05-27 | 华大半导体有限公司 | Method for realizing serial port communication and single chip microcomputer system |
| CN111580491A (en) * | 2020-04-30 | 2020-08-25 | 中国航发哈尔滨东安发动机有限公司 | Novel switching value signal recording, storing and replaying method and system based on PLC |
| CN112562121A (en) * | 2020-12-30 | 2021-03-26 | 洛阳伟信电子科技有限公司 | Storage data and rapid downloading method based on SRIO protocol |
| CN113014462A (en) * | 2021-02-22 | 2021-06-22 | 上海节卡机器人科技有限公司 | Data conversion method, device, controller and circuit thereof |
| CN113590037A (en) * | 2021-07-26 | 2021-11-02 | 中国船舶重工集团公司第七0三研究所 | Data recording method for simultaneously recording CAN protocol data and Modbus protocol data |
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