CN106326155A - Multi-bus data recording and playback device and method - Google Patents
Multi-bus data recording and playback device and method Download PDFInfo
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- CN106326155A CN106326155A CN201610697536.2A CN201610697536A CN106326155A CN 106326155 A CN106326155 A CN 106326155A CN 201610697536 A CN201610697536 A CN 201610697536A CN 106326155 A CN106326155 A CN 106326155A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F2003/0697—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers device management, e.g. handlers, drivers, I/O schedulers
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Abstract
The invention discloses a multi-bus data recording and playback device and method. The device consists of a data recording system and a data playback system, wherein the data recording system comprises a bus data input and output module, a data processing module, a data storage module, a power supply module and an indicating circuit, and the data playback system comprises a data recording device and an upper computer. The data processing module is used for processing data collected by the bus data input and output module, so as to enable the data to confirm to a format of a storage protocol, and sending the data to a next level; the data storage module comprises a storage controller and a storage, and is used for completing the functions such as data storage of a recording phase and data retrieval of a playback phase. The device and method support single data recording or multi-bus simultaneous recording of four bus systems including an RS485 bus, a CAN bus, an Ethernet bus and a FlexRay bus, can realize the playback of recorded data, and has the advantages of low cost, short development period, high reliability, high efficiency and the like.
Description
Technical field
The present invention relates to data record and playback technology field, particularly a kind of multibus data record and playback reproducer and
Method.
Background technology
Along with developing rapidly of electronic technology, the complexity of embedded system is more and more higher, and data traffic constantly increases
Greatly, bus type is the most single, meanwhile, and properly functioning most important, by always to system of the data message in bus
The analysis of line data can grasp the operation conditions of system very easily.Carry out the record analysis to bus data, will be in system
The aspects such as debugging, fault diagnosis, fault location, shortening maintenance time have a very big significance, especially in fault location, shorten dimension
Repair the aspects such as time, there is critically important practical significance.On the other hand, system there will be various fault in development, but certain
The frequency of occurrences of a little faults is the lowest, if waiting these fault recurrences, needs long time, can be greatly increased failture evacuation time
Between, but if the data of record can play back, it is possible to by reproduction artificial for the fault of record stage appearance, increase row
Except the probability of fault, shorten the construction cycle.Therefore, the data record solving all kinds of bus becomes key technology with playback.
At present, domestic most of digital data recording system designs for single bus, but has in same system
The situation having multiple different bus system becomes increasingly common, due to different pieces of information bus use agreement, interface, transmission be situated between
Matter is not quite similar, and what single bus system can not meet that the bus data to same system records simultaneously wants
Ask.And the bus monitor of present stage commonly uses the solution of the high costs such as FPGA and DSP, the solution party of these high costs
Case is not suitable for the system that development cost is relatively low.If only core processor being replaced by cost relatively in original solution
Low, that development difficulty is little processor, does not the most adapt to the requirement of existing bus system data record, especially remembers data
Containing in the situation that multiple bus records simultaneously in recording system, this solution is worthless.Along with bus data amount
Increasing, the increase of bus data transfer speed, each link of single processor is likely to become the bottleneck of digital data recording system
Summary of the invention
It is an object of the invention to provide that a kind of low cost, construction cycle be short, highly reliable and the much higher number of buses of efficiency
According to record and playback reproducer and method, with well record RS485 bus, CAN, industry ethernet and FlexRay bus
Data in four kinds of bus systems, and play back.
The technical solution realizing the object of the invention is: a kind of multibus data record and playback reproducer, including data
Record system and data playback system, wherein digital data recording system include bus data input/output module, data processing module,
Data memory module, power module and indicating circuit, data playback system includes data recording equipment and host computer；Wherein data
The data of bus data input/output module collection are processed by processing module, make the storage agreement of the data fit after process
Form, and data are transmitted to next stage；Data memory module includes storage control and memorizer, completes the data in record stage
Storage and the data retrieval function of playback phase；
Data recording stage, data storage carries out reception and the storage of data, whole mistake according to the mode of snakelike storage
Journey is by data processing module control, and the data needing storage are sent to the currently active data storage mould by data processing module
Block, data memory module receives and data is kept in memory, when data processing module is sent to data memory module
After data reach 2k byte, activating next storage control, a upper storage control being activated starts data from depositing
Reading in reservoir, and be stored in the corresponding page of Flash, the currently active storage control starts to receive temporal data；
In the data readback stage, data processing and control module receives the information of host computer, and notifies that data memory module is carried out
Meeting the retrieval of the data of feature, the load point each retrieved is returned to data processing module by data memory module,
Data processing module carries out the judgement of data starting point, and notifies the data starting point that each storage control is correct, and data store
Module starts to carry out the transmission of data according to the order of regulation, and final data processing module will meet according to the original temporal of bus
The initial data of bus data feature plays back.
Further, 32 arm processor STM32F407ZET6 selected by the master controller of described data processing module.
Further, described bus data input/output module includes: 10M/100M Ethernet input/output module, CAN
Bus input/output module, RS485 bus input/output module and FlexRay bus input/output module；Wherein 10M/100M
Ethernet input/output module uses physical chip LAN8720A and master controller STM32F407ZET6 by RMII interface phase
Even, Ethernet interface selects the RJ45 interface carrying network transformer；CAN input/output module uses CAN transmitting-receiving
The CAN1 mouth of device chip SN65HVD230DR and master controller STM32F407ZET6 is connected；RS485 bus module uses level to turn
The USART3 interface changing chip SP3485EN and master controller STM32F407ZET6 is connected；In addition to network interface, other bus ports make
Picking out with 20 pin binding posts, every road bus pin uses two terminals to pick out simultaneously.
Further, described data memory module uses 4 independent data storage cells to store, and the most each deposits
Storage unit has respective storage control chip STM32F407VET6, and primary storage medium is Nand Flash chip
K9WAG08U1A, capacity is 2G byte, and Data Buffer Memory selects ferroelectric memory FM25V02, and capacity is 256Kb；Respectively deposit
Storage module is connected by parallel port between master controller chip, and wherein data wire is public, and control line, condition line are independent；Every number
Reserve a road serial ports according to memory module can directly read from serial ports as standby port, the data of storage.
Further, described FlexRay bus input/output module uses and carries the 16 of two-way FlexRay bus control unit
Bit microprocessor MC9S12XF512 by FlexRay bus transceiving chip TJA1080 extend, its chips MC9S12XF512 with
The USART6 of master controller chip STM32F407ZET6 is connected, and carries out data exchange.
A kind of multibus data record and back method, step is as follows:
Step 1, according to system task, divides multiple processor: data receiver is separate processor, is responsible for the reception of data
With encapsulation, and sending packaged data to data memory module, multiple storage controls of data memory module are controlled respectively
Make different memory areas；
Step 2, the determination of the data transfer mode between multiprocessor: according to processor division result, use two-way different
Step FIFO carries out buffering and the transmission of data；
Step 3, during data receiver, each bus receives the determination of mode: the reception of multibus data uses DMA transfer mode
Coordinate with interrupting reception mode；
Step 4, the determination of storage method during data storage: according to the division of data memory module multiprocessor, select Serpentis
The mode of shape storage, the reception of i.e. two storage control alternately data and storage；
Step 5, data recording stage, data storage carries out reception and the storage of data according to the mode of snakelike storage,
Whole process is by data processing module control, and the data needing storage are sent to the currently active data and deposit by data processing module
Storage module, data memory module receives and data is kept in memory, when data processing module is sent to data storage mould
After the data of block reach 2k byte, activating next storage control, a upper storage control being activated starts data
Reading from memorizer, and be stored in the corresponding page of Flash, the currently active storage control starts to receive temporal data；
Step 6, in the data readback stage, data processing and control module receives the information of host computer, and notifies that data store mould
Block carries out meeting the retrieval of the data of feature, and the load point each retrieved is returned to data and processes by data memory module
Module, data processing module carries out the judgement of data starting point, and notifies the data starting point that each storage control is correct, data
Memory module starts to carry out the transmission of data according to the order of regulation, and final data processing module will according to the original temporal of bus
The initial data meeting bus data feature plays back.
Further, the determination of storage method during data storage described in step 4, specific as follows:
Data storage controller is divided into two storage controls, controls two memory spaces respectively, and the storage of data uses
The mode of snakelike storage；Wherein the first storage control receives the data that data receiver controller transmits, and data is temporarily stored in and deposits
In reservoir, after data receiving processor transmits one page byte data, start to transmit data, the second storage to the second storage control
Controller starts receive data and keep in, and the first storage control is by paid-in data write Flash simultaneously.
Further, data memory module described in step 5 receives and data is kept in memory, uses maximum virtual
The method of frame, specific as follows: the variable FrameLenMax record maximum frame length from the beginning that powers on is set, to storage control
When device processed sends data, when the data word joint number sent is more than or equal to Flash one page byte with FrameLenMax sum, recognize
There will be for lower frame and block phenomenon, stop transmitting data to this storage control, send and stop transportation protocol, turn to the next one to deposit
Storage controller；When data deficiencies 2K that storage control receives, but when having been received by stopping transportation protocol, supply 2K byte with 0x00
Data, write current page.
Compared with prior art, its remarkable advantage is the present invention: (1) master controller uses the ARM process of Cortex-M4 core
Device, dominant frequency is 168MHz, and each clock cycle is 5.95ns, therefore can provide higher bus data acquisition speed, adapts to
The bus of more speed；(2) multiple bus record system is concentrated on one system, it is to avoid in the occasion that multibus records simultaneously
Use multiple different bus data recording equipment, there is volume little, the advantage such as easy for installation；(3) there is FlexRay bus
Data recording function, has stronger perspective, and universal for FlexRay network prepares, and is also existing FlexRay net
Network system provides the solution of bus data record and playback；(4) there is the playback function of bus data, can quickly determine
The trouble point of position system, the R&D cycle of beneficially shortening system；(5) use relatively conventional arm processor, there is cost
Low, research and development difficulty is little, and the features such as the R&D cycle is short are not only applicable to the big system development of high cost, are also applied for cost relatively low
System in, can't give original system cause the biggest overhead, can promote on a large scale；(6) multibus data record
Use different controllers from playback reproducer data receiver and data storage controller, what two operating process can be real is parallel
Process, improve speed and the reliability of whole system.
Below in conjunction with the accompanying drawings the present invention is described in further detail.
Accompanying drawing explanation
Fig. 1 is the system general frame figure of multibus data record of the present invention and playback reproducer.
Fig. 2 is the logic chart that bus of the present invention receives with data processing circuit.
Fig. 3 is the wiring diagram of the bus input and output terminal of the present invention.
Fig. 4 is that the FlexRay bus data of the present invention receives A channel circuit diagram.
Fig. 5 is the single channel memory element logic chart of the present invention.
Fig. 6 is the memorizer connection circuit diagram with storage control of the present invention.
Fig. 7 is FlexRay bus control unit program flow diagram.
Fig. 8 is master data processor program flow diagram.
Fig. 9 is that Data Integration and data send to storage control program flow diagram.
Figure 10 is data storage controller program flow diagram.
Detailed description of the invention
Multibus data record of the present invention and playback reproducer, including digital data recording system and data playback system, wherein count
Bus data input/output module, data processing module, data memory module, power module and instruction electricity is included according to record system
Road, data playback system includes data recording equipment and host computer；Wherein data processing module is to bus data input and output mould
The data of block collection process, and make the form of the storage agreement of the data fit after process, and data are transmitted to next stage；Data
Memory module includes storage control and memorizer, completes data storage and the data retrieval merit of playback phase in record stage
Energy；
Data recording stage, data storage carries out reception and the storage of data, whole mistake according to the mode of snakelike storage
Journey is by data processing module control, and the data needing storage are sent to the currently active data storage mould by data processing module
Block, data memory module receives and data is kept in memory, when data processing module is sent to data memory module
After data reach 2k byte, activating next storage control, a upper storage control being activated starts data from depositing
Reading in reservoir, and be stored in the corresponding page of Flash, the currently active storage control starts to receive temporal data；
In the data readback stage, data processing and control module receives the information of host computer, and notifies that data memory module is carried out
Meeting the retrieval of the data of feature, the load point each retrieved is returned to data processing module by data memory module,
Data processing module carries out the judgement of data starting point, and notifies the data starting point that each storage control is correct, and data store
Module starts to carry out the transmission of data according to the order of regulation, and final data processing module will meet according to the original temporal of bus
The initial data of bus data feature plays back.
Further, 32 arm processor STM32F407ZET6 selected by the master controller of described data processing module.
Further, described bus data input/output module includes: 10M/100M Ethernet input/output module, CAN
Bus input/output module, RS485 bus input/output module and FlexRay bus input/output module；Wherein 10M/100M
Ethernet input/output module uses physical chip LAN8720A and master controller STM32F407ZET6 by RMII interface phase
Even, Ethernet interface selects the RJ45 interface carrying network transformer；CAN input/output module uses CAN transmitting-receiving
The CAN1 mouth of device chip SN65HVD230DR and master controller STM32F407ZET6 is connected；RS485 bus module uses level to turn
The USART3 interface changing chip SP3485EN and master controller STM32F407ZET6 is connected；In addition to network interface, other bus ports make
Picking out with 20 pin binding posts, every road bus pin uses two terminals to pick out simultaneously.
Further, described data memory module uses 4 independent data storage cells to store, and the most each deposits
Storage unit has respective storage control chip STM32F407VET6, and primary storage medium is Nand Flash chip
K9WAG08U1A, capacity is 2G byte, and Data Buffer Memory selects ferroelectric memory FM25V02, and capacity is 256Kb；Respectively deposit
Storage module is connected by parallel port between master controller chip, and wherein data wire is public, and control line, condition line are independent；Every number
Reserve a road serial ports according to memory module can directly read from serial ports as standby port, the data of storage.
Further, described FlexRay bus input/output module uses and carries the 16 of two-way FlexRay bus control unit
Bit microprocessor MC9S12XF512 by FlexRay bus transceiving chip TJA1080 extend, its chips MC9S12XF512 with
The USART6 of master controller chip STM32F407ZET6 is connected, and carries out data exchange.
A kind of multibus data record and back method, step is as follows:
Step 1, according to system task, divides multiple processor: data receiver is separate processor, is responsible for the reception of data
With encapsulation, and sending packaged data to data memory module, multiple storage controls of data memory module are controlled respectively
Make different memory areas；
The main task of data logger includes the reception of bus data, the storage of bus data, but during uniprocessor, two
Individual task can only perform in serial, significantly constrains the speed of whole data logger.Multiple tasks of data logger are given
Different processors, can increase the speed of data logger, especially can substantially subtract in multibus data receiver with storage system
The leakage frame of little bus data frame.In this method, data receiver is separate processor, is responsible for reception and the encapsulation of data, and will envelope
The data installed send data storage processing device to, and data storage is divided into two data storage controllers, control two respectively not
Same memory area；
Data be received as single processor, be responsible for the data transmission of the reception of bus data and data playback phase,
Bus data receives processor and data is read in from bus port, is then entered by initial data frame storage frame structure as requested
Row encapsulation, is eventually transferred to data storage controller.In view of the coupling of speed between cost and each processor, and the system of programming
One property, processor selects the same series processors of same producer.
Step 2, the determination of the data transfer mode between multiprocessor: according to processor division result, use two-way different
Step FIFO carries out buffering and the transmission of data；
This method stores at data receiving processor and data and uses two-way asynchronous FIFO chip between processor
IDT72V85 is as the data buffering between two processors.IDT72V85 supports that the processor at two ends operates this chip simultaneously,
And there is sky, half-full, full three kinds of status signals, when the transmission carried out between data, data sending processing device only need to be by data
In write FIFO, receive processor and can read data when idle, send and receive and can not simultaneously carry out, increase
The program of processor runs independence.And IDT72V85 is high speed FIFO, being equivalent to SRAM, the speed writing and reading will not
Affect the operation of other programs.
Step 3, during data receiver, each bus receives the determination of mode: the reception of multibus data uses DMA transfer mode
Coordinate with interrupting reception mode；
For the uncertainty of the bus data time of advent, this method selects use DMA and interrupt what reception cooperated
Mode.Make full use of the DMA function of processor, be set to the EBI not having DMA function interrupt receiving, and interruption is received
EBI be set to limit priority response；
Step 4, the determination of storage method during data storage: according to the division of data memory module multiprocessor, select Serpentis
The mode of shape storage, the reception of i.e. two storage control alternately data and storage；
Data storage controller is divided into two storage controls, controls two memory spaces respectively, and the storage of data uses
The mode of snakelike storage；Wherein the first storage control receives the data that data receiver controller transmits, and data is temporarily stored in and deposits
In reservoir, after data receiving processor transmits one page byte data, start to transmit data, the second storage to the second storage control
Controller starts receive data and keep in, and the first storage control is by paid-in data write Flash simultaneously.Memory module
In the data receiver of two storage controls and data write Flash carry out simultaneously, solve current data monitor Flash and write
Enter slow bottleneck problem.
Step 5, data recording stage, data storage carries out reception and the storage of data according to the mode of snakelike storage,
Whole process is by data processing module control, and the data needing storage are sent to the currently active data and deposit by data processing module
Storage module, data memory module receives and data is kept in memory, when data processing module is sent to data storage mould
After the data of block reach 2k byte, activating next storage control, a upper storage control being activated starts data
Reading from memorizer, and be stored in the corresponding page of Flash, the currently active storage control starts to receive temporal data；
Described data memory module receives and data is kept in memory, in order to avoid blocking of Frame occurs,
The most same frame data are stored in afterbody and the stem of next storage chip one page of a storage chip one page, use extreme deficiency syndrome
The method intending frame, specific as follows: the variable FrameLenMax record maximum frame length from the beginning that powers on is set, to storage
When controller sends data, when the data word joint number sent is more than or equal to Flash one page byte with FrameLenMax sum,
Think that lower frame there will be and block phenomenon, stop transmitting data to this storage control, send and stop transportation protocol, turn to the next one
Storage control；When data deficiencies 2K that storage control receives, but when having been received by stopping transportation protocol, supply 2K word with 0x00
Joint number evidence, writes current page.
Step 6, in the data readback stage, data processing and control module receives the information of host computer, and notifies that data store mould
Block carries out meeting the retrieval of the data of feature, and the load point each retrieved is returned to data and processes by data memory module
Module, data processing module carries out the judgement of data starting point, and notifies the data starting point that each storage control is correct, data
Memory module starts to carry out the transmission of data according to the order of regulation, and final data processing module will according to the original temporal of bus
The initial data meeting bus data feature plays back.
The master-plan of multibus data logger of the present invention, specific as follows:
Using the multibus data logger of present method invention, EBI includes RS485 bus, CAN,
FlexRay bus and Etherent bus, four kinds of buses, in addition to FlexRay bus, are directly connected in bus and receive processor
STM32F407ZET6, FlexRay bus uses 16 the high-performance arm processors carrying two-way FlexRay bus control unit
MC9S12XF512 is received with bus and is connected by spi bus between controller, constitutes the receiver module of whole system, completes total
The reception of line data and the transmission of playback phase data；Storage processor is STM32F407VET6, by the two-way FIFO of two panels with
Data receiving processor is connected, and management two simultaneously is respectively arranged with the storage sky that two panels Nand Flash chip K9WAG08U1A is constituted
Between, complete bus and receive the storage of data and the retrieval of playback phase data and transmission；The communication of system and host computer by with
Too net communicates with data receiving processor；Read gps signal by data receiving processor when whole system is powered on to carry out
Time service, and add time scale information accurately to each initial data frame；The software of system uses modular design method, to difference
Processor, different functions programs respectively.
Embodiment 1
In conjunction with Fig. 1, multibus data record of the present invention and playback reproducer, digital data recording system and data playback system, its
Middle digital data recording system includes bus data input/output module, data processing module, data memory module, power module and refers to
Show that circuit, data playback system include data recording equipment and host computer.Wherein data processing module is defeated to bus data input
The data going out module collection process so that it is meet the form of storage agreement, and add the information such as markers in initial data,
Retrieval and playback for data are prepared, and data are transmitted to next stage the most at last.Data memory module includes storage control and deposits
Reservoir two parts, complete the function such as the data storage in record stage and the data retrieval of playback phase.Device does not add additionally
Battery power to RTC circuit, but read gps signal during by powering on to whole system time service, and record current geography
The information such as position coordinates.
Data recording stage, data storage carries out reception and the storage of data, whole mistake according to the mode of snakelike storage
The data needing storage are sent to the currently active memory module by data processing module control, data processing module, are deposited by journey
Storage module receives and also data is temporarily stored in ferroelectric memory, reaches when data processing module is sent to the data of data memory module
After 2k byte, activating next storage control, a upper data storage controller being activated starts data from ferroelectricity
Reading in memorizer, and be stored in Flash in corresponding page, the currently active data storage controller starts to receive temporary number
According to.
In the data readback stage, data processing and control module receives the information of host computer, and notifies that data memory module is carried out
Meeting the retrieval of the data of feature, the load point each retrieved is returned to data processing module by data memory module,
Data processing module carries out the judgement of data starting point, and notifies that the data starting point that each storage control is correct, 4 data are deposited
Storage unit starts to carry out the transmission of data according to the order of regulation, and final data processing unit will symbol according to the original temporal of bus
The initial data closing bus data feature plays back.
The master controller of described data processing module selects 32 arm processor STM32F407ZET6, the number of buses of system
According to input/output module and data processing module with the STM32F407ZET6 of STMicw Electronics as core, it is Cortex-M4 core
32 high-performance arm processors, abundant the connecing such as dominant frequency reaches as high as 168MHz, has been internally integrated serial ports, CAN, Ethernet
Mouthful circuit, and numerous resources such as high-resolution timer.Data recording stage, STM32F407ZET6 controls data input and output
The data receiver of module, adds current time scale information in initial data, after adding the excessive data information needed for storage, passes
To data memory module controller.In the data readback stage, STM32F407ZET6 receives the command information of host computer, and notifies number
Start to retrieve the data meeting feature according to storage control, it is judged that the data start of data memory module passback, will be real
Original position pass to corresponding data storage controller, data storage controller start to data processing controller transmission letter
Breath, data processing controller starts to be played back in corresponding bus data according to the form that bus is arranged.
Configuration circuit is made up of toggle switch and three buttons of one six, and wherein toggle switch is total for appointment data
Line is currently needed for the type of record, if first dial-up is 1, represents FlexRay bus requirements record；If second dial-up
Switch is 1, represents RS485 bus requirements record；If the 3rd toggle switch is 1, represent that CAN needs record；If
4th dial-up is 1, represents that industry ethernet needs record.4-bit DIP switch can be the combination in any in addition to 0000,
5th toggle switch is data receiver and data readback selection dial-up, and when being 0 for the 5th, system is data after currently powering on
The reception stage, otherwise for the data readback stage.6th dial-up does not the most define, and the extension as program function is standby.Press
Key 1 is defined as command key, if Nand Flash is the fullest or confirms the data the most not use being previously recorded,
Nand Flash can be emptied, when Programmable detection to this button is pressed, start to remove all of Nand Flash and deposit
Storage unit, now device can not carry out other work.Button 2 is defined as starting to play back button, after data retrieval completes, and phase
The display lamp answered can light, and at this moment needs this button manually actuated, and device just starts to bus playback of data.Button 3 is temporary transient
Not definition, the extension as program function is standby.
In conjunction with Fig. 2,3, bus data receive completed by the interface circuit of corresponding each bus.This part is processed by bus data
Each EBI of device connects corresponding electrical level transferring chip and constitutes, the wherein data receiver introduction section of seeing below of FlexRay bus.
Wiring for convenience, the terminal of each bus all has two identical incoming ends, so have only to when connecting corresponding bus by
Bus be divided into two sections in centre, be respectively connected in binding post, it is to avoid a terminal hole connects two buses, adds
The firmness that bus accesses, makes the present invention be suitable for severe working environment.
In conjunction with Fig. 4, owing to master controller STM32F407ZET6 does not has integrated FlexRay bus control unit, the present invention selects
16 the high-performance arm processor MC9S12XF512 carrying two-way FlexRay bus control unit of Freescale company, with
FlexRay bus transceiver TJA1080 composition dual pathways FlexRay receives circuit.This circuit module is only completed the reception of data
And sending function, data are not processed, communicated with data processing unit controller by serial ports, data process
Each bus data is processed by cell controller unification.
Master controller STM32F407ZET6 is internally integrated in ethernet medium access control (MAC) with DMA function
Core, is arranged to the address filtering of mixed model, to transmit all frames.The present invention select physical chip LAN8720A pass through
RMII interface is connected with main control chip, completes the monitoring of industry ethernet data.
A road ethernet mac only it is integrated with, the network interface needs communicated with host computer inside master controller STM32F407VET6
Extension, the present invention selects the devices at full hardware ICP/IP protocol stack network chips W 5500 supporting SPI interface, and this network interface is used for whole dress
Put and communicate with host computer, including the data the most recorded to host computer transmission and the instruction of reception host computer.
In conjunction with Fig. 5,6, data memory module mainly by data storage controller, memorizer and data temporary storage location composition.
The memory element of the present invention is made up of 4 Nand Flash K9WAG08U1A, and total capacity is 8G byte, and the storage of 8G byte is held
Amount is respectively by 4 storage control management.Multi-controller management adds storage speed and the data retrieval speed of this system,
And when data volume is less, corresponding for a bus storage control unit can be stored separately, beneficially data
Management.K9WAG08U1A works with page programming mode, a piece of page district in write-once Flash when i.e. receiving 2K byte
Territory, for preventing unexpected power down from causing loss of data, uses ferroelectric memory FM25V02 to carry out data buffer storage, preserves in the present invention
Have not enough time to during power down write the data in Flash, increase the reliability of system.Each data memory module reserves a road serial ports
As standby port, the data of storage can not pass through master controller, directly reads from outlet.
1st foot of data buffer storage chip FM25V02 connects the 23rd foot PA0 of chip STM32F407VET6, and passes through 10K
Pull-up resistor is connected to 3.3V power supply, and the 2nd foot is connected to the MISO of the 31st foot of chip STM32F407VET6, i.e. SPI1, and the 3rd
Foot connects the 24th foot PA1 of chip STM32F407VET6, and is connected to 3.3V power supply by 10K pull-up resistor, the 4th foot ground connection,
32nd foot of the 5th foot chip STM32F407VET6, i.e. the MOSI of SPI1, the 6th foot connects 30 feet of chip STM32F407VET6,
The SCK of i.e. SPI1, the 7th foot connects chip STM32F407VET6 the 29th foot PA4, and is connected to 3.3V by 5.1K pull-up resistor
Power supply, the 8th foot connects 3.3V power supply.
By also port transmission between bus data processing module and data memory module, four storage controls share parallel port
Data wire, but each storage control is connected with master controller with condition line by respective control line.Parallel port adds data
The speed of transmission.
Bus data is only received in the bus data reception stage in conjunction with Fig. 7, FlexRay data receiving processor, and by number
According to being sent to master data processing controller, be equivalent to a data acquisition controller；In playback phase, receive returning of primary processor
After putting order, start to receive the data to be sent that master data processor sends, receive and controlling bus data, in the corresponding time
Data to be sent are sent to bus.Owing to playback and two stages of reception of bus data will not be carried out in the same time,
Program receives in the incipient stage order of master controller, and enters the corresponding stage, if desired for conversion data receiver and playback
Stage, then need, again to system electrification, system to be placed in another stage.
In conjunction with Fig. 8,9, master data processor is the core of whole system, and whole program can be divided into two parts, and one is
The reception of data, one is the playback of data.Wherein the reception of data is that master data processor receives each number of buses in interruption
According to, major cycle carries out the integration of data, and transmits data to the storage control being currently active.Send data it
Before, the maximum frame length of current frame length with record can be compared, if the frame length of this frame is than the data currently recorded
Big frame length is big, then the frame length of this frame is recorded as current maximum frame length.After transmitting the data received, can judge to be currently active
One page remaining space of memorizer whether less than current maximum frame length, if grown up than current largest frames, then it is assumed that under may
Can not there is same one page of memorizer and block in frame, when this happens, system can the storage control of the activated in advance next one
Device processed, the space 0xff of current storage control deficiency one page supplies.The playback of data is upon power-up of the system, detects
Toggle switch is after playback is arranged, and prepares to receive the order of host computer, after receiving the playback feature frame that host computer transmits, and will
This information is sent to each storage control by agreement, and the memory space of storage control retrieval oneself, by meeting of retrieving
First frame data of feature are transferred to master data processor, and main process judges that the first frame which storage control retrieves is true
The first positive frame, and guide the storage control at this frame place to start to transmit the data meeting playback feature, master data processor
Receive and receive bus data, in the time needing playback, by data readback to bus, completing the playback of data.
In conjunction with Figure 10, data storage controller, when receiving the full 2k byte of data, writes data in Flash；In data
Playback phase retrieves the data meeting feature of this memory area, and by data by master data processor lead back to pass to main number
According to processor.
In sum, multibus data record of the present invention and playback reproducer can record RS485 bus, CAN, ether
Data on network bus and four kinds of bus systems of FlexRay bus, support data record and the multiple bus of single bus system
Record while combination, and the playback of recorded data can be realized under the cooperation of upper computer software, the fault facilitating system is fast
Speed location.
Claims (8)
1. a multibus data record and playback reproducer, it is characterised in that include digital data recording system and data playback system,
Wherein digital data recording system include bus data input/output module, data processing module, data memory module, power module and
Indicating circuit, data playback system includes data recording equipment and host computer；Wherein bus data is inputted by data processing module
The data of output module collection process, and make the form of the storage agreement of the data fit after process, and data are transmitted to next
Level；Data memory module includes storage control and memorizer, completes data storage and the data of playback phase in record stage
Search function；
Data recording stage, data storage carries out reception and the storage of data according to the mode of snakelike storage, whole process by
Data processing module controls, and the data needing storage are sent to the currently active data memory module by data processing module, number
Receive according to memory module and by temporary for data in memory, reach when data processing module is sent to the data of data memory module
After 2k byte, activating next storage control, a upper storage control being activated starts data from memorizer
Reading, and be stored in the corresponding page of Flash, the currently active storage control starts to receive temporal data；
In the data readback stage, data processing and control module receives the information of host computer, and notifies that data memory module meets
The retrieval of the data of feature, the load point each retrieved is returned to data processing module, data by data memory module
Processing module carries out the judgement of data starting point, and notifies the data starting point that each storage control is correct, data memory module
Starting to carry out the transmission of data according to the order of regulation, final data processing module will meet bus according to the original temporal of bus
The initial data of data characteristics plays back.
Multibus data record the most according to claim 1 and playback reproducer, it is characterised in that described data processing module
Master controller select 32 arm processor STM32F407ZET6.
Multibus data record the most according to claim 1 and playback reproducer, it is characterised in that described bus data inputs
Output module includes: 10M/100M Ethernet input/output module, CAN input/output module, RS485 bus input and output
Module and FlexRay bus input/output module；Wherein 10M/100M Ethernet input/output module uses physical chip
LAN8720A is connected by RMII interface with master controller STM32F407ZET6, and Ethernet interface is selected and carried network transformer
RJ45 interface；CAN input/output module uses CAN transponder chip SN65HVD230DR and master controller
The CAN1 mouth of STM32F407ZET6 is connected；RS485 bus module uses electrical level transferring chip SP3485EN and master controller
The USART3 interface of STM32F407ZET6 is connected；In addition to network interface, other bus ports use 20 pin binding posts to pick out, and every road is total
Wire pin uses two terminals to pick out simultaneously.
Multibus data record the most according to claim 1 and playback reproducer, it is characterised in that described data memory module
Using 4 independent data storage cells to store, the most each memory element has respective storage control chip
STM32F407VET6, primary storage medium is Nand Flash chip K9WAG08U1A, and capacity is 2G byte, and data buffering stores
Ferroelectric memory FM25V02 selected by device, and capacity is 256Kb；It is connected by parallel port between each memory module with master controller chip,
Wherein data wire is public, and control line, condition line are independent；Each data memory module reserves a road serial ports as standby port, deposits
The data of storage can directly read from serial ports.
Multibus data record the most according to claim 3 and playback reproducer, it is characterised in that described FlexRay bus
Input/output module uses the microprocessor of 16 bit MC9S12XF512 carrying two-way FlexRay bus control unit to pass through FlexRay
Bus transceiving chip TJA1080 extends, and its chips MC9S12XF512 is with master controller chip STM32F407ZET6's
USART6 is connected, and carries out data exchange.
6. a multibus data record and back method, it is characterised in that step is as follows:
Step 1, according to system task, divides multiple processor: data receiver is separate processor, is responsible for reception and the envelope of data
Dress, and send packaged data to data memory module, multiple storage controls of data memory module control not respectively
Same memory area；
Step 2, the determination of the data transfer mode between multiprocessor: according to processor division result, use two-way asynchronous
FIFO carries out buffering and the transmission of data；
Step 3, during data receiver, each bus receives the determination of mode: the reception of multibus data use DMA transfer mode with in
Disconnecting debit's formula coordinates；
Step 4, the determination of storage method during data storage: according to the division of data memory module multiprocessor, select snakelike depositing
The mode of storage, the reception of i.e. two storage control alternately data and storage；
Step 5, data recording stage, data storage carries out reception and the storage of data according to the mode of snakelike storage, whole
Process is by data processing module control, and the data needing storage are sent to the currently active data storage mould by data processing module
Block, data memory module receives and data is kept in memory, when data processing module is sent to data memory module
After data reach 2k byte, activating next storage control, a upper storage control being activated starts data from depositing
Reading in reservoir, and be stored in the corresponding page of Flash, the currently active storage control starts to receive temporal data；
Step 6, in the data readback stage, data processing and control module receives the information of host computer, and notifies that data memory module enters
Row meets the retrieval of the data of feature, and the load point each retrieved is returned to data and processes mould by data memory module
Block, data processing module carries out the judgement of data starting point, and notifies the data starting point that each storage control is correct, and data are deposited
Storage module starts to carry out the transmission of data according to the order of regulation, and final data processing module will symbol according to the original temporal of bus
The initial data closing bus data feature plays back.
Multibus data record the most according to claim 6 and back method, it is characterised in that described in step 4, data are deposited
The determination of method is stored during storage, specific as follows:
Data storage controller is divided into two storage controls, controls two memory spaces respectively, and the storage of data uses snakelike
The mode of storage；Wherein the first storage control receives the data that data receiver controller transmits, and data are temporarily stored in memorizer
In, after data receiving processor transmits one page byte data, starting to transmit data to the second storage control, the second storage controls
Device starts receive data and keep in, and the first storage control is by paid-in data write Flash simultaneously.
Multibus data record the most according to claim 6 and back method, it is characterised in that described in step 5, data are deposited
Storage module receives and data is kept in memory, the method using maximum virtual frames, specific as follows: to arrange a variable
FrameLenMax record is from the maximum frame length started that powers on, when sending data to storage control, the data byte sent
Number with FrameLenMax sum more than or equal to Flash one page byte time, it is believed that lower frame there will be and blocks phenomenon, stops depositing to this
Storage controller transmits data, sends and stops transportation protocol, turns to next storage control；When the data that storage control receives
Less than 2K, but when having been received by stopping transportation protocol, supply 2K byte data with 0x00, write current page.
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